JP2001060589A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain desired electrical characteristics by preventing dishing and making the thickness of copper films in a groove wiring equal to each other by forming another planarizing pattern in a wiring pattern section. SOLUTION: After a Cu film 106 is electroplated, a positive photoresist having a film thickness of 1 μm is applied to the surface of the film 106 as a photosensitive material 107. A KrF excimer laser beam 110 is irradiated upon the upper part of groove wiring, and the photosensitive material is developed with an alkaline solution. Only in the groove wiring section, a Cu film 111, having a thickness of 0.4 μm corresponding to a step 109, is deposited by performing a second plating process for about 50 seconds under the condition of 20 mA/cm2. Through this plating process, a pattern formed of the Cu film 111 is grown on the groove pattern, having a width which is broader than a prescribed value. When the second electroplating is performed, a flat Cu film is no longer able to be formed, because Cu films grow from the side walls of the groove wiring and thick Cu films of the sidewalls. After the second electroplating, the photoresist is removed. Consequently, a flat Cu film having no step is formed before chemical and mechanical polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a metal film in a groove previously formed in an insulating film and removing metal other than the groove using chemical mechanical polishing. And a method of manufacturing a semiconductor device for forming wiring.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices become more highly integrated and operate at higher speeds, fine processing technology has become a very important issue. In particular, for wiring through which current flows, its resistance value,
It is known that electromigration resistance and a processed shape affect the performance of a semiconductor device.

Until now, aluminum has been mainly used as a wiring material for semiconductor devices, and the wiring has been processed by dry etching. However, the use of aluminum as a wiring material with high integration and high speed has caused the following problems. For example, the density of the current flowing through the wiring is increased due to the reduced wiring width. Then, the temperature of the aluminum in the wiring having a high resistance rises. As the temperature of the wiring increases, the wiring resistance further increases and the electromigration resistance decreases.

Therefore, the resistance is lower than that of aluminum.
Copper having good electromigration resistance has been used as a wiring material. Regarding the processing of copper wiring, dry etching of copper is difficult, so filling a groove formed in an insulating film in advance with a metal film and forming a wiring by removing metal other than the groove using chemical mechanical polishing, The so-called damascene method is used.

FIG. 7 is a sectional view showing a manufacturing process of a conventional semiconductor device. In FIG. 7, 1 is a semiconductor substrate, 2 is a silicon oxide film, 3 is a trench wiring, and 4 is a tantalum nitride (hereinafter, referred to as tantalum nitride).
TaN) film, 5 is a seed film made of copper (hereinafter, Cu), 6
Indicates a Cu film formed by a plating method. First,
As shown in FIG. 7A, a groove pattern 3 having a wiring pattern is formed in a silicon oxide film 2 on a semiconductor substrate 1 by dry etching. Next, as shown in FIG. 7B, a TaN film 4 and a Cu film 5 are formed on the silicon oxide film 2 by a sputtering method. After the TaN film 4 and the Cu film 5 are formed, a Cu film 6 is deposited by a plating method, as shown in FIG. Next, the groove 3 is formed by a chemical mechanical polishing method.
By removing the other metals, an embedded wiring as shown in FIG. 7D is formed.

[0006]

However, according to the conventional method, a step 9 is formed in the Cu film 6 in a wide trench wiring region of, for example, 1 μm or more as shown in FIG. As shown in (d), more metal is removed from the wide groove wiring portion. Therefore, a so-called dishing state occurs in which the metal film thickness in the groove wiring portion which is wider than the film thickness of the metal film in the narrow groove wiring portion becomes thin and becomes concave. FIG. 8 shows the relationship between the width of the wiring groove and the dishing. The dishing amount is the amount of depression at the center of the wiring width. If the wiring width is less than 1 μm, the dishing amount is 2
The amount is not more than 0 nm and does not cause any problem. However, when the wiring groove width is 1 μm or more, the dishing amount sharply increases. Since the thickness of the wiring is 400-500 nm,
When the wiring width is, for example, 10 μm, the dishing amount is close to 10% of the wiring film thickness.

When dishing occurs, the wiring cross-sectional area of the wide groove wiring portion becomes smaller than a design value, and therefore, when a semiconductor device is used as designed, the current density increases. Therefore, there arise problems such as an increase in the temperature of the wiring and an increase in the electric resistance or a deterioration in the electromigration resistance. In an extreme case, Cu may not be present at the center of the wide groove pattern. Therefore, when forming the Cu film by the electrolytic plating and the chemical mechanical polishing process, it is a very important issue to keep the wiring film thickness as designed.

[0008] Regarding this problem, see, for example, Japanese Patent Laid-Open No. 6-318.
No. 590 discloses a method of forming a wide wiring pattern, leaving an insulating film in a columnar or slit shape in the wide wiring pattern, and then embedding a metal and performing chemical mechanical polishing. However, according to this method, since columns and slits made of an insulating film remain inside a wide wiring pattern, there arise problems such as a change in wiring resistance and a restriction on the arrangement of via holes connecting the upper layer wiring. .

According to the present invention, in a wiring layer of a semiconductor device in which a wide wiring area and a narrow wiring area are mixed, dishing after chemical mechanical polishing is prevented, so that copper in a wide wiring wiring and a narrow wiring groove is formed. It is an object of the present invention to make film thicknesses equal and to obtain desired electric characteristics.

[0010]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention provides a method of forming a trench wiring by embedding, further forming another flattening pattern in a wiring pattern portion having a predetermined width or more. By doing so, the opening area of the wide wiring pattern portion is substantially reduced, and a wide step is not generated on the substrate surface before performing the chemical mechanical polishing. Here, the pattern formed in the wiring pattern portion is formed of the same type as the metal used for the embedded wiring.

In the method of manufacturing a semiconductor device according to the present invention, an opening pattern made of a photosensitive material is formed in a wide wiring pattern having a predetermined width or more, and a metal film such as copper or a copper alloy is formed as a mask by plating, for example. By selectively forming a film in the pattern, the metal film thickness on the wide wiring before chemical mechanical polishing is increased, the metal film thickness on the parts other than the wide wiring part is made equal, and the inside of the wide groove wiring after polishing is increased. In other words, dishing is eliminated.

Further, according to the method of manufacturing a semiconductor device of the present invention, a pattern made of a photosensitive material is formed in a wide wiring pattern having a predetermined value or more, and a metal film is formed thereon.
After flattening by a chemical mechanical polishing method to expose a pattern made of a photosensitive material and removing the pattern made of the photosensitive material, an opening area of a wide wiring pattern is substantially reduced, and then a metal film is formed. By performing chemical mechanical polishing, the metal film inside the wide trench wiring after polishing is reduced, that is, dishing is eliminated.

As apparent from FIG. 8, the wiring pattern having a predetermined value or more is preferably a wiring pattern having a size of 1 μm or more.

As a method of additionally forming a second pattern in a wide wiring pattern, for example, Japanese Patent Laid-Open No.
-189506. This is to prevent dishing by forming a film having a low polishing rate on an insulating film to be embedded between wirings and then performing chemical mechanical polishing. This prior example uses a film different from the insulating film used for filling, and differs from the present invention in that the material to be filled is not a metal film. Further, this prior example is different from the present invention in that the second pattern is formed by chemical mechanical polishing. Also,
Japanese Patent Application Laid-Open No. 10-22372 discloses a method of forming an oxide film pattern in a wide groove portion to reduce a step during chemical mechanical polishing. This prior example is a method for forming an isolation region, which differs from the present invention in that the buried film is an insulating film and the object of the invention is to suppress the generation of voids in a narrow groove portion.

Japanese Patent Application Laid-Open No. 8-298285 discloses a method of forming a metal wiring by a damascene method.
In this method, a tungsten film is embedded in a narrow wiring groove, and a laminated film of tungsten and copper is formed in the wide wiring groove to reduce the resistance value of the wide wiring groove. This prior example differs from the present invention in that dishing cannot be avoided because a wide wiring portion remains concave when copper is chemically and mechanically polished.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a view showing a manufacturing process of a semiconductor manufacturing apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a semiconductor substrate on which elements (not shown) constituting an integrated circuit such as a transistor element and a capacitor element are formed; 102, a silicon oxide film as an insulating film;
Reference numeral 3 denotes a wiring pattern formed in a groove shape; 104, a TaN film as a barrier film; 105, a Cu (copper) film serving as a seed film for electrolytic plating as a first metal film; and 106, a second metal film. The first Cu plating film, 107 is an opening pattern made of a photoresist as a photosensitive material, 108 is a mask for blocking an energy beam, 109 is a step, 1
Reference numeral 10 denotes exposure light that is an energy beam, and 111 denotes a second Cu plating film that is a third metal film.

First, as shown in FIG. 1A, a silicon oxide film 102 having a thickness of 0.7 μm is formed on a semiconductor substrate 101, and the silicon oxide film 102 is formed by a photo-etching method.
A groove pattern 103 which is a wiring pattern is formed thereon. This groove pattern has various wiring widths. In the present invention, those having a pattern width (wiring groove width) of less than 1 μm are defined as thin groove wirings, and those having a pattern width of 1 μm or more are defined as wide groove wirings. Here, the case where the wiring widths are 0.3 μm and 10 μm will be described. The depth of the groove pattern is 0.4 μm.

Next, as shown in FIG. 1B, a tantalum nitride (hereinafter, referred to as TaN) film is formed as a barrier film 104 on the formed trench wiring pattern 103 by sputtering.
35 μm is formed. Here, a TaN film formed by sputtering is used as the barrier film. However, the TaN film is an example, and the material and the thickness of the barrier film are the first metal film 105 and the second metal film 1.
It is sufficient that the conductive film has a thickness that can suppress the diffusion of Cu into the silicon oxide film 102. For example, as the barrier film, a titanium nitride (hereinafter, TiN) film formed by a CVD method may be used to have a thickness of 0.01 μm.

Next, after the barrier film 104 is formed, Cu as the seed film 105 is formed to a thickness of 0.15 μm by sputtering while holding the semiconductor substrate in a vacuum. Here, the seed film was formed to a thickness of 0.15 μm by a sputtering method.
Other film thicknesses may be used as long as current flows through the seed film and copper is deposited in the next plating step.

After the seed film 105 is formed, as shown in FIG. 1C, the first Cu plating film 106 is formed at a current density of 1 by an electrolytic plating method using a plating solution containing copper sulfate as a main component.
For example, a 0.5 μm film is formed at 0 mA / cm ² . At this film thickness, a thin wiring groove having a wiring width of 0.3 μm can be buried. On the other hand, in the wide trench wiring portion having a width of 10 μm, as shown in FIG. 1C, a step 109 of 0.4 μm substantially corresponding to the depth of the trench wiring is generated. Here, the current density is 5 to 30 mA / cm ² , and there is no problem as long as the current density allows Cu to be deposited. Although the Cu plating deposition film thickness is also 0.5 μm, any film thickness that can embed a 0.3 μm wiring pattern may be used.

After the electrolytic plating, as shown in FIG. 1D, a 1 μm-thick positive type photoresist as a photosensitive material 107 is applied to the surface of the Cu plating film 106. Next, FIG.
As shown in (d), the KrF excimer laser beam 110
Is applied to the upper portion of the 10 μm wide groove wiring with a width of, for example, 9 μm. FIG. 2E is a cross-sectional view showing a process after developing the photosensitive material in the irradiated trench wiring with an alkaline solution. At this time, patterning is performed on the side wall of the trench wiring having a width of 10 μm so that the thickness of the photoresist from the side wall is less than 1 μm and covers the side wall. In this embodiment, the thickness of the photoresist 107 on the side wall is about 0.5 μm.

Next, as shown in FIG. 2F, a 0.4 μm-thick Cu film 111 having a step height of 109 and a thickness of about 50 μm is formed under the condition of 20 mA / cm ² by a second electrolytic plating process only for the trench wiring portion. Deposit for seconds. Through this plating step, a pattern of the Cu film 111 is formed on the groove pattern having a predetermined width (here, 1 μm) or more.

Here, the problem when the side wall of the wide groove wiring is not covered with the photoresist will be described with reference to FIG. FIG. 6A is a sectional view showing a step after the photoresist is removed. From this state, when the second electrolytic plating is performed, as shown in FIG.
A film 411 grows. Eventually, as shown in FIG. 6C, a thick Cu film is formed on the side wall of the trench wiring, so that a flat Cu film cannot be formed. Therefore, covering the side wall of the trench wiring with the photoresist is an important step.

After the second electrolytic plating, the photoresist 407 is removed by, for example, plasma ashing or a chemical solution. Through the steps described above, it can be seen that a flat Cu film without a wide step is formed before the chemical mechanical polishing as shown in FIG.

Here, the thickness of the Cu film 111 formed by the second electrolytic plating is set to 0.4 μm.
It is sufficient to deposit Cu only for the film thickness in which No. 9 occurs. Although the coating thickness of the photoresist 7 is 1 μm, the photosensitive material dissolves in the copper sulfate as a plating solution within the Cu deposition time, and the surface of the first Cu film 106 at the bottom of the wide groove wiring portion is exposed. Any film thickness may be used. Further, although the electrolytic plating method is used here, a Cu film can be formed by an electroless plating method.

After removing the photoresist 107, the Cu film 111 other than the groove portion by the second plating, the Cu film 106 by the first plating, and the Cu film 10 as a seed film
5. By polishing the TaN film 104 as a barrier film by chemical mechanical polishing, a wiring as shown in FIG. 2H can be formed. At this time, when polishing the Cu film 111 and the Cu film 106 by chemical mechanical polishing, the same kind of metal is polished. Therefore, no impurities are mixed in the slurry used for polishing, and a stable polishing state can be maintained.

By the above-described method, in a wiring in which a wide groove wiring and a narrow groove wiring region are mixed, the reduction of the Cu film in the wide groove wiring portion is suppressed, and a buried wiring is formed.

Although the plating method is used as a method for forming the first Cu film 106, a sputtering method or a CVD method can also be used. In this case, the Cu seed film 105 used as the first metal film 105 is It is not necessary to form a film. Only in that case, for example, a Cu film is formed on the barrier metal film 104 by a sputtering method or a CVD method, and a photoresist 107 is applied thereon. Further, Cu was selectively formed in the resist opening pattern 107 by using a plating method for forming the Cu film 111 as the third metal film, but Cu was formed by a CVD method or sputtering, and Cu was formed by a so-called lift-off method. A pattern using the film 111 may be formed. This lift-off method is effective when used for a metal to which the plating method is difficult to apply.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a view showing a manufacturing process of a semiconductor manufacturing apparatus according to a second embodiment of the present invention. In FIG. 3, reference numeral 201 denotes a semiconductor substrate on which elements (not shown) forming an integrated circuit such as a transistor element and a capacitor element are formed; 202, a silicon oxide film as an insulating film;
3 is a trench wiring, 204 is a TaN film as a barrier film, 205
Is a Cu (copper) film functioning as a seed film for electrolytic plating as a first metal film, and 206 is a first Cu film as a second metal film.
Plating film, 207 is a photosensitive material, 209 is a step, 211
Is a second Cu plating film which is a third metal film.

First, as shown in FIG. 3A, a 0.7 μm silicon oxide film 202 is formed on a semiconductor substrate 201, and the silicon oxide film 202 is formed by a photo-etching method.
A groove wiring pattern 203 is formed thereon. This groove pattern has various wiring widths. In the present invention, a thin groove wiring having a pattern width (wiring groove width) of less than 1 μm
The above is a wide groove wiring. Here, the wiring width is 0.3
The case of μm and 10 μm will be described. The depth of the groove pattern is 0.4 μm.

Next, as shown in FIG. 3B, a 0.035 μm TaN film is formed as a barrier film 204 on the formed trench wiring pattern 203 by a sputtering method.
Here, a TaN film formed by a sputtering method is used as the barrier film. However, the TaN film is an example, and the material and the thickness of the barrier film are changed to the Cu silicon oxide film 202 which is the first metal film 205 and the second metal film 206. It is needless to say that any conductive film may be used as long as the film thickness can suppress the diffusion of the conductive film. For example, a TiN film formed by a CVD method with a thickness of 0.01 μm may be used as the barrier film.

Next, after forming the TaN film 204, Cu as the seed film 205 is formed to a thickness of 0.15 μm by sputtering while holding the semiconductor substrate in a vacuum. Here, the seed film was formed to a thickness of 0.15 μm by a sputtering method.
Other film thicknesses may be used as long as current flows through the seed film and copper is deposited in the subsequent plating process.

Next, as shown in FIG. 3C, a 1 μm-thick positive type photoresist 207 is applied as a photosensitive material, and a KrF excimer laser beam is applied to the upper portion of a 10 μm wide wiring with a 9 μm width. Develop with an alkaline solution. At this time, patterning is performed so that the film thickness of the photosensitive material from the side wall is less than 1 μm and covers the side wall of the trench wiring having a width of 10 μm. At this time, if the side walls are not sufficiently covered with the photoresist, the problem described in the first embodiment with reference to FIG. 4 occurs. In this embodiment, the photoresist 207 on the side wall portion is used.
Is about 0.5 μm.

Next, as shown in FIG. 3D, a Cu film 206 having a step difference of about 0.35 μm is formed on the portion opened with the photoresist by a first electrolytic plating step to a thickness of 20 mA.
/ Cm 2 for about 50 seconds. Through this plating step, the Cu film 2 is formed on the groove pattern having a predetermined width or more.
06 has been formed.

Here, the thickness of the Cu film 206 formed by the first electrolytic plating is set to 0.35 μm.
A Cu film may be deposited to a thickness of about 09. The thickness of the photoresist 207 is set to 1 μm.
Any film thickness may be used as long as the photosensitive material dissolves in the plating solution of copper sulfate during the deposition time of the u film 206 and the side wall of the wide groove wiring portion is not exposed. Further, although the electrolytic plating method is used here, a Cu film can be formed by an electroless plating method.

Next, as shown in FIG. 3E, the photosensitive material 207 is removed by, for example, plasma ashing or a chemical solution.

Further, as shown in FIG. 3F, a Cu film 211 having a thickness of 0.4 μm is formed by a second electrolytic plating process.
Deposition is performed for about 50 seconds under the condition of 0 mA / cm ² . By this plating process, Cu is formed in a gap between the step 206 and the pattern 206 formed by the Cu film formed in the thin wiring portion having a width of less than 1 μm and the width of 1 μm or more in the groove wiring pattern 203 other than the groove wiring. Is done. At this time,
Since there is no groove or dent of 1 μm or more that causes a wide step, the substrate surface after the second plating is almost flat.

Next, C by the second plating except for the groove portion
By polishing the u film 211, the Cu film 206 formed by the first plating, the seed Cu film 205, and the TaN film 204 by chemical mechanical polishing, a wiring as shown in FIG. 3G can be formed. At this time, when polishing the Cu film 206 and the Cu film 205 by chemical mechanical polishing, the same kind of metal is polished. Therefore, no impurities are mixed in the slurry used for polishing, and a stable polishing state can be maintained.

By the above-described method, in a wiring in which a wide groove wiring and a narrow groove wiring region are mixed, the reduction in the thickness of the Cu film in the wide groove wiring portion is suppressed, and a buried wiring is formed.

Although the plating method is used as the method for forming the second Cu film 211, a sputtering method or a CVD method may be used. Further, Cu was selectively formed in the opening pattern 207 by the resist using a plating method for forming the Cu film 206 as the second metal film. However, Cu was formed by a CVD method or sputtering, and Cu was formed by a so-called lift-off method. Membrane 2
06 may be formed. This lift-off method is effective when used for a metal to which the plating method is difficult to apply.

(Embodiment 3) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a view showing a manufacturing process of a semiconductor manufacturing apparatus according to the third embodiment of the present invention.

In FIG. 4, reference numeral 301 denotes a semiconductor substrate on which elements (not shown) constituting an integrated circuit such as a transistor element and a capacitor are formed; 302, a silicon oxide film as an insulating film; Wiring, 304, a TiN film as a conductive film, 305, a photosensitive material, 306, a mask for blocking an energy beam, 307, exposure light as an energy beam, 308, a Cu film as a first metal film, 309
Is a Cu film as a second metal film.

First, as shown in FIG. 4A, a 0.7 μm silicon oxide film 302 is formed on a semiconductor substrate 301, and the silicon oxide film 302 is dry-etched to have a wiring width of 0.3 μm. 10 μm, depth 0.4 μm
Is formed. This groove pattern has various wiring widths. In the present invention, those having a pattern width (wiring groove width) of less than 1 μm are defined as thin groove wirings, and those having a pattern width of 1 μm or more are defined as wide groove wirings. Here, the wiring width is 0.3 μm
And the case of 10 μm will be described.

Next, as shown in FIG. 4B, a 0.01 μm TiN film is formed as a conductive film 304 on the formed trench wiring pattern 303 by a sputtering method. Here, as the conductive film, a film thickness of 0.0
Although a 1 μm TiN film is used, the TiN film is an example. Therefore, the material and thickness of the conductive film are the same as those of the first metal film 308.
And the silicon oxide film 302 of Cu which is the second metal film 309
It is needless to say that any material and film thickness that can suppress diffusion into the substrate may be used. For example, a TaN film having a thickness of 0.035 μm formed by a CVD method may be used as the barrier film.

Next, after forming the barrier film, a positive photoresist 305 having a thickness of 0.5 μm is applied as a photosensitive material as shown in FIG. A KrF excimer laser beam 307 is applied through the photomask 306 to the photoresist 30.
5 and developed with an alkaline solution,
As shown in FIG. 2D, 1.A.
A slit-shaped photoresist pattern having a width of 0.5 μm is formed at a pitch of 0 μm. The width between the patterns at this time is 0.
5 μm. Here, the thickness of the photoresist 305 is set to 0.5 μm, but the thickness of the photoresist 305 remaining in the slit shape inside the trench wiring is the sum of the depth of the trench wiring and the thickness of the conductive film. It is sufficient if the film thickness is greater than about 0.41 μm.

In the present embodiment, a slit pattern having a pitch of 1.0 μm and a width of 0.5 μm is used as the photoresist pattern.
Any shape and arrangement may be used as long as it is less than 1 μm, the distance from the trench wiring side wall is less than 1 μm, and the pattern interval is less than 1 μm. For example, a pattern in which 0.5 μm square columnar patterns are arranged at a 1 μm pitch may be used.

After the pattern is formed by the photoresist, C
0.4 μm thick C at 200 ° C. deposition temperature by VD method
A u film 308 is formed as shown in FIG. At this time, since the pattern is formed with the photoresist in the wide groove pattern, the Cu film 308 is formed almost flat.
Here, the film thickness is set to 0.4 μm, but any other film thickness can be embedded between the narrow groove wiring of less than 1 μm and the photoresist pattern of less than 1 μm formed like a slit in a wide wiring groove. The film thickness may be used.

After the Cu film 308 is formed, the Cu film 3 outside the trench wiring is formed as shown in FIG.
08 is removed so that the photoresist pattern 305 appears on the surface. At this time, a part of the Cu film other than the wiring groove may remain.

Next, the photoresist pattern 305 that has appeared on the surface by polishing is removed by ashing or chemical cleaning to form a Cu film 308 formed in a slit shape in a wide groove wiring as shown in FIG. I do.

Next, a 0.4 μm-thick C
A u film 309 is formed. At this time, since a slit-like pattern made of Cu having a pattern width of less than 1 μm is formed in the wide groove wiring, a flat Cu film 309 having no steps is formed as shown in FIG. be able to.

Next, after the second formation of the Cu film 309, the Cu film 309 except for the inside of the trench wiring is formed by the second chemical mechanical polishing.
The Cu film 308 and the TiN film 304 are removed. Through the above steps, a wiring as shown in FIG. 5 (i) can be formed. That is, in a wiring in which a wide groove wiring and a narrow groove wiring region are mixed, it is possible to suppress a film reduction in a wide groove wiring portion.

Although the CVD method is used in the first and second Cu film forming steps, any other method may be used as long as the film can be formed at a temperature at which the photoresist is not ashed. For example, there are a sputtering method, an electrolytic plating method, and an electroless plating method. When the electrolytic plating method is used, a seed layer is required on the barrier layer 304.

In the present invention, for example, a pattern is added to a wiring groove having a width of 1 μm or more to improve the flat soil in this portion. However, an alignment mark for a stepper and a mark for alignment measurement are provided. Is not limited to this. These marks usually have a width of 1 μm or more. However, if these marks are flattened, alignment cannot be performed or measurement of alignment accuracy becomes difficult.

In the present invention, the pattern width (wiring groove width)
Is smaller than 1 .mu.m, a narrow groove wiring is used, and a line having a diameter of 1 .mu.m or more is a wide groove wiring. Needless to say, this range varies depending on the conditions of chemical mechanical polishing and the conditions for forming a metal film.

[0058]

As described above, according to the present invention, in forming a trench wiring by filling, another flattening pattern is formed in a wiring pattern portion having a predetermined width or more, so that an opening area of a wide wiring pattern portion is formed. Is substantially reduced, and a wide step is prevented from being formed on the surface of the substrate before the chemical mechanical polishing is performed, thereby realizing a wiring without reducing the film thickness of the wiring even in a portion having a wide wiring width. Also, in the formation of the flattening pattern, since a method of selectively forming a metal film by using a plating method in an opening made of a photoresist is used, even if a metal material such as Cu is difficult to dry-etch, the pattern is formed. It has the advantage of being easy to form. Further, since the metal used for the flattening pattern is substantially the same as the metal to be embedded in the wiring, no impurities are mixed in the slurry used for polishing during chemical mechanical polishing, and a stable polishing state can be maintained. It has the advantage that. In the third embodiment, the same effect can be obtained by adding a pattern with a photosensitive material in a wide wiring pattern even for a metal film in which it is difficult to use a plating method.

[Brief description of the drawings]

FIG. 1 is a process sectional view in a manufacturing process of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a process sectional view in a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a process sectional view in a manufacturing process of a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a process sectional view in a manufacturing process of a semiconductor device according to a third embodiment of the present invention;

FIG. 5 is a process sectional view in a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a process cross-sectional view in a manufacturing process of the semiconductor device in which a problem has occurred in the embodiment of the present invention;

FIG. 7 is a process sectional view in a conventional semiconductor device manufacturing process.

FIG. 8 is a diagram showing a relationship between a wiring width and a dishing amount;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 silicon oxide film 3 groove wiring 4 barrier film 5 first metal film 6 second metal film 9 step 101 semiconductor substrate 102 silicon oxide film 103 groove wiring 104 barrier film 105 first metal film 106 second metal film 107 photosensitive Active material 108 Mask 109 Step 110 Energy beam 111 Third metal film 201 Semiconductor substrate 202 Silicon oxide film 203 Groove wiring 204 Barrier film 205 First metal film 206 Second metal film 207 Photosensitive material 209 Step 210 Energy beam 211 Third metal Film 301 semiconductor substrate 302 silicon oxide film 303 groove wiring 304 conductive material 305 photosensitive material 306 mask 307 energy beam 308 first metal film 309 second metal film 401 semiconductor substrate 402 silicon oxide film 403 groove wiring 404 barrier film 405 First metal film 406 Second metal film 409 Step 411 Third metal film

Claims (13)

[Claims] 1. A wiring formed on a semiconductor substrate, comprising:
A step of forming a first pattern on an insulating film; a step of forming an opening pattern of a photosensitive material on a pattern wider than a predetermined width in the first pattern; A step of selectively forming a second pattern with a metal of the same kind as a metal to be embedded in the wiring in the formed opening pattern, and a step of forming the wiring by flattening the substrate by chemical mechanical polishing. A method for manufacturing a semiconductor device. 2. A wiring of a semiconductor device in which a metal is buried in a wiring pattern on an insulating film formed on a semiconductor substrate, wherein the step of forming the wiring pattern and the insulating step including the wiring pattern are performed. Forming a barrier film on the film; forming a first metal film on the barrier film; forming a second metal film on the first metal film; Forming an opening pattern with a photosensitive material on a wiring pattern having a predetermined width or more, and selectively forming a third metal film in the opening pattern opened with the photosensitive material. The step of removing the photosensitive material and the step of removing the third metal film, the second metal film, the first metal film and the barrier film other than the wiring pattern by chemical mechanical polishing to form a wiring. Semiconductor device having Manufacturing method. 3. A wiring of a semiconductor device in which a metal is buried in a wiring pattern on an insulating film formed on a semiconductor substrate, wherein the step of forming the wiring pattern; A step of forming a barrier film on the film, a step of forming a first metal film on the barrier film, and forming an opening pattern with a photosensitive material on a wiring pattern having a predetermined width or more among the wiring patterns A step of selectively forming a second metal film in the opening pattern opened by the photosensitive material, a step of removing the photosensitive material, and a step of forming a third metal film. And forming a wiring by removing the third metal film, the second metal film, the first metal film, and the barrier film other than the wiring pattern by chemical mechanical polishing. 4. The method according to claim 2, wherein the second metal film is formed by a plating method. 5. The method according to claim 2, wherein the third metal film is formed by a plating method. 6. The method according to claim 2, wherein the second metal film and the third metal film are made of copper or a copper alloy. 7. The method of manufacturing a semiconductor device according to claim 2, wherein said predetermined width is 1 μm or more. 8. An opening pattern made of the photosensitive material is formed so as to cover a side wall of the wiring pattern having the predetermined width or more, and a film thickness covering the side wall is 1 μm.
8. The method of manufacturing a semiconductor device according to claim 7, wherein: 9. The method of manufacturing a semiconductor device according to claim 7, wherein the wiring pattern having the predetermined width or more does not include a pattern for alignment or alignment measurement. 10. A wiring of a semiconductor device in which a metal is buried in a wiring pattern on an insulating film formed on a semiconductor substrate, wherein the wiring pattern is formed, and the insulating pattern including the wiring pattern is provided. A step of forming a barrier film on the film, a step of forming a pattern with a photosensitive material on a wiring pattern having a predetermined width or more among the wiring patterns on which the barrier film is formed; A step of forming, a step of removing a part of the pattern made of the photosensitive material and the first metal film other than the wiring pattern by chemical mechanical polishing, and exposing a pattern made of the photosensitive material, The step of removing the pattern, the step of forming the second metal film, and the formation of the wiring by removing the second metal film, the first metal film and the barrier film by chemical mechanical polishing The method of manufacturing a semiconductor device having a step. 11. The semiconductor device according to claim 10, wherein said first metal film and said second metal film are made of copper or a copper alloy, and are formed by a chemical vapor deposition method or a sputtering method. Manufacturing method. 12. The method according to claim 10, wherein the pattern formed by the photosensitive material is a column or a slit, and the pattern interval is smaller than the predetermined width. 13. The method according to claim 10, wherein said predetermined width is 1 μm or more.