JP2001053112A - Method for connecting circuit substrate and composite circuit substrate - Google Patents
Method for connecting circuit substrate and composite circuit substrateInfo
- Publication number
- JP2001053112A JP2001053112A JP23038499A JP23038499A JP2001053112A JP 2001053112 A JP2001053112 A JP 2001053112A JP 23038499 A JP23038499 A JP 23038499A JP 23038499 A JP23038499 A JP 23038499A JP 2001053112 A JP2001053112 A JP 2001053112A
- Authority
- JP
- Japan
- Prior art keywords
- resin composition
- composition layer
- circuit substrate
- resin
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、例えば半導体チッ
プや配線基板等の回路基体同士を接続する方法および回
路基体同士が接続された複合回路基体に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting circuit substrates such as a semiconductor chip and a wiring substrate, and a composite circuit substrate in which the circuit substrates are connected.
【0002】[0002]
【従来の技術】従来、半導体チップと配線基板とを接続
して樹脂封止型の半導体装置を製造するには、半導体チ
ップの配線面上および配線基板上の配線形成面の電極パ
ッド上にそれぞれバンプ電極を形成し、半導体チップの
バンプ電極を配線基板上に圧着接合した後、半導体チッ
プの配線面と配線基板の配線面との間隙部にアンダーフ
ィル樹脂を注入する方法が開発されている。しかし、こ
のような製造方法ではアンダーフィル樹脂による樹脂封
止工程に時間を要するばかりでなく、樹脂の流動性や充
填剤量等が制約されるため、十分な信頼性の確保が困難
であった。2. Description of the Related Art Conventionally, in order to manufacture a resin-encapsulated semiconductor device by connecting a semiconductor chip to a wiring board, it is necessary to form the semiconductor device on a wiring surface of the semiconductor chip and on an electrode pad on a wiring forming surface on the wiring board. A method has been developed in which a bump electrode is formed, a bump electrode of a semiconductor chip is pressure-bonded to a wiring board, and then an underfill resin is injected into a gap between a wiring surface of the semiconductor chip and a wiring surface of the wiring board. However, in such a manufacturing method, not only time is required for the resin sealing step with the underfill resin, but also the fluidity of the resin and the amount of the filler are restricted, so that it is difficult to secure sufficient reliability. .
【0003】また、上述のアンダーフィル方式とは異な
り、半導体チップと配線基板との間にあらかじめ樹脂組
成物を介在させた後に、半導体チップと配線基板とを電
気的に接合する方法が開発されている。例えば、特開平
9−237806号公報にはバンプ電極が設けられた半
導体チップに熱可塑性樹脂層を形成し、この熱可塑性樹
脂層が半導体チップの実装時に溶融されて半導体チップ
を実装基板に接合するとともに封止もできることが示さ
れている。Also, unlike the above-described underfill method, a method has been developed in which a resin composition is interposed between a semiconductor chip and a wiring board in advance, and then the semiconductor chip and the wiring board are electrically joined. I have. For example, JP-A-9-237806 discloses that a thermoplastic resin layer is formed on a semiconductor chip provided with bump electrodes, and this thermoplastic resin layer is melted when the semiconductor chip is mounted, and the semiconductor chip is joined to a mounting substrate. In addition, it is shown that sealing can be performed together.
【0004】しかし、半導体チップや配線基板上に樹脂
組成物層を形成する場合、バンプ電極の存在、配線基板
の反りあるいはうねり等の影響で平坦な樹脂組成物層を
形成することは困難である。樹脂組成物層の表面に凹凸
が存在する場合、この状態で半導体チップと配線基板と
を接合すると、樹脂組成物層に空気層が残りボイドとな
る。ボイドは、吸湿時には水が溜まり半導体チップの配
線腐食を加速したり、バンプ電極が半田材料で形成され
ている場合には実装時に半田バンプが流出し、半田バン
プ間でブリッジが形成されて短絡不良が発生したりする
可能性がある。However, when a resin composition layer is formed on a semiconductor chip or a wiring board, it is difficult to form a flat resin composition layer due to the presence of bump electrodes, warpage or undulation of the wiring board, and the like. . In the case where the surface of the resin composition layer has irregularities, when the semiconductor chip and the wiring board are joined in this state, the air layer remains in the resin composition layer and becomes void. The voids accumulate water when absorbing moisture, accelerating the corrosion of the wiring of the semiconductor chip, and when the bump electrodes are formed of a solder material, the solder bumps flow out during mounting and a bridge is formed between the solder bumps, resulting in short-circuit failure. May occur.
【0005】ボイドを抑制する方法については、例え
ば、特開昭58−73126号公報に開示されている。
同公報には、回路基板(配線基板)にあらかじめ樹脂モ
ールド部材を塗布しておき、半導体チップを、樹脂モー
ルド部材を介して回路基板に搭載した後、ヒーターツー
ル等を用いて半導体チップを押圧、加熱することにより
回路基板と半導体チップとを接合すると共に、半導体チ
ップの封止も同時に行う半導体装置の実装方法が示され
ている。A method for suppressing voids is disclosed in, for example, Japanese Patent Application Laid-Open No. 58-73126.
In this publication, a resin mold member is applied to a circuit board (wiring board) in advance, the semiconductor chip is mounted on the circuit board via the resin mold member, and the semiconductor chip is pressed using a heater tool or the like. A method of mounting a semiconductor device in which a circuit board and a semiconductor chip are joined by heating and a semiconductor chip is simultaneously sealed is shown.
【0006】また、特開平6−89914号公報には、
半導体チップに熱可塑性樹脂をノズルにより中央部に塗
布して仮硬化させ、その後半導体チップの電極と回路基
板の電極とが接触する方向に加圧し、熱可塑性樹脂を半
導体チップと回路基板の間の中央部から周辺に拡散させ
て封止させ、半導体チップと回路基板を電気的に接続す
る半導体装置の封止方法が示されている。Further, Japanese Patent Application Laid-Open No. 6-89914 discloses that
A thermoplastic resin is applied to the center of the semiconductor chip with a nozzle and temporarily cured, and then pressed in a direction in which the electrodes of the semiconductor chip and the electrodes of the circuit board are in contact with each other. A sealing method of a semiconductor device in which a semiconductor chip and a circuit board are electrically connected by diffusing and sealing from a central portion to a periphery is shown.
【0007】しかし、上記特開昭58−73126号公
報および特開平6−89914号公報では共に、凸型に
半球状に樹脂を塗布して、回路基板と半導体チップとを
接合する際に、樹脂を周辺に流してボイドの発生を抑制
しており、また、回路基板や半導体チップ上にノズルを
用いて樹脂を塗布している。ノズルを用いて塗布ができ
るような樹脂は室温で液状であるような樹脂が多い。一
般に、室温で液状であるような樹脂組成物は耐加水分解
性に劣るような樹脂組成のものが多く、さらに室温で液
状にするには、充填剤の添加量に関しても制限があり、
樹脂組成物の熱膨張係数が大きいものとなる。熱膨張係
数が大きいと、半導体チップと樹脂組成物間、および配
線基板と樹脂組成物間の熱膨張係数の差が大きく、ヒー
トサイクル時に、半導体チップと樹脂組成物との界面お
よび配線基板と樹脂組成物との界面に発生する応力が大
きく、界面剥離が生じてバンプクラックや導通不良とい
った不良に至る可能性がある。However, in both the above-mentioned Japanese Patent Application Laid-Open No. 58-73126 and Japanese Patent Application Laid-Open No. Hei 6-89914, when a resin is applied in a hemispherical shape in a convex shape and a circuit board and a semiconductor chip are joined together, Is flowed to the periphery to suppress the generation of voids, and a resin is applied to the circuit board or the semiconductor chip using a nozzle. Many resins that can be applied using a nozzle are liquid at room temperature. In general, resin compositions that are liquid at room temperature often have a resin composition that is inferior in hydrolysis resistance, and in order to be liquid at room temperature, there is also a limitation on the amount of filler added,
The resin composition has a large coefficient of thermal expansion. When the coefficient of thermal expansion is large, the difference between the coefficient of thermal expansion between the semiconductor chip and the resin composition, and between the wiring board and the resin composition is large, and during the heat cycle, the interface between the semiconductor chip and the resin composition and between the wiring board and the resin The stress generated at the interface with the composition is large, and there is a possibility that interface delamination may occur, leading to defects such as bump cracks and poor conduction.
【0008】[0008]
【発明が解決しようとする課題】上記のようなアンダー
フィル樹脂を用いる従来の半導体装置は、半導体チップ
と配線基板との間隙に封止樹脂を注入する必要があるた
めに工程が複雑であるという問題がある。さらに、封止
樹脂に関しては未注入部分が生じるのを回避するため、
樹脂の流動性を上げることが求められ、充填剤量を増や
すことに対して限界がある。充填剤量が少ないと樹脂組
成物の熱膨張係数が大きなものとなり、樹脂組成物層と
半導体チップや基板との間の熱応力が大きくなることか
ら、ヒートサイクル等の試験で不良を発生する可能性が
高いという問題がある。The conventional semiconductor device using the above-described underfill resin has a complicated process because it is necessary to inject a sealing resin into a gap between a semiconductor chip and a wiring board. There's a problem. Furthermore, in order to avoid the occurrence of an uninjected portion with respect to the sealing resin,
It is required to increase the fluidity of the resin, and there is a limit to increasing the amount of the filler. If the amount of the filler is small, the thermal expansion coefficient of the resin composition becomes large, and the thermal stress between the resin composition layer and the semiconductor chip or the substrate becomes large, so that a defect such as a heat cycle test may occur. There is a problem that is high.
【0009】また、半導体チップと配線基板との間にあ
らかじめ樹脂組成物を介在させてから半導体チップと配
線基板とを電気的に接合する従来技術では、ボイドの発
生を抑制するためにはいずれも、ノズルを用いて樹脂を
塗布する必要があり、このような室温で液状である樹脂
組成物は充填剤量を増やすことに対しても限界があり、
樹脂組成物の熱膨張係数が大きいものとなる。従って、
樹脂組成物層と半導体チップや基板との間の熱応力が大
きく、ヒートサイクル等の試験で不良を発生する可能性
が高いという問題がある。In the prior art in which a resin composition is interposed in advance between a semiconductor chip and a wiring board and then the semiconductor chip and the wiring board are electrically joined, any method for suppressing the generation of voids is required. It is necessary to apply a resin using a nozzle, and such a resin composition that is liquid at room temperature has a limit to increasing the amount of filler,
The resin composition has a large coefficient of thermal expansion. Therefore,
There is a problem that thermal stress between the resin composition layer and the semiconductor chip or the substrate is large, and there is a high possibility that a defect occurs in a test such as a heat cycle.
【0010】本発明は上記のような従来のものの問題点
に鑑みてなされたもので、樹脂組成物層に残るボイドを
低減し、しかも樹脂組成物層と半導体チップや基板との
間の熱応力も低減して信頼性の高い半導体チップや配線
基板等の回路基体の接続方法および回路基体を接続した
複合回路基体を提供することを目的とする。The present invention has been made in view of the above-mentioned problems of the prior art, and reduces the voids remaining in the resin composition layer, and furthermore, the thermal stress between the resin composition layer and the semiconductor chip or substrate. It is an object of the present invention to provide a method for connecting a circuit substrate such as a semiconductor chip or a wiring substrate with high reliability and a composite circuit substrate connecting the circuit substrates.
【0011】[0011]
【発明を解決するための手段】本発明の第1の方法に係
る回路基体の接続方法は、第1の回路基体の配線面上に
第1の樹脂組成物層を形成し、第1の樹脂組成物層上ま
たは第2の回路基体の配線面上に第1の樹脂組成物層よ
り溶融粘度の低い第2の樹脂組成物層を形成し、第1と
第2の回路基体の配線面をバンプ電極を介在させて対向
配置し、第1と第2の回路基体間を前記樹脂組成物で接
合するとともに、前記回路基体相互の配線間を前記バン
プ電極で電気的に接続するものである。According to a first method of the present invention, a method of connecting a circuit substrate comprises forming a first resin composition layer on a wiring surface of a first circuit substrate, and forming a first resin composition layer on a wiring surface of the first circuit substrate. A second resin composition layer having a lower melt viscosity than the first resin composition layer is formed on the composition layer or on the wiring surface of the second circuit substrate, and the wiring surfaces of the first and second circuit substrates are formed. The first and second circuit boards are opposed to each other with a bump electrode interposed therebetween, and the first and second circuit boards are joined with the resin composition, and the wiring between the circuit boards is electrically connected with the bump electrodes.
【0012】本発明の第2の方法に係る回路基体の接続
方法は、上記第1の方法において、回路基体は半導体チ
ップまたは配線基板であるものである。According to a second method of the present invention, in the first method, the circuit substrate is a semiconductor chip or a wiring board.
【0013】本発明の第3の方法に係る回路基体の接続
方法は、上記第1または第2の方法において、第1の回
路基体の配線面上に第1の樹脂組成物層を形成した後
に、第2の樹脂組成物層を形成するものである。[0013] The method for connecting a circuit board according to a third method of the present invention is a method for connecting a circuit board after forming a first resin composition layer on a wiring surface of the first circuit board in the first or second method. And a second resin composition layer.
【0014】本発明の第4の方法に係る回路基体の接続
方法は、上記第3の方法において、第2の樹脂組成物層
の表面形状を半球状に形成するものである。According to a fourth method of the present invention, in the third method, the surface of the second resin composition layer is formed in a hemispherical shape in the third method.
【0015】本発明の第5の方法に係る回路基体の接続
方法は、上記第3または第4の方法において、第2の樹
脂組成物層として、室温で液状である樹脂組成物を用い
るものである。The method for connecting circuit boards according to a fifth method of the present invention is the method according to the third or fourth method, wherein the second resin composition layer uses a resin composition that is liquid at room temperature. is there.
【0016】本発明の第6の方法に係る回路基体の接続
方法は、上記第1または第2の方法において、第1の樹
脂組成物層上に第2の樹脂組成物層を積層した構成のフ
ィルムを、第1の回路基体の配線面に貼り付けるもので
ある。According to a sixth aspect of the present invention, there is provided a method of connecting a circuit substrate according to the first or second aspect, wherein the second resin composition layer is laminated on the first resin composition layer. The film is attached to the wiring surface of the first circuit substrate.
【0017】本発明の第7の方法に係る回路基体の接続
方法は、上記第1ないし第6のうちのいずれかの方法に
おいて、第2の樹脂組成物層の樹脂量が第1の樹脂組成
物層の樹脂量より少ないものである。According to a seventh aspect of the present invention, in the method for connecting a circuit substrate according to any one of the first to sixth aspects, the resin amount of the second resin composition layer is equal to the first resin composition. It is smaller than the resin amount of the material layer.
【0018】本発明の第8の方法に係る回路基体の接続
方法は、上記第1ないし第7のうちのいずれかの方法に
おいて、第1および第2の樹脂組成物層はバンプ電極の
融点より低い温度で溶融するものである。According to an eighth method of the present invention, in the method for connecting a circuit substrate according to any one of the first to seventh methods, the first and second resin composition layers may have a melting point higher than the melting point of the bump electrode. It melts at low temperatures.
【0019】本発明の第9の方法に係る回路基体の接続
方法は、上記第1ないし第8のうちのいずれかの方法に
おいて、第1または第2の樹脂組成物層がエポキシ樹脂
を含むものである。According to a ninth method of the present invention, in any one of the first to eighth methods, the first or second resin composition layer contains an epoxy resin. .
【0020】本発明の第10の方法に係る回路基体の接
続方法は、上記第1ないし第8のうちのいずれかの方法
において、第1または第2の樹脂組成物層がエポキシ樹
脂およびフェノール硬化剤を含むものである。According to a tenth method of the present invention, there is provided a method of connecting a circuit substrate according to any one of the first to eighth methods, wherein the first or second resin composition layer comprises an epoxy resin and a phenol cured resin. It contains an agent.
【0021】本発明の第11の方法に係る回路基体の接
続方法は、上記第1ないし第10のうちのいずれかの方
法において、第1または第2の樹脂組成物層が充填剤を
含むものである。According to an eleventh method of the present invention, in any one of the first to tenth methods, the first or second resin composition layer contains a filler. .
【0022】本発明の第12の方法に係る回路基体の接
続方法は、上記第1ないし第11のうちのいずれかの方
法において、第1と第2の回路基体の両方にバンプ電極
を形成するものである。According to a twelfth method of the present invention, in any one of the first to eleventh methods, bump electrodes are formed on both the first and second circuit substrates. Things.
【0023】本発明の第1の構成に係る複合回路基体
は、上記第1ないし第12のいずれかに記載の回路基体
の接続方法を用いて製造したものである。The composite circuit board according to the first configuration of the present invention is manufactured by using the circuit board connecting method according to any one of the first to twelfth aspects.
【0024】本発明の第2の構成に係る複合回路基体
は、対向配置された回路基体間が樹脂組成物で接合され
ると共に回路基体相互の配線間がバンプ電極で電気的に
接続された複合回路基体であって、前記樹脂組成物は溶
融粘度の異なる複数種類の樹脂組成物であるものであ
る。The composite circuit substrate according to the second aspect of the present invention is a composite circuit substrate in which opposing circuit substrates are joined with a resin composition and wiring between the circuit substrates is electrically connected by bump electrodes. A circuit substrate, wherein the resin composition is a plurality of types of resin compositions having different melt viscosities.
【0025】[0025]
【発明の実施の形態】本発明における回路基体とは配線
回路が形成された半導体チップや配線基板等である。本
発明に係る2つの回路基体の組み合わせとしては、
(a)半導体チップと半導体チップ、(b)半導体チッ
プと配線基板、(c)配線基板と配線基板が挙げられ
る。(a)の組み合わせにより作製された複合回路基体
は、それをリードフレームや配線基板等に搭載すること
で半導体装置とすることができる。(b)の組み合わせ
により作製された複合回路基体はそのものが半導体装置
であり、(c)の組み合わせで作製された回路基体は多
層配線基板である。DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit substrate according to the present invention is a semiconductor chip or a wiring board on which a wiring circuit is formed. As a combination of two circuit substrates according to the present invention,
(A) a semiconductor chip and a semiconductor chip, (b) a semiconductor chip and a wiring board, and (c) a wiring board and a wiring board. The composite circuit substrate manufactured by the combination of (a) can be used as a semiconductor device by mounting it on a lead frame, a wiring board, or the like. The composite circuit substrate produced by the combination (b) is a semiconductor device itself, and the circuit substrate produced by the combination (c) is a multilayer wiring substrate.
【0026】実施の形態1.本発明の実施の形態1によ
る回路基体の接続方法を、1例として(b)の組み合わ
せで、図1を用いて説明する。図において、1は第1の
回路基体であり本実施の形態では配線基板である。2、
6はバンプ電極、3は樹脂組成物層であり、第1の樹脂
組成物層31とこれより溶融粘度の低い第2の樹脂組成
物層32からなる。4は加熱ステージである。5は第2
の回路基体であり本実施の形態では半導体チップであ
る。7は加熱ヘッド、8は外部バンプ電極である。Embodiment 1 A method of connecting a circuit substrate according to Embodiment 1 of the present invention will be described with reference to FIG. In the figure, reference numeral 1 denotes a first circuit substrate, which is a wiring substrate in the present embodiment. 2,
Reference numeral 6 denotes a bump electrode, and reference numeral 3 denotes a resin composition layer, which comprises a first resin composition layer 31 and a second resin composition layer 32 having a lower melt viscosity than this. 4 is a heating stage. 5 is the second
And a semiconductor chip in the present embodiment. 7, a heating head; and 8, an external bump electrode.
【0027】接続方法は、まず、配線基板1にバンプ電
極2を形成する(工程(ii))。次に、第1の樹脂組
成物層31をバンプ電極2の形成された配線基板1上に
形成した(工程(iii)―1)後、第1の樹脂組成物
層31上に第1の樹脂組成物層31より溶融粘度が低い
第2の樹脂組成物層32を形成する(工程(iii)―
2)。In the connection method, first, the bump electrodes 2 are formed on the wiring board 1 (step (ii)). Next, after forming the first resin composition layer 31 on the wiring substrate 1 on which the bump electrodes 2 are formed (step (iii) -1), the first resin composition layer 31 is formed on the first resin composition layer 31. Forming a second resin composition layer 32 having a lower melt viscosity than the composition layer 31 (step (iii));
2).
【0028】次に、樹脂組成物層3を形成した配線基板
1を所定温度すなわちバンプ電極2,6の融点未満でし
かも樹脂組成物層3の融点以上の温度に設定した加熱ス
テージ4に位置決めして固定する(工程(iv))。ま
た、バンプ電極6を形成した半導体チップ5を加熱ヘッ
ド7に位置決めして固定する。加熱ステージ4が所定の
温度すなわちバンプ電極2,6の融点未満でしかも樹脂
組成物層3の融点以上の温度に加温されているため配線
基板1に形成した樹脂組成物層3は溶融状態となってい
る。Next, the wiring board 1 on which the resin composition layer 3 is formed is positioned on a heating stage 4 which is set at a predetermined temperature, that is, lower than the melting point of the bump electrodes 2 and 6 and higher than the melting point of the resin composition layer 3. (Step (iv)). Further, the semiconductor chip 5 on which the bump electrodes 6 are formed is positioned and fixed on the heating head 7. Since the heating stage 4 is heated to a predetermined temperature, that is, a temperature lower than the melting point of the bump electrodes 2 and 6 and higher than the melting point of the resin composition layer 3, the resin composition layer 3 formed on the wiring board 1 is in a molten state. Has become.
【0029】次に、加熱ヘッド7を動かし、加熱ヘッド
7に固定した半導体チップ5のバンプ電極6と加熱ステ
ージ4に固定した配線基板1のバンプ電極2とを接触さ
せる。さらに、半導体チップ5と配線基板1との間隔を
バンプ電極2と6が接触状態を保つように一定に保持し
たまま、所定のプロファイルで加熱ヘッド7を昇温して
バンプ電極2,6および樹脂組成物層3を樹脂組成物層
3がゲル化しない範囲で加熱し、樹脂組成物層3および
バンプ電極2,6を共に溶融状態として配線基板1と半
導体チップ5とを電気的に接続する(工程(v))。こ
の場合、上層の溶融粘度が低い第2の樹脂組成物層32
は樹脂組成物層3の表面に生じる凹凸を平坦化するのに
使用され、大半は半導体チップ5が配線基板1に接合す
る際に残存するボイドと共に外に押し出され、一部が樹
脂組成物層3中に残る。なお、樹脂のゲル化とは、樹脂
が反応により流動性を示さないことをいう。ただし、本
発明で用いられる樹脂組成物のゲル化時間(温度にも関
係)は特に規定されるものではないが、樹脂のゲル化時
間により製造の途中のプロセスが異なる場合がある。ゲ
ル化時間が短い場合のプロセスについては後述の実施例
2,3中で説明する。Next, the heating head 7 is moved to bring the bump electrodes 6 of the semiconductor chip 5 fixed to the heating head 7 into contact with the bump electrodes 2 of the wiring board 1 fixed to the heating stage 4. Further, while keeping the distance between the semiconductor chip 5 and the wiring board 1 constant so that the bump electrodes 2 and 6 keep the contact state, the heating head 7 is heated at a predetermined profile to increase the bump electrodes 2 and 6 and the resin. The composition layer 3 is heated to the extent that the resin composition layer 3 does not gel, so that the resin composition layer 3 and the bump electrodes 2 and 6 are both in a molten state to electrically connect the wiring board 1 and the semiconductor chip 5 ( Step (v)). In this case, the second resin composition layer 32 having a lower melt viscosity of the upper layer
Are used to flatten irregularities generated on the surface of the resin composition layer 3, and most are pushed out together with voids remaining when the semiconductor chip 5 is joined to the wiring board 1, and a part is extruded. Remains in 3. The gelation of the resin means that the resin does not show fluidity due to the reaction. However, the gelation time (also related to the temperature) of the resin composition used in the present invention is not particularly limited, but the process during the production may differ depending on the gelation time of the resin. The process when the gelation time is short will be described in Examples 2 and 3 described later.
【0030】次に、配線基板1と半導体チップ5との間
隔を一定にしたまま、所定のプロファイルで加熱ヘッド
7を降温して配線基板1、半導体チップ5、バンプ電極
2,6、および樹脂組成物層3をバンプ電極2,6およ
び樹脂組成物層3の融点未満の温度に冷却する。樹脂組
成物層3およびバンプ電極2,6は共に固化する。Next, while keeping the distance between the wiring board 1 and the semiconductor chip 5 constant, the temperature of the heating head 7 is lowered according to a predetermined profile, and the wiring board 1, the semiconductor chip 5, the bump electrodes 2, 6, and the resin composition are formed. The material layer 3 is cooled to a temperature lower than the melting points of the bump electrodes 2 and 6 and the resin composition layer 3. Both the resin composition layer 3 and the bump electrodes 2 and 6 solidify.
【0031】次に、接合された複合回路基体すなわち半
導体装置をバンプ電極2,6の融点未満でしかも樹脂組
成物層3が硬化可能な所定温度に設定したオーブンに樹
脂組成物層3が硬化するまで所定時間置いて、樹脂組成
物層3を硬化させる(工程(vi))。さらに、樹脂組
成物層3の硬化後に、配線基板1に外部バンプ電極8を
形成することもできる(工程(vii))。Next, the resin composition layer 3 is cured in an oven in which the joined composite circuit substrate, that is, the semiconductor device, is set at a predetermined temperature at which the melting point of the bump electrodes 2 and 6 is lower than the melting point and the resin composition layer 3 can be cured. After a predetermined time, the resin composition layer 3 is cured (step (vi)). Further, after the resin composition layer 3 is cured, the external bump electrodes 8 can be formed on the wiring board 1 (step (vii)).
【0032】上記のような接続方法によれば、従来の狭
間隙間に樹脂を流し込むアンダーフィル方式を用いるの
に比較して、時間の短縮、工程の削減ができ、アンダー
フィル方式では困難とされる超狭間隙に対しても、あら
かじめ樹脂組成物層3を形成することにより可能とな
る。According to the connection method as described above, it is possible to reduce the time and the number of steps compared with the conventional underfill method in which a resin is poured into a narrow gap, and it is difficult to use the underfill method. The formation of the resin composition layer 3 in advance is possible even for an ultra-narrow gap.
【0033】また、樹脂組成物層3中で下層の第1の樹
脂組成物層31より上層の第2の樹脂組成物層32の方
が溶融粘度が低くなっていることから、回路基体1と5
間を接合する際に閉じこめられたボイドが第1と第2の
回路基体1と5の間から外に排出されるため、樹脂組成
物層3にボイドが残らない。このため、バンプ電極2,
6が半田材料で形成されている場合で、実装時にはんだ
バンプが再溶融した場合にも、はんだバンプのボイド空
間への流出の心配がない。また、吸湿時にボイド部分へ
水が溜まり、リフロー時のパッケージクラックや回路基
体の配線材料の腐食を加速するといった問題も低減でき
る。Further, in the resin composition layer 3, the melt viscosity of the upper second resin composition layer 32 is lower than that of the lower first resin composition layer 31. 5
The voids trapped during the bonding are discharged outside from between the first and second circuit substrates 1 and 5, so that no voids remain in the resin composition layer 3. Therefore, the bump electrodes 2
When the solder bumps 6 are formed of a solder material and the solder bumps are re-melted during mounting, there is no fear that the solder bumps flow out into the void space. Further, the problem that water accumulates in the void portion during moisture absorption and accelerates the corrosion of package cracks and the corrosion of the wiring material of the circuit substrate during reflow can be reduced.
【0034】さらに、ボイドの発生を低減しようとした
従来の方法では樹脂組成物をノズル等で回路基体の中央
部に塗布し、もう一方の回路基体と接合する際に樹脂組
成物全体が流動することでボイド発生を低減するので、
樹脂組成物に高流動特性が求められ、充填剤の添加量に
制限があるために熱膨張係数が大きく、回路基体との熱
膨張係数の差が大きなものとなったが、本実施の形態で
は第2の樹脂組成物層32が接合時に流動すればよく、
しかも第2の樹脂組成物層32は接合時にそのほとんど
が流出してしまうので、回路基体1,5の熱膨張係数に
近い熱膨張係数を有する樹脂組成物層3とすることがで
きる。Further, in the conventional method for reducing the generation of voids, the resin composition is applied to the central portion of the circuit substrate with a nozzle or the like, and the entire resin composition flows when it is joined to another circuit substrate. Reduces the occurrence of voids,
The resin composition is required to have high fluidity characteristics, and the amount of the filler added is limited, so that the coefficient of thermal expansion is large, and the difference in the coefficient of thermal expansion with the circuit substrate is large. The second resin composition layer 32 only needs to flow at the time of joining,
In addition, since most of the second resin composition layer 32 flows out at the time of joining, the resin composition layer 3 having a coefficient of thermal expansion close to the coefficient of thermal expansion of the circuit substrates 1 and 5 can be obtained.
【0035】さらに、上記のような接続方法によれば、
樹脂組成物層3が溶融状態で固体のバンプ2,6を接触
させるので、バンプ2,6間に樹脂組成物がかみ込むこ
となく接合が可能となり、電気的接続の信頼性の高い複
合回路基体が得られる。また、バンプ2,6が溶融して
第1と第2の回路基体1と5間を電気的に接続する時
に、周囲に存在している樹脂組成物も溶融しているた
め、樹脂組成物に拘束されることなく、バンプ2,6は
最適な接合形状の形成が可能となり、これによっても電
気的接続の信頼性の高い複合回路基体が得られる。更
に、第1と第2の回路基体1と5間は常に一定の間隔で
保持されているため樹脂組成物層3やバンプ2,6が溶
融して液状化しても第1と第2の回路基体1,5間から
流失してしまうこともないので、接合の信頼性が向上す
る。Further, according to the above connection method,
Since the resin composition layer 3 is brought into contact with the solid bumps 2 and 6 in a molten state, the bumps 2 and 6 can be joined without the resin composition being bitten between the bumps 2 and 6, and the composite circuit substrate has high electrical connection reliability. Is obtained. Further, when the bumps 2 and 6 are melted to electrically connect the first and second circuit substrates 1 and 5, the surrounding resin composition is also melted. The bumps 2 and 6 can be formed in an optimum joint shape without being restrained, so that a composite circuit substrate having high reliability of electrical connection can be obtained. Further, since the first and second circuit substrates 1 and 5 are always kept at a constant interval, even if the resin composition layer 3 and the bumps 2 and 6 are melted and liquefied, the first and second circuit substrates 1 and 5 are liquefied. Since there is no loss from the space between the substrates 1 and 5, the reliability of bonding is improved.
【0036】本実施の形態で用いることのできるバンプ
電極2,6の材料としては、電気的な導通を確保できる
ものであれば特に限定されるものではない。半田バンプ
電極の材料としては、錫−鉛系の共晶半田(錫63重量
%、融点183℃)がプロセス面で使用しやすく信頼性
も高い。また、鉛を含有しないため環境に対する負荷を
低減することが可能なことから、錫―銀系、錫―銅系、
錫―亜鉛系、錫―ビスマス系およびこれらの系にさらに
ビスマス、銅またはビスマスと銅などを添加したいずれ
の半田材料も本実施の形態において適用可能である。ま
た、半田以外の材料もバンプ電極2,6の材料として使
用することができ、例えば金等を使用することができ
る。The material of the bump electrodes 2 and 6 that can be used in the present embodiment is not particularly limited as long as electrical conductivity can be ensured. As a material for the solder bump electrode, a tin-lead eutectic solder (63% by weight of tin, melting point: 183 ° C.) is easy to use on the process side and has high reliability. Also, since it does not contain lead, it is possible to reduce the burden on the environment, so tin-silver, tin-copper,
A tin-zinc system, a tin-bismuth system, and any solder material obtained by further adding bismuth, copper or bismuth and copper to these systems can be applied in the present embodiment. Also, materials other than solder can be used as the material of the bump electrodes 2 and 6, for example, gold and the like can be used.
【0037】回路基体1,5へのバンプ電極2,6の形
成方法としては、加熱溶融転写方式、蒸着方式、めっき
方式、ワイヤボンド方式、印刷方式、ボール搭載方式な
どいずれの方法も本実施の形態において適用が可能であ
る。さらに、インクジェットプリンタ方式の原理を利用
し溶解したはんだをジェッティングし、バンプ電極2,
6を形成する方式も本実施の形態において適用が可能で
ある。As a method for forming the bump electrodes 2 and 6 on the circuit substrates 1 and 5, any method such as a heat-melt transfer method, a vapor deposition method, a plating method, a wire bonding method, a printing method, and a ball mounting method is used in the present embodiment. Applicable in form. Further, the molten solder is jetted using the principle of the ink jet printer method, and the bump electrodes 2 and 2 are jetted.
6 can also be applied in the present embodiment.
【0038】本実施の形態では、樹脂組成物層3は、下
層にある第1の樹脂組成物層31の溶融粘度より上層に
ある第2の樹脂組成物層32の溶融粘度が低ければ、特
に限定されるものではなく、熱硬化性および熱可塑性の
何れの樹脂組成物を用いることも可能である。ただし、
熱可塑性の樹脂組成物を用いた場合は加熱による樹脂組
成物の硬化工程(工程(vi))は不要である。また、
必ずしも2層構造である必要もなく、3層以上の多層構
造であっても最上層の樹脂組成物(第2の樹脂組成物
層)の溶融粘度がそれより下層の樹脂組成物(第1の樹
脂組成物層)の溶融粘度より低ければよい。In this embodiment, if the melt viscosity of the second resin composition layer 32 in the upper layer is lower than the melt viscosity of the first resin composition layer 31 in the lower layer, The resin composition is not limited, and any of a thermosetting resin and a thermoplastic resin composition can be used. However,
When a thermoplastic resin composition is used, the step of curing the resin composition by heating (step (vi)) is unnecessary. Also,
The melt viscosity of the uppermost resin composition (second resin composition layer) is not necessarily required to be a two-layer structure, and even in a multilayer structure of three or more layers, the lower layer resin composition (first resin composition) What is necessary is that it is lower than the melt viscosity of the resin composition layer).
【0039】回路基体1,5への樹脂組成物層3の形成
方法、すなわち回路基体1,5への第1の樹脂組成物層
31の形成方法および第1の樹脂組成物層31への第2
の樹脂組成物層32の形成方法としては、印刷方式、デ
ィスペンス方式、スタンピング方式、キャスト方式、ス
ピンコート方式、カーテンコート方式などいずれの方法
でも本実施の形態において適用が可能である。また、加
熱しながら形成してもよい。The method for forming the resin composition layer 3 on the circuit substrates 1 and 5, that is, the method for forming the first resin composition layer 31 on the circuit substrates 1 and 5, and the method for forming the first resin composition layer 31 on the first resin composition layer 31 2
As a method for forming the resin composition layer 32, any method such as a printing method, a dispensing method, a stamping method, a casting method, a spin coating method, and a curtain coating method can be applied in the present embodiment. Further, it may be formed while heating.
【0040】なお、第1および第2の樹脂組成物31,
32を印刷塗布後、バンプ電極2周辺の残存する空気や
樹脂組成物中の揮発成分を除去するため減圧加熱を行う
ことも可能である。更に、減圧雰囲気中で第1および第
2の樹脂組成物層31,32を形成すると、ボイドの発
生を押えて樹脂組成物層3を形成することができる。Incidentally, the first and second resin compositions 31,
After the printing and application of 32, heating under reduced pressure can be performed to remove air remaining around the bump electrode 2 and volatile components in the resin composition. Furthermore, when the first and second resin composition layers 31 and 32 are formed in a reduced-pressure atmosphere, it is possible to form the resin composition layer 3 by suppressing generation of voids.
【0041】液状樹脂組成物として、溶剤を含有した樹
脂組成物も本実施の形態において適用が可能である。回
路基体1、5に塗布後、溶剤を揮発させることにより樹
脂組成物層3を形成する。溶剤としては、樹脂組成物中
の無機系材料以外を溶解させるものであれば特に制限は
ないが、例えば、ジメチルスルホキシド、ジメチルホル
ムアミド、塩化メチレン、クロロホルム、メチルエチル
ケトン、アセトン、テトラヒドロフラン、酢酸エチルな
どの溶剤単独またはその混合溶剤があげられる。特に、
80〜150℃で揮発が可能な単独および混合溶剤が好
ましく、80〜100℃で乾燥でき、樹脂組成物を溶解
させることができる点で、メチルエチルケトンまたはそ
の混合溶剤が好ましい。As the liquid resin composition, a resin composition containing a solvent is also applicable in the present embodiment. After application to the circuit substrates 1 and 5, the solvent is volatilized to form the resin composition layer 3. The solvent is not particularly limited as long as it dissolves other than the inorganic material in the resin composition.For example, solvents such as dimethyl sulfoxide, dimethylformamide, methylene chloride, chloroform, methyl ethyl ketone, acetone, tetrahydrofuran, and ethyl acetate A single solvent or a mixed solvent thereof can be used. In particular,
A single or mixed solvent which can be volatilized at 80 to 150 ° C. is preferable, and methyl ethyl ketone or a mixed solvent thereof is preferable because it can be dried at 80 to 100 ° C. and can dissolve the resin composition.
【0042】第1および第2の樹脂組成物層31、32
の少なくとも一方は、半導体分野で使用実績があり、樹
脂組成物に接着性を付与することから、エポキシ樹脂を
含むことが好ましい。エポキシ樹脂としては、1分子中
に2個以上のエポキシ基をもつエポキシ樹脂であれば特
に制限はないが、例えばビスフェノールA型エポキシ樹
脂、ビスフェノールF型エポキシ樹脂、ビスフェノール
S型エポキシ樹脂、ビスフェノールAD型エポキシ樹
脂、ジアリルビスフェノールA型エポキシ樹脂、ジアリ
ルビスフェノールF型エポキシ樹脂、ジアリルビスフェ
ノールAD型エポキシ樹脂、テトラメチルビフェノール
型エポキシ樹脂、ビフェノール型エポキシ樹脂、シクロ
ペンタジエン型エポキシ樹脂、テルペンフェノール型エ
ポキシ樹脂、テトラブロムビスフェノールA型エポキシ
樹脂、フェノールノボラック型エポキシ樹脂、クレゾー
ルノボラック型エポキシ樹脂、トリフェニルメタン型エ
ポキシ樹脂、環式脂肪族エポキシ樹脂、グリシジルエス
テルエポキシ樹脂および複素環式エポキシ樹脂等があげ
られ、単独またはその混合物が用いられる。なお、上記
エポキシ樹脂の中で、ビスフェノールA型エポキシ樹
脂、ビスフェノールF型エポキシ樹脂、環式脂肪族エポ
キシ樹脂およびグリシジルエステルエポキシ樹脂は室温
で液状の樹脂である。First and second resin composition layers 31 and 32
At least one of them has been used in the semiconductor field, and preferably contains an epoxy resin since it imparts adhesiveness to the resin composition. The epoxy resin is not particularly limited as long as it has two or more epoxy groups in one molecule. For example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol AD type Epoxy resin, diallyl bisphenol A type epoxy resin, diallyl bisphenol F type epoxy resin, diallyl bisphenol AD type epoxy resin, tetramethyl biphenol type epoxy resin, biphenol type epoxy resin, cyclopentadiene type epoxy resin, terpene phenol type epoxy resin, tetrabromo Bisphenol A type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, triphenylmethane type epoxy resin, cycloaliphatic epoxy resin, Glycidyl ester epoxy resins, and heterocyclic epoxy resins and the like, alone or a mixture thereof. Among the above epoxy resins, bisphenol A epoxy resin, bisphenol F epoxy resin, cycloaliphatic epoxy resin and glycidyl ester epoxy resin are liquid resins at room temperature.
【0043】また、第1および第2の樹脂組成物層3
1、32の少なくとも一方は、加水分解性の心配がなく
高信頼性の必要な半導体分野での使用実績があるフェノ
ール樹脂をエポキシ樹脂の硬化剤として使用することが
好ましい。フェノール樹脂としては、フェノールノボラ
ック、クレゾールノボラック、キシレゾールノボラッ
ク、ビスフェノールAのノボラック、ビスフェノールF
のノボラック、ビスフェノールADのノボラック、ビス
フェノールA、ビスフェノールF、ビスフェノールA
D、ジアリルビスフェノールA、ジアリルビスフェノー
ルF、およびジアリルビスフェノールAD等があげら
れ、単独またはその混合物が用いられる。The first and second resin composition layers 3
For at least one of 1, 32, it is preferable to use a phenol resin which has been used in the field of semiconductors requiring high reliability without worrying about hydrolyzability as a curing agent for epoxy resin. Phenol resins include phenol novolak, cresol novolak, xylesol novolak, bisphenol A novolak, bisphenol F
Novolak, bisphenol AD novolak, bisphenol A, bisphenol F, bisphenol A
D, diallyl bisphenol A, diallyl bisphenol F, and diallyl bisphenol AD, and the like, or a mixture thereof is used.
【0044】また、第1および第2の樹脂組成物層3
1、32の少なくとも一方は、熱膨張係数を小さくした
り、低吸水性を付与したりするために充填剤を含むこと
が好ましい。充填剤としては、例えば、溶融シリカ、結
晶シリカなどのシリカ、アルミナ、チッ化ケイ素、炭酸
カルシウム、酸化亜鉛などがあげられる。中でも、得ら
れる樹脂組成物の熱膨張係数を低下させ、機械的強度を
向上させるという点から、溶融シリカを用いるのが好ま
しい。さらに、流動性を付与する点から、球状の溶融シ
リカが好ましい。The first and second resin composition layers 3
It is preferable that at least one of 1 and 32 contains a filler in order to reduce the coefficient of thermal expansion or to impart low water absorption. Examples of the filler include silica such as fused silica and crystalline silica, alumina, silicon nitride, calcium carbonate, zinc oxide and the like. Above all, it is preferable to use fused silica from the viewpoint of reducing the coefficient of thermal expansion of the obtained resin composition and improving the mechanical strength. Further, spherical fused silica is preferred from the viewpoint of imparting fluidity.
【0045】回路基体1,5相互の配線間をバンプ電極
2,6で電気的に接続するのに用いる装置には特に制限
はないが、位置決め精度、昇温・降温機能の観点からフ
リップチップボンダが本実施の形態において好ましく用
いられ、例えば、市販のフリップチップボンダCB−1
750(ミスズFA(株)製)等が使用可能である。The device used to electrically connect the wiring between the circuit substrates 1 and 5 with the bump electrodes 2 and 6 is not particularly limited. However, from the viewpoints of positioning accuracy and temperature raising / lowering functions, a flip chip bonder is used. Is preferably used in the present embodiment, for example, a commercially available flip chip bonder CB-1
750 (manufactured by Miss FA Corporation) and the like can be used.
【0046】フリップチップボンダにて第1の回路基体
1と第2の回路基体5とを接合する際に、樹脂組成物層
3が固体であると、バンプ電極2,6同士を接触させて
導通を確保するために回路基体1,5に大きな加重を加
える必要が生じ回路基体1,5の破損やバンプ電極2,
6の形状が悪く接触状態が不安定なために信頼性が低下
するなどの問題が発生する。また、バンプ電極2,6お
よび樹脂組成物層3の両方が溶融している状態では、回
路基体1,5に形成したバンプ電極2,6同士を確実に
接触させるのが難しく、電気的接続の信頼性が低下す
る。これに対して、樹脂組成物層3が溶融状態でかつバ
ンプ電極2,6は固体状態である場合には、容易に回路
基体1,5に形成したバンプ電極2,6同士を接触させ
ることが可能となるので好ましい。When joining the first circuit substrate 1 and the second circuit substrate 5 with a flip chip bonder, if the resin composition layer 3 is solid, the bump electrodes 2 and 6 are brought into contact with each other to conduct electricity. It is necessary to apply a large weight to the circuit substrates 1 and 5 to secure the circuit board 1 and 5, and damage of the circuit substrates 1 and 5 and the bump electrodes 2 and
Since the shape of No. 6 is bad and the contact state is unstable, problems such as a decrease in reliability occur. Further, in a state where both the bump electrodes 2 and 6 and the resin composition layer 3 are molten, it is difficult to make sure that the bump electrodes 2 and 6 formed on the circuit substrates 1 and 5 are in contact with each other. Reliability decreases. On the other hand, when the resin composition layer 3 is in a molten state and the bump electrodes 2 and 6 are in a solid state, the bump electrodes 2 and 6 formed on the circuit substrates 1 and 5 can be easily brought into contact with each other. It is preferable because it becomes possible.
【0047】上記の理由から、第1と第2の回路基体1
と5間を接合する際、樹脂組成物層3がバンプ電極2,
6の融点より低い温度で溶融することが好ましく、バン
プ電極2,6として錫―鉛系(錫63重量%)の共晶は
んだを用いた場合には、その融点が183℃であるた
め、樹脂組成物層3が183℃に加熱するまでに溶融す
ることが好ましい。なおこの場合、室温で液状であって
も問題はない。For the above reasons, the first and second circuit substrates 1
When joining between 5 and 5, the resin composition layer 3 is
It is preferable that the resin be melted at a temperature lower than the melting point of No.6. When a tin-lead (eutectic 63% by weight) eutectic solder is used as the bump electrodes 2 and 6, the melting point is 183 ° C. It is preferable that the composition layer 3 is melted before being heated to 183 ° C. In this case, there is no problem even if it is liquid at room temperature.
【0048】また、溶融粘度が低い最上層の第2の樹脂
組成物層32の樹脂量がそれより下層の第1の樹脂組成
物層31の樹脂量より少ないことが好ましい。この場
合、最上層の第2の樹脂組成物層32は樹脂組成物層3
に発生する凹凸部分を補って平坦化するのに用いられ、
樹脂の大半は両回路基体1,5を接合した際には閉じこ
められたボイドと共に外に押し出されていることが好ま
しい。そのため、下層の第2の樹脂組成物層32の樹脂
量に比較して最上層の第2の樹脂組成物層32の樹脂量
は少ないことが好ましく、第2の樹脂組成物層32の樹
脂量は第1の樹脂組成物層31の樹脂量に対して50%
以下(体積比)であることが好ましい。さらに、下層の
第1の樹脂組成物層31が本来目的としている両回路基
体1,5の間隙に相当する厚みであるなら、最上層の第
2の樹脂組成物層32の樹脂量は第1の樹脂組成物層3
1の樹脂量に対して30%以下(体積比)であることが
好ましい。It is preferable that the resin amount of the uppermost second resin composition layer 32 having a lower melt viscosity is smaller than the resin amount of the lower first resin composition layer 31. In this case, the uppermost second resin composition layer 32 is
It is used to compensate for unevenness that occurs in
Most of the resin is preferably pushed out together with the confined void when the two circuit substrates 1 and 5 are joined. Therefore, the amount of resin in the uppermost second resin composition layer 32 is preferably smaller than the amount of resin in the lower second resin composition layer 32, and the amount of resin in the second resin composition layer 32 is preferably smaller. Is 50% of the resin amount of the first resin composition layer 31
The following (volume ratio) is preferable. Furthermore, if the lower first resin composition layer 31 has a thickness corresponding to the gap between the circuit substrates 1 and 5 which is originally intended, the amount of resin in the uppermost second resin composition layer 32 is the first. Resin composition layer 3
It is preferably 30% or less (volume ratio) with respect to the amount of the resin (1).
【0049】なお、本実施の形態では、バンプ電極2,
6は第1と第2両方の回路基体1と5に形成されてお
り、回路基体1,5の反りやうねり、各バンプ電極2,
6の高さのバラツキ等を緩衝でき、より確実に電気的接
続が行えるために好ましい。In this embodiment, the bump electrodes 2 and
6 is formed on both the first and second circuit substrates 1 and 5, and the circuit substrates 1 and 5 are warped or undulated, and each bump electrode 2 is formed.
This is preferable because variations in height 6 can be buffered and electrical connection can be performed more reliably.
【0050】また、上記実施の形態では、第2の樹脂組
成物層32を第1の樹脂組成物層31の上に形成する場
合について説明したが、第2の回路基体5の配線面上に
形成してもよく、上記実施の形態と同様の効果が得られ
る。Further, in the above embodiment, the case where the second resin composition layer 32 is formed on the first resin composition layer 31 has been described, but the second resin composition layer 32 is formed on the wiring surface of the second circuit substrate 5. It may be formed, and the same effect as in the above embodiment can be obtained.
【0051】実施の形態2.図2は本発明の実施の形態
2による回路基体の接続方法を工程順に示す説明図であ
る。本実施の形態は、第2の樹脂組成物層32を、第1
の樹脂組成物層31上に中央部が高くしかもその表面形
状が半球状となるようにディスペンス法等を用いて塗布
した(工程(iii)―2)以外は、実施の形態1と同
じである。なお、本実施の形態では、第2の樹脂組成物
層32としては、ディスペンス法等で塗布がしやすいこ
とから室温で液状であるものを用いるのが好ましい。Embodiment 2 FIG. 2 is an explanatory view showing a method of connecting circuit substrates according to a second embodiment of the present invention in the order of steps. In the present embodiment, the second resin composition layer 32 is
It is the same as that of the first embodiment, except that it is applied using a dispensing method or the like (step (iii) -2) so that the central portion is high and the surface shape is hemispherical on the resin composition layer 31 of (1). . In the present embodiment, it is preferable that the second resin composition layer 32 be liquid at room temperature because it can be easily applied by a dispensing method or the like.
【0052】本実施の形態によれば、第2の樹脂組成物
層32を、中央部が高くしかもその表面形状が半球状と
なるように形成したので、回路基体を接合する際に第2
の樹脂組成物を周辺に流してボイドの発生を効果的に抑
制することができる。According to the present embodiment, the second resin composition layer 32 is formed so that its central portion is high and its surface shape is hemispherical.
By flowing the resin composition in the vicinity, the generation of voids can be effectively suppressed.
【0053】なお、上記実施の形態2では、第2の樹脂
組成物層32は第1の樹脂組成物層31の上に形成する
場合について説明したが、第2の回路基体5の配線面上
に形成してもよく、上記実施の形態2と同様の効果が得
られる。Although the second embodiment has described the case where the second resin composition layer 32 is formed on the first resin composition layer 31, the second resin composition layer 32 is formed on the wiring surface of the second circuit substrate 5. The same effect as in the second embodiment can be obtained.
【0054】実施の形態3.図3は本発明の実施の形態
3による回路基体の接続方法を工程順に示す説明図であ
る。本実施の形態は、第1の樹脂組成物層31上にこれ
より溶融粘度の低い第2の樹脂組成物層32を積層した
構成のフィルム状の樹脂組成物を、第1の回路基体1の
配線面に貼り付けて樹脂組成物層3を形成した以外は、
実施の形態1と同じである。フィルム状の樹脂組成物の
貼り付けは、ラミネータやホットプレス等を用いて配線
基板1上にフィルム状の樹脂組成物を圧着することによ
り行うことができる。なお、フィルム状の樹脂組成物の
材料としては実施の形態1で示したものと同様のものを
用いることができる。Embodiment 3 FIG. FIG. 3 is an explanatory view showing a method of connecting circuit substrates according to a third embodiment of the present invention in the order of steps. In the present embodiment, a film-shaped resin composition having a configuration in which a second resin composition layer 32 having a lower melt viscosity is laminated on a first resin composition layer 31 is applied to the first circuit substrate 1. Except that the resin composition layer 3 was formed by sticking to the wiring surface,
This is the same as the first embodiment. The attachment of the film-shaped resin composition can be performed by pressing the film-shaped resin composition onto the wiring board 1 using a laminator, a hot press, or the like. Note that the same material as that described in Embodiment 1 can be used as the material of the resin composition in the form of a film.
【0055】なお、図ではフィルム状の樹脂組成物とし
て2層構造のものを用いた場合について説明したが、必
ずしも2層である必要はなく、最上層に溶融粘度が最も
低い第2の樹脂組成物層32を用いた3層以上、あるい
は下層から上層にかけて徐々に溶融粘度が低くなる傾斜
タイプのフィルムを使用することも可能である。なお、
フィルムを回路基体1に貼り付けた後、回路基体1の凹
凸部分に残るボイドや樹脂組成物層3中に残存するボイ
ドを取り除くために、樹脂組成物31,32が溶融する
温度に加温して減圧することことで、残存ボイドを防ぐ
こともできる。In the drawings, the case where a film-shaped resin composition having a two-layer structure is used has been described. However, it is not always necessary to have two layers, and the second resin composition having the lowest melt viscosity is provided on the uppermost layer. It is also possible to use three or more layers using the material layer 32 or an inclined type film in which the melt viscosity gradually decreases from the lower layer to the upper layer. In addition,
After the film is attached to the circuit substrate 1, the film is heated to a temperature at which the resin compositions 31 and 32 are melted in order to remove voids remaining in the uneven portions of the circuit substrate 1 and voids remaining in the resin composition layer 3. By reducing the pressure, residual voids can be prevented.
【0056】本実施の形態によれば、樹脂組成物がフィ
ルムのため取り扱いが容易であり生産効率の向上が可能
となる。According to the present embodiment, since the resin composition is a film, handling is easy and production efficiency can be improved.
【0057】なお、上記実施の形態3では、第2の樹脂
組成物層32は第1の樹脂組成物層31の上に形成する
場合について説明したが、第2の回路基体5の配線面上
に形成してもよく、上記実施の形態3と同様の効果が得
られる。In the third embodiment, the case where the second resin composition layer 32 is formed on the first resin composition layer 31 has been described. The same effect as in the third embodiment can be obtained.
【0058】実施の形態4.図4は本発明の実施の形態
4による回路基体の接続方法を工程順に示す説明図であ
る。一方の回路基体1に樹脂組成物層3を形成し(工程
(iii)―1,2および工程(iv))、他方の回路
基体2にバンプ電極6を形成した(工程(v))以外は
実施の形態2と同様である。なお、実施の形態2に限ら
ず実施の形態1や3と同様であってもよい。Embodiment 4 FIG. 4 is an explanatory view showing a method of connecting circuit substrates according to a fourth embodiment of the present invention in the order of steps. Except for forming the resin composition layer 3 on one circuit substrate 1 (step (iii) -1, 2 and step (iv)) and forming the bump electrode 6 on the other circuit substrate 2 (step (v)). This is the same as in the second embodiment. Note that the present invention is not limited to the second embodiment, and may be the same as the first and third embodiments.
【0059】本実施の形態によれば、樹脂組成物層3を
バンプ電極2の無い平坦な第1の回路基体1に形成でき
るため、ボイド無く均一に形成することが可能となり信
頼性の向上が可能となる。According to the present embodiment, since the resin composition layer 3 can be formed on the flat first circuit substrate 1 without the bump electrode 2, it can be formed uniformly without voids and the reliability can be improved. It becomes possible.
【0060】なお、上記実施の形態4では、第2の樹脂
組成物層32は第1の樹脂組成物層31の上に形成する
場合について説明したが、バンプ電極6が形成された第
2の回路基体5の配線面上に形成してもよく、この場合
にも第2の樹脂組成物層32の大半は接合時に残存する
ボイドと共に外に押し出されるため、バンプ電極6と第
2の樹脂組成物層32間に仮にボイドができていたとし
てもこれを除去したり、第1の樹脂組成物層31表面の
凹凸を平坦化したりでき、上記実施の形態4と同様にボ
イドの低減効果の向上が図れる。Although the fourth embodiment has described the case where the second resin composition layer 32 is formed on the first resin composition layer 31, the second resin composition layer 32 on which the bump electrode 6 is formed is formed. The second resin composition layer 32 may also be formed on the wiring surface of the circuit substrate 5, and in this case also, most of the second resin composition layer 32 is pushed out together with the voids remaining at the time of bonding. Even if voids are formed between the material layers 32, the voids can be removed or the irregularities on the surface of the first resin composition layer 31 can be flattened, thereby improving the effect of reducing voids as in the fourth embodiment. Can be achieved.
【0061】実施の形態5.図5は本発明の実施の形態
5による回路基体の接続方法を工程順に示す説明図であ
る。一方の回路基体1にバンプ電極2と樹脂組成物層3
の両方を形成し(工程(ii)、工程(iii)―1,
2および工程(iv))、他方の回路基体2にはバンプ
電極も樹脂組成物層も形成しなかった以外は実施の形態
2と同様である。なお、実施の形態2に限らず実施の形
態1や3と同様であってもよい。Embodiment 5 FIG. 5 is an explanatory view showing a method of connecting circuit substrates according to a fifth embodiment of the present invention in the order of steps. A bump electrode 2 and a resin composition layer 3
(Step (ii), step (iii) -1,
2 and step (iv)), except that neither the bump electrode nor the resin composition layer was formed on the other circuit substrate 2. Note that the present invention is not limited to the second embodiment, and may be the same as the first and third embodiments.
【0062】本実施の形態によれば、バンプ2および樹
脂組成物層3の両方を一方の回路基体1のみに形成した
ため、実施の形態1〜3のように両方の回路基体1と5
にバンプ2と6を、一方の回路基体1に樹脂組成物層3
をそれぞれ形成する場合や、実施の形態4のように一方
の回路基体1に樹脂組成物層3を、他方の回路基体5に
バンプ電極6をそれぞれ形成する場合に比較して、製造
工程を短縮でき生産効率が向上する。According to the present embodiment, since both the bump 2 and the resin composition layer 3 are formed on only one circuit substrate 1, both circuit substrates 1 and 5 are formed as in the first to third embodiments.
And the resin composition layer 3 on one circuit substrate 1.
Respectively, or in a case where the resin composition layer 3 is formed on one circuit substrate 1 and the bump electrode 6 is formed on the other circuit substrate 5 as in the fourth embodiment, respectively. Production efficiency is improved.
【0063】なお、上記実施の形態1、2、4および5
において、第1の樹脂組成物層31としてフィルムを用
いてこれを配線基板1に貼り付けた上に、第2の樹脂組
成物層32を印刷やディスペンスなどの方法で形成する
こともできる。また、第1の樹脂組成物層31を第1の
回路基体1上に、第2の樹脂組成物層32を第2の回路
基体5上にそれぞれ形成する場合には、第1および第2
の樹脂組成物層31および32は共にフィルム状であっ
てもよい。これらの場合には、各実施の形態の効果に加
えて、樹脂組成物がフィルム状であることから取り扱い
が容易となる効果が得られる。In the first, second, fourth and fifth embodiments,
In the above, a second resin composition layer 32 may be formed by a method such as printing or dispensing after a film is used as the first resin composition layer 31 and attached to the wiring substrate 1. When the first resin composition layer 31 is formed on the first circuit substrate 1 and the second resin composition layer 32 is formed on the second circuit substrate 5, the first and second resin composition layers 32 are formed.
Both the resin composition layers 31 and 32 may be in the form of a film. In these cases, in addition to the effects of the respective embodiments, an effect of facilitating handling is obtained because the resin composition is in the form of a film.
【0064】なお、上記各実施の形態では、第1の回路
基体1が配線基板で、第2の回路基体5が半導体チップ
である場合について説明したが、逆であってもよく、同
様の効果が得られるのは言うまでもない。また、第1お
よび第2の回路基体1,5が、共に半導体チップである
場合や、共に配線基板であってもよく、この場合にも同
様の効果が得られる。In each of the above embodiments, the case where the first circuit substrate 1 is a wiring substrate and the second circuit substrate 5 is a semiconductor chip has been described. Needless to say, this is obtained. In addition, the first and second circuit substrates 1 and 5 may both be semiconductor chips, or both may be wiring substrates. In this case, the same effect can be obtained.
【0065】[0065]
【実施例】以下に具体的実施例を示すが、本発明はこれ
らのみに限定されるものではない。以下の各実施例は、
第1の回路基体1が配線基板、第2の回路基体5が半導
体チップである場合について示している。各実施例にお
いて、半導体チップ5および配線基板1の少なくとも一
方に形成するバンプ電極材料、並びに配線基板1に形成
する樹脂組成物層3は表1に示す組み合わせで行った。
また、各実施例で使用する樹脂組成物は、表2に示す材
料を使用した。なお、ゲル化時間はあらかじめ所定の温
度に設定した熱板上にて測定した値である。なお、表2
中、下層および上層とはそれぞれ第1および第2の樹脂
組成物層31,32のことである。EXAMPLES Specific examples are shown below, but the present invention is not limited to these examples. Each of the following examples,
The case where the first circuit substrate 1 is a wiring substrate and the second circuit substrate 5 is a semiconductor chip is shown. In each example, the bump electrode material formed on at least one of the semiconductor chip 5 and the wiring board 1 and the resin composition layer 3 formed on the wiring board 1 were combined in the combinations shown in Table 1.
Moreover, the resin composition used in each Example used the material shown in Table 2. The gelation time is a value measured on a hot plate set at a predetermined temperature in advance. Table 2
The middle, lower and upper layers are the first and second resin composition layers 31 and 32, respectively.
【0066】[0066]
【表1】 [Table 1]
【0067】[0067]
【表2】 [Table 2]
【0068】実施例1.図3の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。Embodiment 1 Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate.
【0069】接続方法は、まず、配線基板1上に錫−鉛
系(錫63重量%)の共晶半田バンプ電極2を形成し、
バンプ電極2付き配線基板1を作製した(工程(i
i))。次に、この配線基板1上に2層フィルム状の樹
脂組成物(A)を加熱および加圧(80℃、10秒、
0.1kgf/mm2)して樹脂組成物層3を形成した
(工程(iii))。次に、フリップチップボンダ上
で、樹脂組成物層3を形成した配線基板1を所定温度
(150℃)に設定した加熱ステージ4に位置決めして
固定した(工程(iv))。また、バンプ電極6付き半
導体チップ5を加熱ヘッド7(150℃)に位置決めし
て固定した。表2より樹脂組成物(A)の溶融温度が8
0℃であり、加熱ステージ4がそれより高い温度(15
0℃)に加温されているため、配線基板1に形成した樹
脂組成物層3は溶融状態となっている。First, a eutectic solder bump electrode 2 of tin-lead (63% by weight of tin) is formed on a wiring board 1,
The wiring substrate 1 with the bump electrodes 2 was manufactured (step (i)
i)). Next, the resin composition (A) in the form of a two-layer film is heated and pressed (80 ° C., 10 seconds,
0.1 kgf / mm 2 ) to form a resin composition layer 3 (step (iii)). Next, on the flip chip bonder, the wiring substrate 1 on which the resin composition layer 3 was formed was positioned and fixed on the heating stage 4 set at a predetermined temperature (150 ° C.) (step (iv)). Further, the semiconductor chip 5 with the bump electrode 6 was positioned and fixed on the heating head 7 (150 ° C.). According to Table 2, the melting temperature of the resin composition (A) was 8
0 ° C. and the heating stage 4 is at a higher temperature (15 ° C.).
(0 ° C.), the resin composition layer 3 formed on the wiring board 1 is in a molten state.
【0070】次に、加熱ヘッド7を動かし、加熱ヘッド
7に固定した半導体チップ5のバンプ電極6と加熱ステ
ージ4に固定した配線基板1上のバンプ電極2とを接触
させた。次に、半導体チップ5と配線基板1との間隔を
両バンプ電極2と6を接触させた状態で一定(90μ
m)に保持したまま、加熱ヘッド7を5秒で230℃ま
で昇温した後、230℃で10秒保持し、バンプ電極
2、6および樹脂組成物層3を加熱した。バンプ電極
2、6および樹脂組成物層3は共に溶融状態となり配線
基板1と半導体チップ5がバンプ電極2、6を介して電
気的に接続された(工程(v))。この場合、上層の溶
融粘度が低い第2の樹脂組成物層32は樹脂組成物層3
に生じる凹凸を平坦化するのに使用され、大半は半導体
チップ5が配線基板1に接合する際に残存ボイドと共に
外に押し出され、一部は樹脂組成物層3中に残った。次
に、配線基板1と半導体チップ5との間隔を一定(90
μm)に保持したまま、所定のプロファイルで加熱ヘッ
ド7を降温して配線基板1、半導体チップ5、バンプ電
極2,6、および樹脂組成物層3を100℃まで冷却し
た。するとバンプ電極2,6は固化し、次にフリップチ
ップボンダ上から取り出して室温で放置することで樹脂
組成物層3も固化した。Next, the heating head 7 was moved to bring the bump electrodes 6 of the semiconductor chip 5 fixed to the heating head 7 into contact with the bump electrodes 2 on the wiring board 1 fixed to the heating stage 4. Next, the distance between the semiconductor chip 5 and the wiring board 1 is kept constant (90 μm) while the bump electrodes 2 and 6 are in contact with each other.
After the temperature of the heating head 7 was raised to 230 ° C. in 5 seconds while maintaining the temperature in m), the temperature was maintained at 230 ° C. for 10 seconds to heat the bump electrodes 2 and 6 and the resin composition layer 3. The bump electrodes 2 and 6 and the resin composition layer 3 were both in a molten state, and the wiring board 1 and the semiconductor chip 5 were electrically connected via the bump electrodes 2 and 6 (step (v)). In this case, the upper resin composition layer 32 having a low melt viscosity is the resin composition layer 3
Mostly, the semiconductor chip 5 was pushed out together with the remaining voids when the semiconductor chip 5 was bonded to the wiring board 1, and a part thereof was left in the resin composition layer 3. Next, the distance between the wiring board 1 and the semiconductor chip 5 is fixed (90
While maintaining the temperature, the heating head 7 was cooled down with a predetermined profile to cool the wiring board 1, the semiconductor chip 5, the bump electrodes 2, 6, and the resin composition layer 3 to 100 ° C. Then, the bump electrodes 2 and 6 were solidified, and then taken out from the flip chip bonder and left at room temperature to solidify the resin composition layer 3.
【0071】次に、接合された配線基板1と半導体チッ
プ5を、バンプ電極2、6の溶融温度(183℃)より
低い170℃に設定したオーブン中で2時間放置して、
樹脂組成物層3の硬化を行った(工程(vi))。最後
に、配線基板1に外部バンプ電極8を形成して半導体装
置を得た(工程(vii))。Next, the bonded wiring board 1 and semiconductor chip 5 are left in an oven set at 170 ° C. lower than the melting temperature of the bump electrodes 2 and 6 (183 ° C.) for 2 hours.
The resin composition layer 3 was cured (step (vi)). Finally, an external bump electrode 8 was formed on the wiring board 1 to obtain a semiconductor device (step (vii)).
【0072】実施例2.図3の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。Embodiment 2 FIG. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate.
【0073】接続方法は、まず、実施例1と同様に配線
基板1上に錫−鉛系(錫63重量%)の共晶半田バンプ
電極2を形成した(工程(ii))。次にこの配線基板
1上に2層フィルム状の樹脂組成物(B)を加熱および
加圧(80℃、10秒、0.1kgf/mm2)して樹
脂組成物層3を形成した(工程(iii))。次に、フ
リップチップボンダ上で、樹脂組成物層3を形成した配
線基板1を所定温度(80℃)に設定した加熱ステージ
4に位置決めして固定した(工程(iv))。また、バ
ンプ電極6付き半導体チップ5を加熱ヘッド7(150
℃)に位置決めして固定した。表2より樹脂組成物
(B)の溶融温度が80℃であり、加熱ステージ4が8
0℃に加温されているため、配線基板1に形成した樹脂
組成物層3は溶融状態となっている。First, a eutectic solder bump electrode 2 of tin-lead (63% by weight of tin) was formed on the wiring board 1 in the same manner as in Example 1 (step (ii)). Next, the resin composition (B) in the form of a two-layer film was heated and pressed (80 ° C., 10 seconds, 0.1 kgf / mm 2 ) on the wiring substrate 1 to form the resin composition layer 3 (step). (Iii)). Next, on the flip chip bonder, the wiring board 1 on which the resin composition layer 3 was formed was positioned and fixed on the heating stage 4 set at a predetermined temperature (80 ° C.) (step (iv)). Further, the semiconductor chip 5 with the bump electrode 6 is moved to the heating head 7 (150
° C) and fixed. According to Table 2, the melting temperature of the resin composition (B) was 80 ° C.
Since the substrate is heated to 0 ° C., the resin composition layer 3 formed on the wiring board 1 is in a molten state.
【0074】次に、加熱ヘッド7を動かし、加熱ヘッド
7に固定した半導体チップ5のバンプ電極6と加熱ステ
ージ4に固定した配線基板1上のバンプ電極2とを一定
圧(15kgf/チップ)を加えて接触させ、この状態
で60秒間保持した。表2より樹脂組成物層3のゲル化
時間は150℃で30秒であるので、この間に配線基板
1と半導体チップ5双方の共晶半田バンプ2、6が接触
を維持した状態で樹脂組成物層3はゲル化した(工程
(v))。なおこの場合、上層の溶融粘度が低い第2の
樹脂組成物層32は樹脂組成物層3に生じる凹凸を平坦
化するのに使用され、大半は半導体チップ5が配線基板
1に接合する際に残存ボイドと共に外に押し出され、一
部が樹脂組成物層3中に残った。次に、所定のプロファ
イルで加熱ヘッド7を降温して配線基板1、半導体チッ
プ5、バンプ電極2、6、および樹脂組成物層3を10
0℃まで冷却した。Next, the heating head 7 is moved to apply a constant pressure (15 kgf / chip) between the bump electrode 6 of the semiconductor chip 5 fixed to the heating head 7 and the bump electrode 2 on the wiring board 1 fixed to the heating stage 4. In addition, they were brought into contact and kept in this state for 60 seconds. According to Table 2, the gel time of the resin composition layer 3 is 30 seconds at 150 ° C., and during this time, the eutectic solder bumps 2 and 6 of both the wiring board 1 and the semiconductor chip 5 are kept in contact with each other. Layer 3 gelled (step (v)). In this case, the upper second resin composition layer 32 having a low melt viscosity is used for flattening irregularities generated in the resin composition layer 3, and most of the second resin composition layer 32 is used when the semiconductor chip 5 is bonded to the wiring board 1. It was extruded out together with the remaining voids, and a part thereof remained in the resin composition layer 3. Next, the temperature of the heating head 7 is lowered with a predetermined profile, and the wiring board 1, the semiconductor chip 5, the bump electrodes 2, 6, and the resin composition
Cooled to 0 ° C.
【0075】次に、接合された配線基板1と半導体チッ
プ5を、バンプ電極2、6の溶融温度より低い150℃
に設定したオーブン中で1時間放置して、樹脂組成物層
3の硬化を行った(工程(vi))。Next, the bonded wiring board 1 and the semiconductor chip 5 are heated at 150 ° C. lower than the melting temperature of the bump electrodes 2 and 6.
Was left in the oven set for 1 hour to cure the resin composition layer 3 (step (vi)).
【0076】最後に、配線基板1に外部バンプ電極8を
形成して半導体装置を得た(工程(vii))。なお、
配線基板1に外部バンプ電極8を形成する際に半田の融
点以上の温度域に半導体装置がさらされることから、配
線基板1と半導体チップ5の間にあるバンプ電極2、6
は溶融し、バンプ電極2、6は金属結合した状態で電気
的に導通を確保することができた。Finally, external bump electrodes 8 were formed on the wiring board 1 to obtain a semiconductor device (step (vii)). In addition,
Since the semiconductor device is exposed to a temperature range higher than the melting point of solder when forming the external bump electrodes 8 on the wiring board 1, the bump electrodes 2, 6 between the wiring board 1 and the semiconductor chip 5 are exposed.
Was melted, and electrical continuity could be secured in a state where the bump electrodes 2 and 6 were metal-bonded.
【0077】実施例3.図3の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。Embodiment 3 FIG. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate.
【0078】接続方法は、まず、配線基板1上に金バン
プ電極2を形成した(工程(ii))。次にこの配線基
板1上に2層フィルム状の樹脂組成物(B)を加熱およ
び加圧(80℃、10秒、0.1kgf/mm2)して
樹脂組成物層3を形成した(工程(iii))。次に、
フリップチップボンダ上で樹脂組成物層3を形成した配
線基板1を所定温度(80℃)に設定した加熱ステージ
4に位置決めして固定した(工程(iv))。また、バ
ンプ電極6付き半導体チップ5を加熱ヘッド7(150
℃)に位置決めして固定した。In the connection method, first, the gold bump electrode 2 was formed on the wiring substrate 1 (step (ii)). Next, the resin composition (B) in the form of a two-layer film was heated and pressed (80 ° C., 10 seconds, 0.1 kgf / mm 2 ) on the wiring substrate 1 to form the resin composition layer 3 (step). (Iii)). next,
The wiring substrate 1 on which the resin composition layer 3 was formed on the flip chip bonder was positioned and fixed on the heating stage 4 set at a predetermined temperature (80 ° C.) (step (iv)). Further, the semiconductor chip 5 with the bump electrode 6 is moved to the heating head 7 (150
° C) and fixed.
【0079】次に、加熱ヘッド7を動かし、加熱ヘッド
7に固定した半導体チップ5のバンプ電極6と加熱ステ
ージ4に固定した配線基板1上のバンプ電極2とを一定
圧(15kgf/チップ)を加えて接触させ、この状態
で60秒間保持した。表2より樹脂組成物層3のゲル化
時間は150℃で30秒であるので、この間に配線基板
1と半導体チップ5双方の金バンプ2、6が接触しを維
持した状態で樹脂組成物層3はゲル化した(工程
(v))。なおこの場合、上層の溶融粘度が低い第2の
樹脂組成物層32は樹脂組成物層3に生じる凹凸を平坦
化するのに使用され、大半は半導体チップ5が配線基板
1に接合する際に残存ボイドと共に外に押し出され一部
が樹脂組成物層3中に残った。次に、所定のプロファイ
ルで加熱ヘッド7を降温して配線基板1、半導体チップ
5、バンプ電極2,6、および樹脂組成物層3を100
℃まで冷却した。Next, the heating head 7 is moved to apply a constant pressure (15 kgf / chip) between the bump electrode 6 of the semiconductor chip 5 fixed to the heating head 7 and the bump electrode 2 on the wiring board 1 fixed to the heating stage 4. In addition, they were brought into contact and kept in this state for 60 seconds. According to Table 2, the gel time of the resin composition layer 3 is 30 seconds at 150 ° C., so that the gold bumps 2 and 6 of both the wiring board 1 and the semiconductor chip 5 are kept in contact during this time. 3 was gelled (step (v)). In this case, the upper second resin composition layer 32 having a low melt viscosity is used for flattening irregularities generated in the resin composition layer 3, and most of the second resin composition layer 32 is used when the semiconductor chip 5 is bonded to the wiring board 1. The resin was extruded out together with the remaining voids, and a part thereof remained in the resin composition layer 3. Next, the temperature of the heating head 7 is lowered with a predetermined profile to remove the wiring board 1, the semiconductor chip 5, the bump electrodes 2, 6, and the resin composition layer 3 by 100.
Cooled to ° C.
【0080】次に、接合された配線基板1と半導体チッ
プ5を、バンプ電極2、6の溶融温度より低い150℃
に設定したオーブン中で1時間放置して、樹脂組成物層
3の硬化を行った(工程(vi))。最後に、配線基板
1に外部バンプ電極8を形成して半導体装置を得た(工
程(vii))。なお、本実施例ではバンプ電極2,6
としてその融点が千℃以上である金を用いたので、実施
例2のように外部バンプ電極8の形成時に溶融すること
はなかった。Next, the bonded wiring board 1 and the semiconductor chip 5 are heated at 150 ° C. lower than the melting temperature of the bump electrodes 2 and 6.
Was left in the oven set for 1 hour to cure the resin composition layer 3 (step (vi)). Finally, an external bump electrode 8 was formed on the wiring board 1 to obtain a semiconductor device (step (vii)). In this embodiment, the bump electrodes 2, 6
Since gold having a melting point of 1000 ° C. or more was used, no melting occurred during the formation of the external bump electrode 8 as in Example 2.
【0081】実施例4.図1の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。Embodiment 4 FIG. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate.
【0082】接続方法は、まず、配線基板1上に錫−鉛
系(錫63重量%)の共晶半田バンプ電極2を形成し、
バンプ電極2付き配線基板1を作製した(工程(i
i))。次にこの配線基板1上に樹脂組成物(C)―1
を第1の樹脂組成物層31として加熱(80℃)印刷後
(工程(iii)―1)、さらに樹脂組成物(C)―2
を第2の樹脂組成物層32として加熱(80℃)印刷
し、樹脂組成物層3を形成した(工程(iii)―
2)。以後、実施例1と同様の工程にて、加熱、接合、
樹脂硬化、外部バンプ8電極形成を行い半導体装置を得
た。The connection method is as follows. First, a eutectic solder bump electrode 2 of tin-lead (63% by weight of tin) is formed on a wiring board 1,
The wiring substrate 1 with the bump electrodes 2 was manufactured (step (i)
i)). Next, the resin composition (C) -1 is placed on the wiring board 1.
Is printed as a first resin composition layer 31 after heating (80 ° C.) (step (iii) -1), and further, a resin composition (C) -2
Was printed as a second resin composition layer 32 by heating (80 ° C.) to form a resin composition layer 3 (step (iii)).
2). Thereafter, in the same steps as in Example 1, heating, bonding,
The semiconductor device was obtained by curing the resin and forming the eight external bump electrodes.
【0083】実施例5.図1の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。Embodiment 5 FIG. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate.
【0084】接続方法は、まず、配線基板1上に錫−鉛
系(錫63重量%)の共晶半田バンプ電極2を形成し、
バンプ電極2付き配線基板1を作製した(工程(i
i))。次にこの配線基板1上にフィルム状の樹脂組成
物(D)―1を第1の樹脂組成物層31として加熱加圧
(80℃、10秒、0.1kgf/mm2)して貼り付
け(工程(iii)―1)、さらにその上に樹脂組成物
(D)―2を第2の樹脂組成物層32として加熱(80
℃)印刷し、樹脂組成物層3を形成した(工程(ii
i)―2)。以後、実施例1と同様の工程にて、加熱、
接合、樹脂硬化、外部バンプ電極8形成を行い半導体装
置を得た。The connection method is as follows. First, a eutectic solder bump electrode 2 of tin-lead (63% by weight of tin) is formed on a wiring board 1,
The wiring substrate 1 with the bump electrodes 2 was manufactured (step (i)
i)). Next, a film-shaped resin composition (D) -1 is applied as a first resin composition layer 31 on the wiring board 1 by applying heat and pressure (80 ° C., 10 seconds, 0.1 kgf / mm 2 ). (Step (iii) -1), and further heating the resin composition (D) -2 as a second resin composition layer 32 thereon (80).
° C) to form a resin composition layer 3 (step (ii)
i) -2). Thereafter, in the same process as in Example 1, heating,
Bonding, resin curing, and formation of the external bump electrode 8 were performed to obtain a semiconductor device.
【0085】実施例6.図2の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。接続方法は、まず、配線基板1上に
錫−鉛系(錫63重量%)の共晶半田バンプ電極2を形
成し、バンプ電極2付き配線基板1を作製した(工程
(ii))。次にこの配線基板1上にフィルム状の樹脂
組成物(E)―1を第1の樹脂組成物層31として加熱
加圧(80℃、10秒、0.1kgf/mm2)して貼
り付け(工程(iii)―1)、その上に第2の樹脂組
成物層32としてディスペンサ10で樹脂組成物(E)
―2を中央部が凸型に表面形状が半球状になるようディ
スペンスした(工程(iii)―2)。以後、実施例1
と同様の工程にて、加熱、接合、樹脂硬化、外部バンプ
電極8形成を行い半導体装置を得た。Embodiment 6 FIG. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate. In the connection method, first, a eutectic solder bump electrode 2 of a tin-lead system (63% by weight of tin) was formed on the wiring substrate 1, and the wiring substrate 1 with the bump electrode 2 was manufactured (step (ii)). Next, a film-shaped resin composition (E) -1 is applied as a first resin composition layer 31 on the wiring board 1 by applying heat and pressure (80 ° C., 10 seconds, 0.1 kgf / mm 2 ). (Step (iii) -1), on which the resin composition (E) is formed as a second resin composition layer 32 by the dispenser 10.
-2 was dispensed such that the central portion was convex and the surface shape was hemispherical (step (iii) -2). Hereinafter, Example 1
In the same steps as those described above, heating, bonding, resin curing, and formation of the external bump electrode 8 were performed to obtain a semiconductor device.
【0086】実勢例7.図2の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。接続方法は、まず、配線基板1上に
金バンプ電極2を形成し、バンプ電極2付き配線基板1
を作製した(工程(ii))。次に、この配線基板1上
にフィルム状の樹脂組成物(F)―1を第1の樹脂組成
物層31として加熱加圧(80℃、10秒、0.1kg
f/mm2)して貼り付け(工程(iii)―1)、そ
の上に第2の樹脂組成物層32としてディスペンサ10
で樹脂組成物(F)―2を中央部が凸型に表面形状が半
球状になるようディスペンスした(工程(iii)―
2)。以後、実施例3と同様の工程にて、加熱、接合、
樹脂硬化、外部バンプ電極8形成を行い半導体装置を得
た。Practical example 7. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate. The connection method is as follows. First, a gold bump electrode 2 is formed on a wiring substrate 1, and the wiring substrate 1 with the bump electrode 2 is formed.
Was prepared (step (ii)). Next, the film-shaped resin composition (F) -1 was heated and pressed (80 ° C., 10 seconds, 0.1 kg) on the wiring board 1 as a first resin composition layer 31.
f / mm 2 ) and affixed (step (iii) -1), on which the dispenser 10 is formed as a second resin composition layer 32.
The resin composition (F) -2 was dispensed so that the central part was convex and the surface shape was hemispherical (step (iii)).
2). Thereafter, in the same steps as in Example 3, heating, bonding,
The resin was cured and the external bump electrodes 8 were formed to obtain a semiconductor device.
【0087】実施例8.図3の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。接続方法は、まず、配線基板1上に
錫−鉛系(錫63重量%)の共晶半田バンプ電極2を形
成し、バンプ電極2付き配線基板1を作製した(工程
(ii))。次に、この配線基板1上に下層から上層に
かけて徐々に溶融粘度が低くなる傾斜フィルム状の樹脂
組成物(G)を加熱加圧(80℃、10秒、0.1kg
f/mm2)として樹脂組成物層3を形成した(工程
(iii))。以後、実施例1と同様の工程にて、加
熱、接合、樹脂硬化、外部バンプ電極8形成を行い半導
体装置を得た。Embodiment 8 FIG. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate. In the connection method, first, a eutectic solder bump electrode 2 of a tin-lead system (63% by weight of tin) was formed on the wiring substrate 1, and the wiring substrate 1 with the bump electrode 2 was manufactured (step (ii)). Next, a resin composition (G) in the form of a gradient film, whose melt viscosity gradually decreases from the lower layer to the upper layer, is heated and pressed (80 ° C., 10 seconds, 0.1 kg) on the wiring board 1.
f / mm 2 ) to form the resin composition layer 3 (step (iii)). Thereafter, in the same steps as in Example 1, heating, bonding, resin curing, and formation of the external bump electrode 8 were performed to obtain a semiconductor device.
【0088】実施例9.図4の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。接続方法は、まず、配線基板1上に
フィルム状の樹脂組成物(E)―1を第1の樹脂組成物
層31として加熱加圧(80℃、10秒、0.1kgf
/mm2)して貼り付け(工程(iii)―1)、その
上に第2の樹脂組成物層32としてディスペンサ10で
樹脂組成物(E)―2を中央部が凸型に表面形状が半球
状になるようディスペンスした(工程(iii)―
2)。以後、実施例1と同様の工程にて、加熱、接合、
樹脂硬化、外部バンプ電極8形成を行い半導体装置を得
た。Embodiment 9 FIG. Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate. The connection method is as follows. First, a film-shaped resin composition (E) -1 is formed on the wiring substrate 1 as a first resin composition layer 31 by heating and pressing (80 ° C., 10 seconds, 0.1 kgf).
/ Mm 2 ) and affixed (step (iii) -1), on which the resin composition (E) -2 was formed as a second resin composition layer 32 by the dispenser 10 so that the central part was convex and the surface shape was convex. Dispensed into a hemispherical shape (step (iii))
2). Thereafter, in the same steps as in Example 1, heating, bonding,
The resin was cured and the external bump electrodes 8 were formed to obtain a semiconductor device.
【0089】実施例10.図5の工程に従って配線基板
1と半導体チップ5とを接続して複合回路基体である半
導体装置を製造した。接続方法は、まず、配線基板1上
に錫−鉛系(錫63重量%)の共晶半田バンプ電極2を
形成し、バンプ電極2付き配線基板1を作製した(工程
(ii))。次にこの配線基板1上に樹脂組成物(E)
―1を第1の樹脂組成物層31として加熱(80℃)印
刷後(工程(iii)―1)、さらにその上に樹脂組成
物(E)―2を第2の樹脂組成物層32として加熱印刷
し、樹脂組成物層3を形成した(工程(iii)―
2)。Embodiment 10 FIG. By connecting the wiring board 1 and the semiconductor chip 5 according to the process of FIG. 5, a semiconductor device as a composite circuit base was manufactured. In the connection method, first, a eutectic solder bump electrode 2 of a tin-lead system (63% by weight of tin) was formed on the wiring substrate 1, and the wiring substrate 1 with the bump electrode 2 was manufactured (step (ii)). Next, a resin composition (E) is
-1 as a first resin composition layer 31 after heating (80 ° C.) printing (step (iii) -1), and further thereon a resin composition (E) -2 as a second resin composition layer 32 Heat printing was performed to form a resin composition layer 3 (step (iii))
2).
【0090】次に、フリップチップボンダ上で樹脂組成
物層3を形成した配線基板1を所定温度(150℃)に
設定した加熱ステージ4に位置決めして固定した(工程
(iv))。また、半導体チップ5を加熱ヘッド7(1
50℃)に位置決めして固定した。表2より、樹脂組成
物(E)―1は室温で液状、樹脂組成物(E)―2の溶
融温度は80℃であり、加熱ステージ4が150℃に加
温されているため配線基板1に形成した樹脂組成物層3
は溶融状態となっている。Next, the wiring board 1 on which the resin composition layer 3 was formed on the flip chip bonder was positioned and fixed on the heating stage 4 set at a predetermined temperature (150 ° C.) (step (iv)). The semiconductor chip 5 is connected to the heating head 7 (1
(50 ° C.) and fixed. From Table 2, the resin composition (E) -1 is liquid at room temperature, the melting temperature of the resin composition (E) -2 is 80 ° C., and the wiring board 1 is heated because the heating stage 4 is heated to 150 ° C. Resin composition layer 3 formed on
Is in a molten state.
【0091】以後、実施例1と同様の工程にて、接合、
樹脂硬化、外部バンプ電極8形成を行い半導体装置を得
た。Thereafter, bonding and bonding are performed in the same steps as in the first embodiment.
The resin was cured and the external bump electrodes 8 were formed to obtain a semiconductor device.
【0092】実施例11.図3の工程に従って配線基板
1と半導体チップ5とを接続して複合回路基体である半
導体装置を製造した。接続方法は、まず、配線基板1上
に金バンプ電極2を形成し、バンプ電極2付き配線基板
1を作製した(工程(ii))。次にこの配線基板1上
に2層フィルム状の樹脂組成物(H)を加熱加圧(80
℃、10秒、0.1kgf/mm2)して樹脂組成物層
3を形成した(工程(iii))。次に、フリップチッ
プボンダ上で樹脂組成物層3を形成した配線基板1を所
定温度(180℃)に設定した加熱ステージ4に位置決
めして固定した(工程(iv))。また、バンプ電極6
付き半導体チップ5を加熱ヘッド7(180℃)に位置
決めして固定した。表2より樹脂組成物(H)の溶融温
度は150℃であり、加熱ステージ4がそれより高い1
80℃に加温されているため、配線基板1に形成した樹
脂組成物層3は溶融状態となっている。Embodiment 11 FIG. According to the process of FIG. 3, the wiring substrate 1 and the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate. In the connection method, first, the gold bump electrodes 2 were formed on the wiring substrate 1, and the wiring substrate 1 with the bump electrodes 2 was manufactured (step (ii)). Next, the resin composition (H) in the form of a two-layer film is heated and pressurized (80
C., 10 seconds, 0.1 kgf / mm 2 ) to form a resin composition layer 3 (step (iii)). Next, the wiring board 1 on which the resin composition layer 3 was formed on the flip chip bonder was positioned and fixed on the heating stage 4 set at a predetermined temperature (180 ° C.) (step (iv)). Also, the bump electrode 6
The attached semiconductor chip 5 was positioned and fixed to the heating head 7 (180 ° C.). From Table 2, the melting temperature of the resin composition (H) is 150 ° C.
Since the substrate is heated to 80 ° C., the resin composition layer 3 formed on the wiring board 1 is in a molten state.
【0093】次に、加熱ヘッド7を動かし、加熱ヘッド
7に固定した半導体チップ5のバンプ電極6と加熱ステ
ージ4に固定した配線基板1上のバンプ電極2とを一定
圧(15kgf/チップ)を加えて接触させた。配線基
板1と半導体チップ5双方の金バンプ2、6は接触した
(工程(v))。この際、溶融粘度が低い第2の樹脂組
成物層32は樹脂組成物層3に生じる凹凸を平坦化する
のに使用され、大半は半導体チップ5が配線基板1に接
合する際に外に押し出され、一部は樹脂組成物層3中に
残る。次に、所定のプロファイルで加熱ヘッド7を降温
して配線基板1、半導体チップ5、バンプ電極2、6、
および樹脂組成物層3を100℃まで冷却した。する
と、溶融していた樹脂組成物層3は固化した。 最後に
配線基板1に外部電極8を形成し半導体装置を得た(工
程(vii))。Next, the heating head 7 is moved, and the bump electrode 6 of the semiconductor chip 5 fixed to the heating head 7 and the bump electrode 2 on the wiring board 1 fixed to the heating stage 4 are applied with a constant pressure (15 kgf / chip). In addition, contact was made. The gold bumps 2 and 6 of both the wiring board 1 and the semiconductor chip 5 were in contact (step (v)). At this time, the second resin composition layer 32 having a low melt viscosity is used to flatten the unevenness generated in the resin composition layer 3, and most of the second resin composition layer 32 is pushed out when the semiconductor chip 5 is joined to the wiring board 1. And a part remains in the resin composition layer 3. Next, the temperature of the heating head 7 is lowered according to a predetermined profile, and the wiring substrate 1, the semiconductor chip 5, the bump electrodes 2, 6,
And the resin composition layer 3 was cooled to 100 degreeC. Then, the molten resin composition layer 3 was solidified. Finally, external electrodes 8 were formed on the wiring substrate 1 to obtain a semiconductor device (step (vii)).
【0094】比較例1.図6は比較例1による回路基体
の接続方法を工程順に示す説明図である。図6の工程に
従って配線基板1と半導体チップ5とを接続して複合回
路基体である半導体装置を製造した。Comparative Example 1 FIG. 6 is an explanatory view showing a method of connecting circuit substrates according to Comparative Example 1 in the order of steps. By connecting the wiring board 1 and the semiconductor chip 5 according to the process of FIG. 6, a semiconductor device as a composite circuit base was manufactured.
【0095】接続方法は、まず、配線基板1上に錫−鉛
系(錫63重量%)の共晶半田バンプ電極2を形成し、
バンプ電極2付き配線基板1を作製した(工程(i
i))。次にこの配線基板1上に単層フィルム状の樹脂
組成物(I)を加熱加圧(80℃、10秒、0.1kg
f/mm2)して貼り付け、配線基板1上に樹脂組成物
層3を形成した(工程(iii))。以後、実施例1と
同様の工程にて、加熱、接合、樹脂硬化、外部バンプ電
極8形成を行い半導体装置を得た。The connection method is as follows. First, a eutectic solder bump electrode 2 of tin-lead (63% by weight of tin) is formed on a wiring board 1,
The wiring substrate 1 with the bump electrodes 2 was manufactured (step (i)
i)). Next, the resin composition (I) in the form of a single-layer film is heated and pressed (80 ° C., 10 seconds, 0.1 kg) on the wiring board 1.
f / mm 2 ) and affixed to form a resin composition layer 3 on the wiring board 1 (step (iii)). Thereafter, in the same steps as in Example 1, heating, bonding, resin curing, and formation of the external bump electrode 8 were performed to obtain a semiconductor device.
【0096】比較例2.図6の工程に従って配線基板1
と半導体チップ5とを接続して複合回路基体である半導
体装置を製造した。Comparative Example 2 Wiring board 1 according to the process of FIG.
And the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate.
【0097】接続方法は、まず、配線基板1上に金バン
プ電極2を形成し、バンプ電極2付き配線基板1を作製
した(工程(ii))。次にこの配線基板1上にフィル
ム状の樹脂組成物(J)を加熱加圧(80℃、10秒、
0.1kgf/mm2)して貼り付け、配線基板1上に
樹脂組成物層3を形成した(工程(iii))。以後、
実施例3と同様の工程にて、加熱、接合、樹脂硬化、外
部バンプ電極8形成を行い半導体装置を得た。[0097] In the connection method, first, the gold bump electrodes 2 were formed on the wiring substrate 1, and the wiring substrate 1 with the bump electrodes 2 was manufactured (step (ii)). Next, the film-shaped resin composition (J) is heated and pressed (80 ° C., 10 seconds,
0.1 kgf / mm 2 ) and affixed to form a resin composition layer 3 on the wiring board 1 (step (iii)). Since then
In the same steps as in Example 3, heating, bonding, resin curing, and formation of external bump electrodes 8 were performed to obtain a semiconductor device.
【0098】比較例3.図7は比較例3による回路基体
の接続方法を工程順に示す説明図である。図7の工程に
従って配線基板1と半導体チップ5とを接続して複合回
路基体である半導体装置を製造した。Comparative Example 3 FIG. 7 is an explanatory view showing a method of connecting circuit substrates according to Comparative Example 3 in the order of steps. According to the process of FIG. 7, the wiring board 1 and the semiconductor chip 5 were connected to manufacture a semiconductor device as a composite circuit substrate.
【0099】接続方法は、まず、配線基板1上に錫−鉛
系(錫63重量%)の共晶半田バンプ電極2を形成し、
バンプ電極2付き配線基板1を作製した(工程(i
i))。The connection method is as follows. First, a eutectic solder bump electrode 2 of tin-lead (63% by weight of tin) is formed on a wiring board 1,
The wiring substrate 1 with the bump electrodes 2 was manufactured (step (i)
i)).
【0100】次に、この配線基板1上にディスペンサ1
0で樹脂組成物(K)を中央部が凸型で表面形状が半球
状になるようディスペンスした(工程(iii))。以
後、実施例1と同様の工程にて、加熱、接合、樹脂硬
化、外部バンプ電極8形成を行い半導体装置を得た。Next, the dispenser 1 is placed on the wiring board 1.
At 0, the resin composition (K) was dispensed so that the central portion was convex and the surface shape was hemispherical (step (iii)). Thereafter, in the same steps as in Example 1, heating, bonding, resin curing, and formation of the external bump electrode 8 were performed to obtain a semiconductor device.
【0101】実施例1〜11および比較例1〜3で作製
した半導体装置の樹脂組成物層3に存在するボイドを確
認するため、超音波顕微鏡および断面研磨による観察を
行った。表3には観察の結果を示す。In order to confirm the voids present in the resin composition layers 3 of the semiconductor devices manufactured in Examples 1 to 11 and Comparative Examples 1 to 3, observations were made with an ultrasonic microscope and section polishing. Table 3 shows the results of the observation.
【0102】[0102]
【表3】 [Table 3]
【0103】表3より、実施例1〜11に基づいて作製
した半導体装置の樹脂組成物層3にはボイドが観察され
なかった。これに対して、比較例3に基づいて作製した
半導体装置の樹脂組成物層3にはボイドが観察されなか
ったものの、比較例1および2に基づいて作製した半導
体装置の樹脂組成物層3には半導体チップ5と配線基板
1とを接合した際に、閉じこめられたとみられる空気層
(ボイド)が観察された。From Table 3, no voids were observed in the resin composition layer 3 of the semiconductor devices manufactured based on Examples 1 to 11. On the other hand, although no void was observed in the resin composition layer 3 of the semiconductor device manufactured based on Comparative Example 3, the resin composition layer 3 of the semiconductor device manufactured based on Comparative Examples 1 and 2 did not. When the semiconductor chip 5 and the wiring substrate 1 were joined, an air layer (void) which was considered to be trapped was observed.
【0104】次に、実施例1〜11および比較例3に基
づいて作製した半導体装置について、1サイクルが−4
0℃/30分〜125℃/30分である温度サイクル試
験を1000サイクル行った。その結果を表3に示す。
表3より、実施例1〜11に基づいて作製した半導体装
置において接続抵抗の変化は認められなかった。これに
対して、比較例3に基づいて作製した半導体装置は10
00サイクル後の導通測定評価でオープン不良となっ
た。Next, in the semiconductor device manufactured based on Examples 1 to 11 and Comparative Example 3, one cycle was -4.
1000 cycles of a temperature cycle test at 0 ° C./30 minutes to 125 ° C./30 minutes were performed. Table 3 shows the results.
From Table 3, no change in the connection resistance was observed in the semiconductor devices manufactured based on Examples 1 to 11. On the other hand, the semiconductor device manufactured based on Comparative Example 3 has 10
An open failure was found in the continuity measurement evaluation after 00 cycles.
【0105】[0105]
【発明の効果】本発明の第1の方法に係る回路基体の接
続方法は、第1の回路基体の配線面上に第1の樹脂組成
物層を形成し、第1の樹脂組成物層上または第2の回路
基体の配線面上に第1の樹脂組成物層より溶融粘度の低
い第2の樹脂組成物層を形成し、第1と第2の回路基体
の配線面をバンプ電極を介在させて対向配置し、第1と
第2の回路基体間を前記樹脂組成物で接合するととも
に、前記回路基体相互の配線間を前記バンプ電極で電気
的に接続するので、樹脂組成物層に残るボイドを低減
し、しかも樹脂組成物層と回路基体との間の熱応力も低
減して信頼性の高い回路基体の接続方法を得ることがで
きる。According to the first method of the present invention, a method for connecting a circuit substrate includes forming a first resin composition layer on a wiring surface of the first circuit substrate, and forming the first resin composition layer on the first resin composition layer. Alternatively, a second resin composition layer having a lower melt viscosity than the first resin composition layer is formed on the wiring surface of the second circuit substrate, and the wiring surfaces of the first and second circuit substrates are interposed with bump electrodes. And the first and second circuit boards are joined with the resin composition, and the wiring between the circuit boards is electrically connected with the bump electrodes, so that the wiring remains on the resin composition layer. The voids are reduced, and the thermal stress between the resin composition layer and the circuit substrate is also reduced, so that a highly reliable circuit substrate connection method can be obtained.
【0106】本発明の第2の方法に係る回路基体の接続
方法は、上記第1の方法において、回路基体は半導体チ
ップまたは配線基板であるので、樹脂組成物層に残るボ
イドを低減し、しかも樹脂組成物層と回路基体との間の
熱応力も低減して信頼性の高い半導体装置や多層配線基
板を得ることができる。According to the method for connecting a circuit substrate according to the second method of the present invention, since the circuit substrate is a semiconductor chip or a wiring substrate in the first method, voids remaining in the resin composition layer can be reduced. The thermal stress between the resin composition layer and the circuit substrate is also reduced, so that a highly reliable semiconductor device or multilayer wiring board can be obtained.
【0107】本発明の第3の方法に係る回路基体の接続
方法は、上記第1または第2の方法において、第1の回
路基体の配線面上に第1の樹脂組成物層を形成した後
に、第2の樹脂組成物層を形成するので、あらかじめ2
層構造での入手が困難であるが、単独で材料特性が良好
なものを組み合わせて使用することができる。The method for connecting a circuit board according to the third method of the present invention is the method for connecting a circuit board according to the first or second method, after forming the first resin composition layer on the wiring surface of the first circuit board. , The second resin composition layer is formed.
Although it is difficult to obtain a layered structure, those having good material properties can be used alone.
【0108】本発明の第4の方法に係る回路基体の接続
方法は、上記第3の方法において、第2の樹脂組成物層
の表面形状を半球状に形成するので、回路基体を接合す
る際に第2の樹脂組成物を周辺に流してボイドの発生を
効果的に抑制することができる。In the method for connecting circuit boards according to the fourth method of the present invention, since the surface shape of the second resin composition layer is formed to be hemispherical in the above-described third method, the circuit board can be connected with the circuit board at a time of joining. In addition, the second resin composition can be flowed to the periphery to effectively suppress the generation of voids.
【0109】本発明の第5の方法に係る回路基体の接続
方法は、上記第3または第4の方法において、第2の樹
脂組成物層として、室温で液状である樹脂組成物を用い
るので、樹脂組成物の塗布が容易となる。特に、ディス
ペンス法等により樹脂組成物層の表面形状を半球状に形
成するのに有利である。In the method of connecting a circuit substrate according to the fifth method of the present invention, a resin composition that is liquid at room temperature is used as the second resin composition layer in the third or fourth method. The application of the resin composition becomes easy. In particular, it is advantageous for forming the surface shape of the resin composition layer into a hemispherical shape by a dispensing method or the like.
【0110】本発明の第6の方法に係る回路基体の接続
方法は、上記第1または第2の方法において、第1の樹
脂組成物層上に第2の樹脂組成物層を積層した構成のフ
ィルムを、第1の回路基体の配線面に貼り付けるので、
樹脂組成物がフィルムのため取り扱いが容易であり、生
産効率の向上が可能である。The method of connecting a circuit substrate according to the sixth method of the present invention is the same as the first or second method, except that the second resin composition layer is laminated on the first resin composition layer. Since the film is attached to the wiring surface of the first circuit substrate,
Since the resin composition is a film, it is easy to handle and the production efficiency can be improved.
【0111】本発明の第7の方法に係る回路基体の接続
方法は、上記第1ないし第6のうちのいずれかの方法に
おいて、第2の樹脂組成物層の樹脂量が第1の樹脂組成
物層の樹脂量より少ないので、第2の樹脂組成物層の大
半がボイドと共に流れ出しても、第1の樹脂組成物層で
回路基体間に必要な樹脂量を確保でき、また、流れ出し
た樹脂組成物が過剰になることを防止できる。The method for connecting a circuit substrate according to a seventh method of the present invention is the method according to any one of the first to sixth methods, wherein the amount of resin in the second resin composition layer is less than the first resin composition. Since the amount of resin in the second resin composition layer is smaller than the amount of resin in the first resin composition layer, the first resin composition layer can secure the required amount of resin between circuit substrates even if most of the second resin composition layer flows out. The composition can be prevented from becoming excessive.
【0112】本発明の第8の方法に係る回路基体の接続
方法は、上記第1ないし第7のうちのいずれかの方法に
おいて、第1および第2の樹脂組成物層はバンプ電極の
融点より低い温度で溶融するので、バンプ電極を溶融さ
せることなく樹脂組成物層は溶融した状態で精度の高い
位置合わせが可能となり、電気的接続の信頼性が向上す
る。The method of connecting a circuit substrate according to an eighth method of the present invention is the method according to any one of the first to seventh methods, wherein the first and second resin composition layers are formed by melting the bump electrode at a melting point. Since the resin composition layer is melted at a low temperature, the resin composition layer can be aligned with high accuracy without melting the bump electrode, and the reliability of electrical connection is improved.
【0113】本発明の第9の方法に係る回路基体の接続
方法は、上記第1ないし第8のうちのいずれかの方法に
おいて、第1または第2の樹脂組成物層がエポキシ樹脂
を含むので、樹脂組成物に接着性を付与することができ
る。The method of connecting a circuit substrate according to the ninth method of the present invention is the same as the method of any one of the first to eighth methods, since the first or second resin composition layer contains an epoxy resin. It is possible to impart adhesiveness to the resin composition.
【0114】本発明の第10の方法に係る回路基体の接
続方法は、上記第1ないし第8のうちのいずれかの方法
において、第1または第2の樹脂組成物層がエポキシ樹
脂およびフェノール硬化剤を含むので、エポキシ樹脂に
より樹脂組成物に接着性を付与することができるととも
に、フェノール硬化剤により加水分解性の心配無くエポ
キシ樹脂を硬化させることができる。According to a tenth method of the present invention, there is provided a method of connecting a circuit substrate according to any one of the first to eighth methods, wherein the first or second resin composition layer is made of an epoxy resin and a phenol cured resin. Since the resin composition contains the agent, the epoxy resin can impart adhesiveness to the resin composition, and the phenol curing agent can cure the epoxy resin without concern for hydrolysis.
【0115】本発明の第11の方法に係る回路基体の接
続方法は、上記第1ないし第10のうちのいずれかの方
法において、第1または第2の樹脂組成物層が充填剤を
含むので、樹脂組成物層の熱膨張係数を小さくし、回路
基体と樹脂組成物間に発生する熱応力を低減でき、さら
に低吸水性を付与することもできる。The method for connecting a circuit substrate according to the eleventh method of the present invention is the same as the method of any one of the first to tenth methods, since the first or second resin composition layer contains a filler. In addition, the thermal expansion coefficient of the resin composition layer can be reduced, the thermal stress generated between the circuit substrate and the resin composition can be reduced, and low water absorption can be imparted.
【0116】本発明の第12の方法に係る回路基体の接
続方法は、上記第1ないし第11のうちのいずれかの方
法において、第1と第2の回路基体の両方にバンプ電極
を形成するので、回路基体の反りやうねり、各バンプ電
極の高さのバラツキ等を緩衝でき、より確実に電気的接
続を行うことか可能となる。According to a twelfth method of the present invention, in any one of the first to eleventh methods, bump electrodes are formed on both the first and second circuit substrates. Therefore, warpage and undulation of the circuit substrate, variations in the height of the bump electrodes, and the like can be buffered, and the electrical connection can be performed more reliably.
【0117】本発明の第1の構成に係る複合回路基体
は、上記第1ないし第12のいずれかに記載の回路基体
の接続方法を用いて製造したので、樹脂組成物層に残る
ボイドを低減し、しかも樹脂組成物層と回路基体との間
の熱応力も低減して信頼性の高い複合回路基体を得るこ
とができる。Since the composite circuit board according to the first aspect of the present invention is manufactured by using the circuit board connecting method according to any one of the first to twelfth aspects, the voids remaining in the resin composition layer are reduced. In addition, the thermal stress between the resin composition layer and the circuit substrate is reduced, and a highly reliable composite circuit substrate can be obtained.
【0118】本発明の第2の構成に係る複合回路基体
は、対向配置された回路基体間が樹脂組成物で接合され
ると共に回路基体相互の配線間がバンプ電極で電気的に
接続された複合回路基体であって、前記樹脂組成物は溶
融粘度の異なる複数種類の樹脂組成物であるので、樹脂
組成物層に残るボイドを低減し、しかも樹脂組成物層と
回路基体との間の熱応力も低減して信頼性の高い複合回
路基体を得ることができる。The composite circuit substrate according to the second configuration of the present invention is a composite circuit substrate in which opposing circuit substrates are joined with a resin composition and wiring between the circuit substrates is electrically connected by bump electrodes. A circuit substrate, wherein the resin composition is a plurality of types of resin compositions having different melt viscosities, so that voids remaining in the resin composition layer are reduced, and thermal stress between the resin composition layer and the circuit substrate is reduced. And a highly reliable composite circuit substrate can be obtained.
【図1】 本発明の実施の形態1による回路基体の接続
方法を工程順に示す説明図である。FIG. 1 is an explanatory view showing a method of connecting circuit substrates according to a first embodiment of the present invention in the order of steps.
【図2】 本発明の実施の形態2による回路基体の接続
方法を工程順に示す説明図である。FIG. 2 is an explanatory view showing a method of connecting circuit substrates according to a second embodiment of the present invention in the order of steps.
【図3】 本発明の実施の形態3による回路基体の接続
方法を工程順に示す説明図である。FIG. 3 is an explanatory view showing a method of connecting circuit substrates according to a third embodiment of the present invention in the order of steps.
【図4】 本発明の実施の形態4による回路基体の接続
方法を工程順に示す説明図である。FIG. 4 is an explanatory view showing a method of connecting a circuit substrate according to a fourth embodiment of the present invention in the order of steps.
【図5】 本発明の実施の形態5による回路基体の接続
方法を工程順に示す説明図である。FIG. 5 is an explanatory view showing a method of connecting circuit substrates according to a fifth embodiment of the present invention in the order of steps.
【図6】 比較例による回路基体の接続方法を工程順に
示す説明図である。FIG. 6 is an explanatory view showing a method of connecting circuit substrates according to a comparative example in the order of steps.
【図7】 別の比較例による回路基体の接続方法を工程
順に示す説明図である。FIG. 7 is an explanatory view showing a method of connecting circuit substrates according to another comparative example in the order of steps.
1 第2の回路基体(配線基板)、2 バンプ電極、3
樹脂組成物層、31第1の樹脂組成物、32 第2の
樹脂組成物層、4 加熱ステージ、5 第2の回路基体
(半導体チップ)、6 バンプ電極、7 加熱ヘッド、
8 外部バンプ電極、10 ディスペンサ。1 second circuit substrate (wiring board), 2 bump electrode, 3
Resin composition layer, 31 first resin composition, 32 second resin composition layer, 4 heating stage, 5 second circuit substrate (semiconductor chip), 6 bump electrode, 7 heating head,
8 External bump electrodes, 10 dispensers.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 藤岡 弘文 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 冨田 至洋 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 上田 直人 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 Fターム(参考) 5E319 AA03 AB05 BB04 BB20 CC33 CC58 CD16 GG05 5E346 AA22 CC09 CC41 EE12 FF24 GG25 GG28 HH11 5F044 KK01 KK16 LL11 QQ01 RR17 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirofumi Fujioka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Toshihiro Tomita 2-3-2 Marunouchi, Chiyoda-ku, Tokyo (72) Inventor Naoto Ueda 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5E319 AA03 AB05 BB04 BB20 CC33 CC58 CD16 GG05 5E346 AA22 CC09 CC41 EE12 FF24 GG25 GG28 HH11 5F044 KK01 KK16 LL11 QQ01 RR17
Claims (14)
組成物層を形成し、第1の樹脂組成物層上または第2の
回路基体の配線面上に第1の樹脂組成物層より溶融粘度
の低い第2の樹脂組成物層を形成し、第1と第2の回路
基体の配線面をバンプ電極を介在させて対向配置し、第
1と第2の回路基体間を前記樹脂組成物で接合するとと
もに、前記回路基体相互の配線間を前記バンプ電極で電
気的に接続することを特徴とする回路基体の接続方法。A first resin composition layer is formed on a wiring surface of a first circuit substrate, and a first resin composition layer is formed on the first resin composition layer or on a wiring surface of a second circuit substrate. Forming a second resin composition layer having a lower melt viscosity than the material layer, arranging the wiring surfaces of the first and second circuit substrates facing each other with a bump electrode interposed therebetween, and connecting the first and second circuit substrates. A method of connecting a circuit substrate, comprising: bonding with the resin composition; and electrically connecting the wiring between the circuit substrates with the bump electrode.
である請求項1記載の回路基体の接続方法。2. The method according to claim 1, wherein the circuit substrate is a semiconductor chip or a wiring substrate.
組成物層を形成した後に、第2の樹脂組成物層を形成す
ることを特徴とする請求項1または2記載の回路基体の
接続方法。3. The circuit according to claim 1, wherein the second resin composition layer is formed after the first resin composition layer is formed on the wiring surface of the first circuit substrate. How to connect the substrate.
に形成することを特徴とする請求項3記載の回路基体の
接続方法。4. The method according to claim 3, wherein the surface of the second resin composition layer is formed in a hemispherical shape.
である樹脂組成物を用いることを特徴とする請求項3ま
たは4記載の回路基体の接続方法。5. The method according to claim 3, wherein a resin composition that is liquid at room temperature is used as the second resin composition layer.
物層を積層した構成のフィルムを、第1の回路基体の配
線面に貼り付けることを特徴とする請求項1または2記
載の回路基体の接続方法。6. A film having a structure in which a second resin composition layer is laminated on a first resin composition layer is attached to a wiring surface of a first circuit substrate. The method for connecting circuit substrates according to the above.
脂組成物層の樹脂量より少ないことを特徴とする請求項
1ないし6のいずれかに記載の回路基体の接続方法。7. The method for connecting circuit boards according to claim 1, wherein the amount of resin in the second resin composition layer is smaller than the amount of resin in the first resin composition layer.
電極の融点より低い温度で溶融することを特徴とする請
求項1ないし7のいずれかに記載の回路基体の接続方
法。8. The method according to claim 1, wherein the first and second resin composition layers are melted at a temperature lower than a melting point of the bump electrode.
シ樹脂を含むことを特徴とする請求項1ないし8のいず
れかに記載の回路基体の接続方法。9. The method according to claim 1, wherein the first or second resin composition layer contains an epoxy resin.
キシ樹脂およびフェノール硬化剤を含むことを特徴とす
る請求項1ないし8のいずれかに記載の回路基体の接続
方法。10. The method according to claim 1, wherein the first or second resin composition layer contains an epoxy resin and a phenol curing agent.
剤を含むことを特徴とする請求項1ないし10のいずれ
かに記載の回路基体の接続方法。11. The method according to claim 1, wherein the first or second resin composition layer contains a filler.
電極を形成することを特徴とする請求項1ないし11の
いずれかに記載の回路基体の接続方法。12. The method according to claim 1, wherein the bump electrodes are formed on both the first and second circuit substrates.
路基体の接続方法を用いて製造した複合回路基体。13. A composite circuit substrate manufactured by using the circuit substrate connection method according to claim 1.
物で接合されると共に回路基体相互の配線間がバンプ電
極で電気的に接続された複合回路基体であって、前記樹
脂組成物は溶融粘度の異なる複数種類の樹脂組成物であ
ることを特徴とする複合回路基体。14. A composite circuit substrate in which opposing circuit substrates are joined by a resin composition and wiring between the circuit substrates is electrically connected by bump electrodes, wherein the resin composition is melted. A composite circuit substrate comprising a plurality of types of resin compositions having different viscosities.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP23038499A JP2001053112A (en) | 1999-08-17 | 1999-08-17 | Method for connecting circuit substrate and composite circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23038499A JP2001053112A (en) | 1999-08-17 | 1999-08-17 | Method for connecting circuit substrate and composite circuit substrate |
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Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP23038499A Pending JP2001053112A (en) | 1999-08-17 | 1999-08-17 | Method for connecting circuit substrate and composite circuit substrate |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930395B2 (en) * | 2000-12-05 | 2005-08-16 | Matsushita Electric Industrial Co., Ltd. | Circuit substrate having improved connection reliability and a method for manufacturing the same |
JP2009259924A (en) * | 2008-04-15 | 2009-11-05 | Shinko Electric Ind Co Ltd | Method of manufacturing semiconductor device |
JP2010245434A (en) * | 2009-04-09 | 2010-10-28 | Panasonic Corp | Solder bonding method and solder bonding structure |
JP2012186511A (en) * | 2012-07-04 | 2012-09-27 | Shinko Electric Ind Co Ltd | Semiconductor device manufacturing method |
-
1999
- 1999-08-17 JP JP23038499A patent/JP2001053112A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6930395B2 (en) * | 2000-12-05 | 2005-08-16 | Matsushita Electric Industrial Co., Ltd. | Circuit substrate having improved connection reliability and a method for manufacturing the same |
JP2009259924A (en) * | 2008-04-15 | 2009-11-05 | Shinko Electric Ind Co Ltd | Method of manufacturing semiconductor device |
JP2010245434A (en) * | 2009-04-09 | 2010-10-28 | Panasonic Corp | Solder bonding method and solder bonding structure |
JP2012186511A (en) * | 2012-07-04 | 2012-09-27 | Shinko Electric Ind Co Ltd | Semiconductor device manufacturing method |
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