JP2000333039A - Contour correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a contour correction device to enhance sharpness of a contour of an original video signal without providing a pre-shoot and an overshoot and without losing the geometrical structure of the original video signal. SOLUTION: A video signal S1 is fed to a correction component generating circuit 4 and delay circuits 3(1) to 3(n+1). A waveform recognition circuit 6 recognizes a waveform pattern in the vicinity of a sample point to be corrected based on output signals S3(1) to S3(n+1), an intermediate limit value generating section 7 and a peak limit value generating section 8 provide an output of output signals S7, S8 with a limit area surrounded by an upper limit and a lower limit based on an output signal S6 of the waveform recognition circuit 6 and the output signals S3(n-1), S3(n), S3(n+1) respectively. An adder circuit 9 sums the signals S3(n) at a sample point to be corrected and an output signal S4 of the correction component generating circuit 4 and an amplitude control circuit 10 conducts amplitude control based on the output signals S7, S8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to various video devices such as a television receiver (TV), a video tape recorder (VTR), and a video disk (LD, DVD, video CD), and various image processing for handling image data. More particularly, the present invention relates to a contour correction device for improving the sharpness of a contour portion and improving image quality.

[0002]

2. Description of the Related Art Conventionally, as a contour correction for improving sharpness of a contour portion for improving image quality, a contour correction component is obtained by a second derivative process, and the correction component is multiplied by an appropriate coefficient and added to an original signal. (For example, Nobuyuki Yagi, et al., "Practical Digital Video Processing Learned in C Language," Ohmsha, published May 10, 1995, p.17
3).

[0003] A conventional contour correction device will be described below. FIG. 21 shows a configuration diagram of a conventional first contour correction device. 21, 1 is an input terminal, 2 is an output terminal, 200 is a correction component generation circuit, 201 to 206 are components of the correction component generation circuit 200,
02 is a delay circuit for delaying a predetermined time, 203 to 205 are multiplication circuits, 206 is an addition circuit, 207 is a gain adjustment circuit for controlling a correction component amount, 208 is a delay circuit for delaying a predetermined time, and 209 is an addition circuit. FIG. 22 shows the operation of each signal shown in FIG.

The operation of the conventional first contour correction device having the structure shown in FIG. 21 will be described with reference to FIGS. 21 and 22. The video signal S1 input from the input terminal 1 is supplied to the delay circuit 201, the delay circuit 208, and the multiplication circuit 205. The output signal S201 of the delay circuit 201 is
02, is supplied to the multiplication circuit 204. The output signal S202 of the delay circuit 202 is supplied to the multiplication circuit 203.

For example, if the video signal S1 is a signal as shown in FIG. 22A, the output signal S201 of the delay circuit 201 and the output signal S202 of the delay circuit 202 are
The signals are as shown in FIGS. 22 (B) and 22 (C). These three signals are supplied to a multiplying circuit 203 having a multiplier of −−１, a multiplying circuit 204 having a multiplier of １ ／, and a multiplying circuit 205 having a multiplier of −−１. The output signal S203 of the multiplication circuit 203 multiplied by the multiplier and the multiplication circuit 20
4 and the output signal S2 of the multiplication circuit 205.
05 is supplied to the adding circuit 206 and added. The addition result of the addition circuit 206 is the output signal S200 of the correction component generation circuit 200, which is a signal obtained by secondarily differentiating the original video signal as shown in FIG.

The output signal S20 of the correction component generation circuit 200
0 is supplied to the gain adjustment circuit 207. Assuming that the gain of the gain adjustment circuit 207 is 2, for example, the output signal S207 of the gain adjustment circuit 207 becomes a signal as shown in FIG. Output signal S207 of gain adjustment circuit 207
Is the output signal S2 of the delay circuit 208 shown in FIG.
08, and supplied to the addition circuit 209 to be added. The addition result of the addition circuit 209 is the output signal S of the contour correction device.
2 is output from the output terminal 2. As can be seen from FIG. 22 (G), the conventional contour correction device configured as described above performs contour correction for improving sharpness while adding preshoot or overshoot to a contour portion for improving image quality. Was completed.

As a second conventional example of improving the sharpness of a contour portion without adding a preshoot or an overshoot, in addition to the above-described conventional first contour correction device, Japanese Patent Application No. 5-316392. There is a contour correction device described in (1). Hereinafter, a second conventional contour correction device will be described. FIG. 23 shows a configuration diagram of a second conventional contour correction device. In FIG. 23, 1 is an input terminal, 2 is an output terminal, 300 to 303 are delay circuits, 304 is a maximum value detection circuit, 305 is a minimum value detection circuit, 306 is a position detection circuit, 307 is an arithmetic circuit, and 308 is an average value. 309 is a subtraction circuit, 310 is a gain adjustment circuit, 311 is an addition circuit, and 312 is a non-linear processing circuit. FIG. 24 corresponds to FIG.
1 shows the operation of each signal shown in FIG.

The operation of the contour correction device having the configuration shown in FIG. 23 will be described with reference to FIGS. The video signal S1 input from the input terminal 1 is applied to the delay circuits 300 to 3
03. Input video signal S1, delay circuit 3
00 output signal S300 and delay circuit 301 output signal S
301, the output signal S302 of the delay circuit 302, and the output signal S303 of the delay circuit 303 are the maximum value detection circuit 304,
It is supplied to the minimum value detection circuit 305 and the position detection circuit 306, respectively. The output signal S301 of the delay circuit 301 is supplied to one input terminal of the subtraction circuit 309 and one input terminal of the addition circuit 311.

The output signal S304 of the maximum value detection circuit 304
Is supplied to the position detection circuit 306, the average value circuit 308, and the nonlinear processing circuit 312, respectively. The output signal S305 of the minimum value detection circuit 305 is
The average value circuit 308 and the non-linear processing circuit 312 are supplied. Output signal S308 of average value circuit 308
Is supplied to the other input terminal of the subtraction circuit 309. The subtraction result S307 of the subtraction circuit 309 and the output signal S306 of the position detection circuit 306 are supplied to the gain adjustment circuit 310, and the output signal S310 of the gain adjustment circuit 310 is output.
Is supplied to the other input terminal of the adder circuit 311. The addition result S311 of the addition circuit 311 is subjected to nonlinear processing in the nonlinear processing circuit 312 according to the output signal S304 from the maximum value detection circuit 304 and the output signal S305 from the minimum value detection circuit 305, and is output from the output terminal 2. .

The operation of the other conventional contour correction device configured as described above will be described with reference to FIGS. In FIG. 23, it is assumed that a video signal having a contour as shown in FIG. This video signal is supplied to delay circuits 300 to 30
24, respectively, and FIG. 24 (B) to FIG.
The signal shown in (E) is obtained. The maximum value detection circuit 304 receives the input signals S1, S300, S301, S302, S
The maximum value is output by comparing the size of 303. Therefore, the output signal S304 of the maximum value detection circuit 304 is
4 (F) is obtained. Minimum value detection circuit 305
Are the input signals S1, S300, S301, S30
2. Compare the magnitudes of S303 and output the minimum value.
Therefore, the output signal S305 of the minimum value detection circuit 305
Obtains the signal shown in FIG. FIG. 24 (F)
The signal shown in FIG. 24 (G) is averaged by the averaging circuit 308 to obtain the signal shown in FIG. 24 (H).

In the subtraction circuit 309, the delay circuit 30
The output signal S308 of the averaging circuit 308 is subtracted from the output signal S301 of 1 to obtain the signal of FIG. The position detection circuit 306 performs a logical operation from the input signal,
When a specific waveform is detected, 0 is output. In the signal as shown in FIG. 24, since a specific waveform is not detected, 1 is output as shown in FIG. Gain adjuster 3
10, the gain is set to 0 when the output signal S306 of the position detection circuit 306 is 0, and the gain adjustment circuit 31 is set when the output signal S306 is 1.
Follows the original gain of zero. When the gain of the gain adjustment circuit 310 is set to, for example, 1, the output signal S31
24 becomes the signal shown in FIG. 24 (K). When the adder 311 adds the signal to the output signal S301 from the delay circuit 301 shown in FIG. 24 (C), the addition result of the adder 311 is shown in FIG. Obtain the signal shown. This signal is output from the nonlinear processing circuit 312 to the output signal S304 of the maximum value detection circuit 304 and the output signal S3 of the minimum value detection circuit 305.
05 is performed in a non-linear manner.

For example, by comparing the magnitudes of the signals shown in FIGS. 24F, 24G, and 24L, FIG.
When the signal shown in (L) is larger than the signal shown in FIG. 24 (F), the signal shown in FIG. 24 (F) is output. FIG. 2
When the signal shown in FIG. 4 (L) is smaller than the signal shown in FIG. 24 (G), the signal shown in FIG. 24 (G) is output. Otherwise, the signal shown in FIG. 24 (F) is output. That is, the amplitude is limited using the detected maximum value or minimum value. According to this, as the output signal S2 of the nonlinear processing circuit 312, a video signal having a steep contour as shown in FIG. With the other conventional contour correction device configured as described above, it was possible to perform contour correction for improving sharpness without adding preshoot or overshoot to a contour portion for improving image quality.

[0013]

However, in the above-described conventional first contour correction device, the effect of the contour correction is small in a smooth contour portion, and a preshoot or an overshoot in a relatively steep contour portion. May occur, which may result in contour correction with an adverse effect such as the formation of a white line or a black line in the outline of the image. Further, in the conventional second contour correction device described below, since contour correction can be performed without adding a preshoot or overshoot, an adverse effect such as a white line or a black line bordering on a contour portion of an image. Can be avoided. However, since the level is limited by the maximum value and the minimum value around the target value in order to avoid the addition of preshoot or overshoot, the input signal and the output signal are compared as shown in FIG. 24 or FIG. There is a disadvantage that the geometrical structure of the signal contour may change.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a contour correction for improving the sharpness of a contour of an original video signal without adding a preshoot or an overshoot, and losing a geometric structure of the original video signal. It is an object of the present invention to provide a contour correction device free from defects.

[0015]

SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problems of the prior art, and the invention of claim 1 corrects a video signal in order to enhance the outline of the video. Recognizing means for recognizing a waveform pattern of a signal from a difference value between a signal to be corrected of a target sample of a video signal sampled at a predetermined sample interval and amplitude data of signals of samples before and after the contour correcting device. Calculating an amplitude data upper limit value from one of a signal to be corrected of a sample of interest and signals of samples before and after the signal based on a recognition result of the waveform recognition unit; An intermediate limit value generating unit that performs an operation of generating an amplitude data lower limit value from the other of the signals of the preceding and following samples; and An operation for generating an upper limit value of amplitude data and a lower limit value of amplitude data from a signal to be corrected and a signal of a sample having a smaller difference value between the amplitude data and a signal to be corrected of a target sample among signals of samples before and after the signal to be corrected is performed. A peak limit value generating unit, and an amplitude data upper limit value and an amplitude data lower limit value generated by the intermediate limit value generating unit or the peak limit value generating unit are selected based on the recognition result of the waveform recognition unit; An amplitude limiter for limiting the amplitude data value of the video signal based on the amplitude data upper limit value and the amplitude data lower limit value set.

According to a second aspect of the present invention, in the contour correcting apparatus according to the first aspect, the generation of the upper limit value of the amplitude data and the lower limit value of the amplitude data in the intermediate limit value generation means is performed by setting a signal to be corrected of a target sample. The amplitude value is M _N , the amplitude value of the sample with the larger amplitude value among the samples before and after the sample of interest is M _LRG , the amplitude value of the sample with the smaller amplitude value is M _SML , and the upper limit value of the amplitude data is M _MH. When the lower limit value of the amplitude data is M _ML , M _MH = M _N × A + M _LRG × (1-A) M _ML = M _N × B + M _SML × (1-B) (where A and B are It is characterized by comprising a comparing means, a selecting means, a multiplying means, and an adding means so that the calculation is performed by an operation of 0 ≦ A ≦ 1, 0 ≦ B ≦ 1).

According to a third aspect of the present invention, there is provided the contour according to the first aspect.
In the correction device, the vibration in the intermediate limit value generating means is
Focus on generation of upper limit value of width data and lower limit value of amplitude data
The amplitude value of the signal to be corrected for the sample to be corrected is M_NPay attention
Of the amplitude value of the signal of the sample before and after the sample
The amplitude value of the sample_LRG, The smaller of the amplitude values
M is the sample amplitude value._SML, The upper limit of the amplitude data_MH,
Set the lower limit of the amplitude data to M_{M L}, And M_MH= M_LRG−C (M_LRG−C> M_N) = M_N (M_LRG−C ≦ M_N) M_ML= M_SML+ D (M_SML+ D <M_N) = M_N (M_SML+ D ≧ M_N) (However, C and D are arbitrary constants)
Thus, the comparison means, the selection means, the addition means, and the subtraction means
It is characterized by having.

According to a fourth aspect of the present invention, in the contour correction apparatus according to any one of the first to third aspects, the generation of the amplitude data upper limit value and the amplitude data lower limit value by the peak limit value generating means is performed for a sample of interest. M _{N represents} the amplitude value of the signal to be corrected, M _{PNR represents} the amplitude value of the sample having a smaller difference value between the signal to be corrected and the amplitude data of the sample before and after the sample of interest, and M _PNR . the upper limit value M _PH, when the amplitude data lower limit value and M _PL, and, (when the _{(M N -M PNR) × E} ≦ F) M PH = M N + (M N -M PNR) × E = M _N + F (when (M _N −M _PNR ) × E> F) M _PL = M _N −G or M _PH = M _N + _GM P _L = M _N − (M _PNR −M _N ) × E ((M _PNR − _MN ) × E ≦ F) = _MN− F (when ( _MPNR − _MN ) × E> F) (Where E, F, and G are arbitrary constants), and are characterized by comprising a comparing unit, a selecting unit, a multiplying unit, an adding unit, and a subtracting unit.

According to a fifth aspect of the present invention, there is provided the contour correcting apparatus according to any one of the first to fourth aspects, further comprising a contour component amount detecting means for detecting a contour component amount per arbitrary unit time of the video signal, The intermediate limit value generating means includes an adaptive processing means for changing an arbitrary constant, A, B, C, D, based on the detection result of the contour component amount detecting means. An arbitrary constant based on the detection result of the contour component amount detecting means;
An adaptive processing means for changing E, F, and G is provided.

According to a sixth aspect of the present invention, in the contour correction device according to any one of the first to fifth aspects, the contour component amount detecting means detects a contour component amount per arbitrary unit time of the video signal. A contour part detecting means for detecting a contour part of the video signal; a contour component extracting means for extracting a specific frequency component of the contour part of the video signal based on a detection result of the contour part detecting means; A contour component accumulating means for accumulating the extraction result of the means for each arbitrary unit time, and a contour component per arbitrary unit time of the video signal is determined based on the accumulation result of the contour component accumulating means. It is characterized by comprising a contour component judging means.

According to a seventh aspect of the present invention, in the contour correction apparatus according to any one of the first to sixth aspects, before performing further contour correction, a discrete video signal having a sampling frequency f ₁ is used as an input signal, and First frequency converting means for up-sampling the sampling frequency to f ₂ , and after the contour correction is performed, the output signal of the contour correcting means, which is a discretized video signal of the sampling frequency f ₂ , is used as an input signal for sampling. it is characterized in further comprising a second frequency conversion means for downsampling the frequency f _1.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of a contour correction device according to the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a configuration diagram of a contour correction device according to a first embodiment of the present invention. In FIG. 1, 1 is an input terminal, 2 is an output terminal, 3 (1) to 3 (n + 1) are delay circuits, 4 is a correction component generation circuit, 5 is a gain adjustment circuit, 6 is a waveform recognition circuit, and 7 is an intermediate limit. A value generation circuit, 8 is a peak limit value generation circuit, 9 is an addition circuit, and 10 is an amplitude limit circuit.

The video signal S1 input from the input terminal 1
Is supplied to the correction component generation circuit 4 and the delay circuit 3 (1). The output signal S4 of the correction component generation circuit 4 is supplied to a gain adjustment circuit 5. Output signal S5 of gain adjustment circuit 5
Is supplied to one input terminal of the adder circuit 9. In the delay circuits 3 (1) to 3 (n + 1), (n + 1) delay circuits are connected in series, and a maximum of (n +
1) Data sample is delayed. Delay circuit 3 (n-
1), the output signal S3 (n) of the delay circuit 3 (n), and the output signal S of the delay circuit 3 (n + 1).
3 (n + 1) is supplied to the waveform recognition circuit 6, the intermediate limit value generation circuit 7, and the peak limit value generation circuit 8, respectively. Further, the output signal S3 (n) of the delay circuit 3 (n) is added to the addition circuit 9
Is supplied to the other input terminal. The output signal S6 of the waveform recognition circuit 6 is supplied to an intermediate limit value generation circuit 7, a peak limit value generation circuit 8, and an amplitude limit circuit 10, respectively.
The output signal S7 of the intermediate limit value generation circuit 7 and the output signal S8 of the peak limit value generation circuit 8 are supplied to the amplitude limit circuit 10. The output signal S9 of the adding circuit 9 is
, The signal is nonlinearly processed according to the output signal S6 of the waveform recognition circuit 6, the output signal S7 of the intermediate limit value generation circuit 7, and the output signal S8 of the peak limit value generation circuit 8, and output from the output terminal 2.

The configuration and operation of the first embodiment of the contour correcting apparatus according to the present invention will be described with reference to FIGS. In FIG. 1, it is assumed that a video signal having a contour as shown in FIG.

The input video signal S1 is supplied to the correction component generation circuit 4
Generates a contour correction component. The correction component generation circuit 4 can be constituted by, for example, a 7-tap symmetrical FIR filter as shown in FIG. In FIG. 2A, reference numerals 40 (1) to 40 (6) denote delay circuits, and 41 (0) to 41 (0).
41 (6) is a multiplication circuit, and 42 is an addition circuit. The input video signal S1 is delayed by the delay circuits 40 (1) to 40 (6). Input signal S1 and delay circuit 40 (1)-
The output signals S40 (1) to S40 (6) of 40 (6) are
Each of the multiplication circuits 41 (0) to 41 (6) in FIG.
After the coefficients K1 to K4 shown in FIG.
Are all added together. Here, K1 = 12/1
6, K2 = -3 / 16, K3 = -2 / 16, K4 = -1
/ 16, which is a high-pass filter characteristic as shown in FIG.

The correction component of the contour by the correction component generation circuit 4 becomes a signal as shown in FIG. by the way,
Here, the configuration of the correction component generation circuit 4 is a 7-tap symmetric FIR filter, but a 3-tap symmetric FIR filter as described in the first conventional example shown in FIG. 21 may be used. Although not shown, a symmetric type F having an arbitrary number of taps
An IR filter, an asymmetric FIR filter, or an IIR filter may be used. The characteristic may be a high-pass filter characteristic as shown in FIG. 2B or a band-pass filter characteristic for extracting a specific frequency component.

The gain of the output signal S4 of the correction component generation circuit 4 is appropriately controlled by the gain adjustment circuit 5.
Here, the gain is set to 2, and as a result, a signal as shown in FIG. The video signal S1 input from the input terminal 1 is delayed by the delay circuits 3 (1) to 3 (n + 1). At this time, the output signal S3 of the delay circuit 3 (n)
(N) shows the correction component generation circuit 4 and the gain adjustment circuit 5
Are delayed by n data samples corresponding to the delay amount n required for the signal processing of the delay circuits 3 (1) to 3 (n + 1).
Is a time-invariant characteristic and does not change its waveform-like characteristic, and is represented as the same waveform as the input signal as shown in FIG. Output signal S3 of delay circuit 3 (n)
(N) and the output signal S5 of the gain adjustment circuit 5 are added in the addition circuit 9 to obtain a signal as shown in FIG.

The waveform recognition circuit 6 includes a delay circuit 3 (n-1)
Output signal S3 (n-1), the output signal S3 (n) of the delay circuit 3 (n) and the output signal S3 of the delay circuit 3 (n + 1)
By inputting (n-1), the waveform pattern near the data sample of interest is recognized from the polarity of the difference value between the data sample of interest and the amplitude data of the data sample immediately before and after the data sample of interest. FIG. 3A shows the configuration of the waveform recognition circuit 6. In FIG. 3A, 60 and 61 are subtraction circuits, 62 and 63 are polarity detection circuits, and 64 is a pattern recognition circuit. FIG. 3B illustrates the polarity of the difference value between the data sample of interest and the amplitude data of the data sample immediately before and after the data sample of interest, and the recognition result of the waveform pattern near the data sample of interest. .

The operation of the waveform recognition circuit 6 is shown in FIGS.
This will be described with reference to FIG. The output signal S3 (n + 1) of the delay circuit 3 (n + 1) is subtracted from the output signal S3 (n) of the delay circuit 3 (n) by the subtraction circuit 60, and the output signal of the delay circuit 3 (n-1) is subtracted by the subtraction circuit 61. The output signal S3 (n) of the delay circuit 3 (n) is subtracted from the output signal S3 (n-1). Output signal S of subtraction circuit 60
At 60, the polarity detection circuit 62 detects the polarity,
0 is S60> 0, or S60 = 0, or S60 <
It is detected which state is 0.

Similarly, the output signal S61 of the subtraction circuit 61
In step S61, the polarity is detected by the polarity detection circuit 63.
Is S61> 0 or S61 = 0 or S61 <0
Is detected. The output signal S62 of the polarity detection circuit 62 and the output signal S of the polarity detection circuit 63
63 is supplied to a pattern recognition circuit 64. In the pattern recognition circuit 64, as shown in FIG. 3B, the waveform pattern near the data sample of interest, that is, the data of interest is determined from the polarity of the output signal S62 of the polarity detection circuit 62 and the polarity of the output signal S63 of the polarity detection circuit 63. It recognizes whether the sample is at a partial peak position of the waveform.

Here, for example, as shown in FIG. 3B, the polarities of S62 and S63 are S62> 0 and S63>
If 0, and if S62 <0 and S63 <0, it is recognized that the data sample of interest is located at the intermediate position (meaning that it is not at the peak position, represented by M in the figure), and S62 ≧ 0 When S63 ≦ 0, it is assumed that the data sample of interest is at the positive peak position (represented by + P in the figure), and the other data samples are S62 and S63.
With the polarity of, the data sample of interest is recognized as being at the negative peak position (represented by -P in the figure). As described above, the output signal S6 of the waveform recognition circuit 6 in which the waveform pattern near the data sample of interest has been recognized is shown in FIG.
A signal having a recognition result as shown in FIG.

The intermediate limit value generation circuit 7 includes a delay circuit 3 (n
-1), the output signal S3 (n) of the delay circuit 3 (n), the output signal S3 (n + 1) of the delay circuit 3 (n + 1), and the output signal S6 of the waveform recognition circuit 6. By inputting, Figure 11 of the data sample of interest
(E) The amplitude data upper limit value and the amplitude data lower limit value at point M are generated. FIG. 4 shows the configuration of the intermediate limit value generation circuit 7. In FIG. 4, reference numeral 70 denotes a comparison circuit;
Is a selection circuit, 73 and 74 are multiplication circuits, 75 is an addition circuit,
76 and 77 are multiplication circuits, and 78 is an addition circuit. FIG.
7 specifically shows the operation of the intermediate limit value generation circuit 7 with a waveform.

The operation of the intermediate limit value generating circuit 7 will be described with reference to FIGS. 4 to 5 and FIG. The intermediate limit value generation circuit 7 operates only at the point M in FIG. 11E based on the output signal S6 of the waveform recognition circuit 6. The output signal S3 of the delay circuit 3 (n + 1) is output from the comparison circuit 70.
(N + 1) and the output signal S3 (n) of the delay circuit 3 (n-1).
-1) The amplitude data values are compared. Based on the output signal S70 of the comparison circuit 70, the selection circuit 71
(N + 1) output signal S3 (n + 1) and the delay circuit 3 (n
-1) The output signal S3 (n-1) having the larger amplitude data value is output. On the other hand, the selection circuit 72
Based on the output signal S70 of 0, the output signal S3 (n + 1) of the delay circuit 3 (n + 1) and the output signal S3 (n-1) of the delay circuit 3 (n-1) having a smaller amplitude data value are output. .

In FIG. 5, as an example, S3 (n-1)> S
The waveform at the time of 3 (n + 1) is shown. S3 (n-
1) When <S3 (n + 1), the same operation is performed, and the description is omitted here. S3 (n-1)> S3 (n +
1), the output signal S7 of the selection circuit 71 is output at this time.
1 is the value of S3 (n-1), and the output signal S72 of the selection circuit 72 is the value of S3 (n + 1). The output signal S3 (n) of the delay circuit 3 (n) is multiplied by an arbitrary constant A by a multiplier 73, and the output signal S71 of the selector 71 is multiplied by an arbitrary constant 1-A by a multiplier 74. The output signal S7 of the multiplication circuit 73 is calculated by the addition circuit 75.
3 and the output signal S74 of the multiplying circuit 74 are added.

Output signal S3 (n) of delay circuit 3 (n)
Is also multiplied by an arbitrary constant B by a multiplication circuit 76,
The output signal S72 of the selection circuit 72 is
Multiplied by an arbitrary constant 1-B and multiplied by an adder circuit 78
The output signal S76 of the circuit 76 and the output signal S of the multiplication circuit 77
77 is added. This is as shown in FIG.
The amplitude data value is added to the output signal S3 (n) of the extension circuit 3 (n).
M_N, The amplitude data value of the output signal S71 of the selection circuit 71
M_LRG, The amplitude data value of the output signal S72 of the selection circuit 72
To M_SML, The amplitude data upper limit M_MHAnd amplitude
Data lower limit value is M_{M L}, M_MH= M_N× A + M_LRG× (1-A) M_ML= M_N× B + M_SML× (1-B) indicates that it is determined. Where A and B are 0 ≦
Any constant satisfying A ≦ 1, 0 ≦ B ≦ 1, and A =
B or A ≠ B. Addition calculated in this way
The output signal S7U of the circuit 75 is set to the amplitude data upper limit value,
Using the output signal S7L of the path 78 as the lower limit value of the amplitude data,
It is output from the interval limit value generation circuit 7. Intermediate limit value generation circuit
7 is an upper limit value as shown in FIG.
And a signal having a limited area surrounded by the lower limit.

FIG. 6 shows an example of a configuration different from that of the intermediate limit value generation circuit 7 shown in FIG. In FIG. 6, 7
0-2 is a comparison circuit, 71-2 and 72-2 are selection circuits, 7
3-2 is a subtraction circuit, 74-2 is an addition circuit, 75-2 is a comparison circuit, 76-2 is a selection circuit, 77-2 is a comparison circuit, 7
8-2 is a selection circuit. FIG. 7 specifically shows the operation of the intermediate limit value generation circuit 7 shown in FIG. 6 by a waveform, and the operation will be described with reference to FIGS. 6, 7, and 11.

The intermediate limit value generation circuit 7 includes a waveform recognition circuit 6
Operates only at the point M in FIG. 11E based on the output signal S6 of FIG. The delay circuit 3 is provided by the comparison circuit 70-2.
(N + 1) output signal S3 (n + 1) and the delay circuit 3 (n
-1) The amplitude data values of the output signal S3 (n-1) are compared. Based on the output signal S70-2 of the comparison circuit 70-2, the selection circuit 71-2 outputs the output signal S3 (n + 1) of the delay circuit 3 (n + 1) and the output signal S3 (n-) of the delay circuit 3 (n-1). The one having the larger amplitude data value among 1) is output. On the other hand, based on the output signal S70-2 of the comparison circuit 70-2, the selection circuit 72-2 outputs the output signal S3 (n + 1) of the delay circuit 3 (n + 1) and the output signal S3 (n) of the delay circuit 3 (n-1). -1) is output with the smaller amplitude data value. In FIG. 7, as an example, S3 (n-1)> S3 (n +
The waveform at the time of 1) is shown. S3 (n-1) <S3
In the case of (n + 1), the same operation is performed, and the description is omitted here.

Since S3 (n-1)> S3 (n + 1), the output signal S71-2 of the selection circuit 71-2 at this time.
Is the value of S3 (n-1), and the output signal S72-2 of the selection circuit 72-2 is the value of S3 (n + 1). The output signal S71-2 of the selection circuit 71-2 is reduced by an arbitrary constant C by a subtraction circuit 73-2.
5-2, the output signal S73-2 of the subtraction circuit 73-2
And the amplitude data value of the output signal S3 (n) of the delay circuit 3 (n) is compared with the output signal S75-2 of the comparison circuit 75-2.
, The selection circuit 76-2 outputs the output signal S73-2 of the subtraction circuit 73-2 and the output signal S3 of the delay circuit 3 (n).
The one with the larger amplitude data value among (n) is output.

Output signal S72-2 of selection circuit 72-2
, An arbitrary constant D is added by an adding circuit 74-2, and an output signal S74-2 of the adding circuit 74-2 and an output signal S3 of the delay circuit 3 (n) are added by a comparing circuit 77-2.
The amplitude data value of (n) is compared, and based on the output signal S77-2 of the comparison circuit 77-2, the selection circuit 78-2 selects the output signal S74-2 of the addition circuit 74-2 and the delay circuit 3
The output signal S3 (n) having the smaller amplitude data is output.

This is, as shown in FIG.
The amplitude data value of the output signal S3 (n) of (n) is M _N , the amplitude data value of the output signal S71-2 of the selection circuit 71-2 is M _LRG , and the amplitude of the output signal S72-2 of the selection circuit 72-2. When the data value is M _SML , the amplitude data upper limit value M _MH and the amplitude data lower limit value M _ML are defined as M _MH = _MLRG- C (when _MLRG- C> _MN ) = _MN ( _MLRG- C ≦ M _N ) M _ML = M _SML + D (when M _SML + D <M _N ) = M _N (when M _SML + D ≧ M _N ). Here, C and D are arbitrary constants, and C = D or C ≠ D. The intermediate limit value generation circuit 7 outputs the calculated output signal S7U of the selection circuit 76-2 as the amplitude data upper limit value and the output signal S7L of the selection circuit 78-2 as the amplitude data lower limit value. The output signal S7 of the intermediate limit value generation circuit 7 is
The signal has a restricted area surrounded by an upper limit and a lower limit as shown in FIG.

The peak limit value generating circuit 8 includes a delay circuit 3
(N-1) output signal S3 (n-1) and delay circuit 3
(N) output signal S3 (n), delay circuit 3 (n + 1) output signal S3 (n + 1), and waveform recognition circuit 6 output signal S
By inputting 6, the amplitude data upper limit value and the amplitude data lower limit value at the point P in FIG. 11E of the data sample of interest are generated. FIG. 8 shows the configuration of the peak limit value generation circuit 8. 8, reference numeral 80 denotes a comparison circuit;
Is a selection circuit, 82 is a subtraction circuit, 83 is a multiplication circuit, 84 is a comparison circuit, 85 and 86 are selection circuits, and 87 and 88 are addition circuits. FIGS. 9 and 10 specifically show the operation of the peak limit value generation circuit 8 by waveforms.

The operation of the peak limit value generation circuit 8 will be described with reference to FIGS. The peak limit value generation circuit 8 performs the operation shown in FIG. 1 on the basis of the output signal S6 of the waveform recognition circuit 6.
It operates only at the + P point or the -P point of 1 (E). The comparator 80 compares the amplitude data value of the output signal S3 (n + 1) of the delay circuit 3 (n + 1) with the amplitude data value of the output signal S3 (n-1) of the delay circuit 3 (n-1). The output signal S80 of the comparison circuit 80 and the output signal S6 of the waveform recognition circuit 6
At the point + P, the selection circuit 81 outputs the output signal S3 (n + 1) of the delay circuit 3 (n + 1) and the delay circuit 3
Of the output signal S3 (n-1) of (n-1), the one having the larger amplitude data value is output, and at point -P, the delay circuit 3
(N + 1) output signal S3 (n + 1) and the delay circuit 3 (n
-1) The output signal S3 (n-1) having the smaller amplitude data value is output.

In FIG. 9, as an example, S3 at + P point
It shows the waveform when (n-1)> S3 (n + 1). Since S3 (n-1)> S3 (n + 1), the output signal S81 of the selection circuit 81 at this time is S3 (n-1).
Value. Delay circuit 3 by subtraction circuit 82
The output signal S81 of the selection circuit 81 is subtracted from the output signal S3 (n) of (n), and the output signal S82 of the subtraction circuit 82 is subtracted.
Is multiplied by an arbitrary constant E by the multiplication circuit 83. The comparison circuit 84 compares the output signal S83 of the multiplication circuit 83 with the amplitude data value of an arbitrary constant F. Based on the output signal S84 of the comparison circuit 84, the selection circuit 85
The smaller of the output data S83 and the arbitrary constant F is output. At this time, the selection circuit 86 outputs an arbitrary constant -G. Output signal S of delay circuit 3 (n)
3 (n) and the output signal S85 of the selection circuit 85 are added by an addition circuit 87, and the output signal S3 (n) of the delay circuit 3 (n) and the output signal S86 of the selection circuit 86 are added by an addition circuit 88. You.

As another example, FIG. 10 shows a waveform at the point -P when S3 (n-1) <S3 (n + 1). Since S3 (n-1) <S3 (n + 1), the output signal S81 of the selection circuit 81 at this time is
(N-1). The output signal S81 of the selection circuit 81 is subtracted from the output signal S3 (n) of the delay circuit 3 (n) by the subtraction circuit 82.
82 is multiplied by an arbitrary constant E by a multiplying circuit 83. The output signal S8 of the multiplication circuit 83 is output by the comparison circuit 84.
3 is compared with the amplitude data value of an arbitrary constant -F, and based on the output signal S84 of the comparison circuit 84, the selection circuit 86 determines that the amplitude data value of the output signal S83 of the multiplication circuit 83 and the arbitrary constant -F is larger. Output. At this time, the selection circuit 8
5 outputs an arbitrary constant G. The output signal S3 (n) of the delay circuit 3 (n) and the output signal S85 of the selection circuit 85 are
The output signal S3 (n) of the delay circuit 3 (n) and the output signal S86 of the selection circuit 86 are added by the addition circuit 87.
Are added by an adder circuit 88.

This is, as shown in FIGS. 9 and 10,
Amplitude data value of output signal S3 (n) of delay circuit 3 (n)
To M_N, The amplitude data value of the output signal S81 of the selection circuit 81
To M_{P NR}, The amplitude data upper limit M_PHAnd amplitude
Data lower limit M_PL, M_PH= M_N+ (M_N-M_PNR) × E ((M_N-M_PNR) × E ≦ F) = M_N+ F ((M_N-M_PNR) × E> F) M_PL= M_N-G or M_PH= M_N+ GM_PL= M_N(M_PNR-M_N) × E ((M_PNR-M_N) × E ≦ F) = M_N−F ((M_PNR-M_N) × E> F). However, E, F, G,
Is an arbitrary constant.

The output signal S8U of the adder circuit 87 thus calculated is output from the peak limit value generating circuit 8 with the upper limit value of the amplitude data and the output signal S8L of the adder circuit 88 as the lower limit value of the amplitude data. The output signal S8 of the peak limit value generation circuit 8 is a signal having a limit area surrounded by the upper limit value and the lower limit value, but depending on the video signal, the upper limit value and the lower limit value as shown in FIG. It may be equal.

The output signal S9 of the adder 9 is output to the output signal S7 of the intermediate limit value generator 7 in the amplitude limiter 10.
The nonlinear processing is performed according to the output signal S8 of the peak limit value generation circuit 8. For example, at point M, FIG.
The magnitude of the output signal S9 of the adder 9 shown in FIG. 1 (H) is compared with the magnitude of the output signal S7 of the intermediate limit value generator 7, and the output signal S9 of the adder 9 is used to generate an intermediate limit value that is the upper limit of amplitude control. If the output signal S7U is larger than the output signal S7U of the circuit 7, the output signal S7U of the intermediate limit value generation circuit 7 is output.

The output signal S9 of the adder 9 is the output signal S7L of the intermediate limit value generator 7 which is the lower limit of the amplitude control.
If smaller, the output signal S of the intermediate limit value generation circuit 7
7L is output. Otherwise, the output signal S9 of the adding circuit 9 is output. On the other hand, at points + P and −P, the magnitudes of the output signal S9 of the adder 9 and the output signal S8 of the peak limit value generator 8 shown in FIG. Is larger than the output signal S8U of the peak limit value generation circuit 8 which is the upper limit value of the amplitude control, the output signal S8U of the peak limit value generation circuit 8 is output.

The output signal S9 of the adder 9 is the output signal S8 of the peak limit value generator 8 which is the lower limit of the amplitude control.
If it is smaller than L, the output signal S8L of the peak limit value generation circuit 8 is output. Otherwise, the output signal S9 of the adding circuit 9 is output. That is, the intermediate limit value generation circuit 7
Alternatively, the amplitude is limited using the upper limit value or the lower limit value generated by the peak limit value generation circuit 8. If you follow this,
As the output signal S2 of the amplitude limiting circuit 10, FIG.
A video signal having a sharp contour as shown in FIG.

As described above, according to the first embodiment of the present invention, the contour correction component is added by the upper limit value and the lower limit value generated by the waveform recognition means, the intermediate limit value generation means, and the peak limit value generation means. Since the amplitude control of the video signal is performed, the effect of the outline correction can be sufficiently obtained even in a gently contoured portion, and it can be realized without adding a preshoot or an overshoot even in a relatively steep contour portion.

When a signal which may lose the geometrical structure of the original video signal as shown in FIG. 12A is input to the contour correcting apparatus according to the first embodiment of the present invention, The output signal S4 of the correction component generation circuit 4 becomes a signal as shown in FIG. 12B, the output signal S5 of the gain adjustment circuit 5 becomes a signal as shown in FIG. The output signal S9 of the circuit 9 becomes a signal as shown in FIG. 12D, and the output signal S6 of the waveform recognition circuit 6 becomes the signal shown in FIG.
2 (E), the output signal S7 of the intermediate limit value generation circuit 7 becomes a signal as shown in FIG. 12 (F), and the output signal S8 of the peak limit value generation circuit 8 becomes
12 (G), and the signal as shown in FIG. 12 (H) is output by the amplitude limiting circuit 10 as shown in FIG. 12 (I). As a result, as can be seen from the output signal S3 (n) of the delay circuit 3 (n) and the output signal S2 of the contour corrector shown in FIG. 13, the contour can be corrected without losing the geometric structure.

Hereinafter, a second embodiment of the contour correction device of the present invention will be described with reference to the accompanying drawings. FIG.
FIG. 9 shows a configuration diagram of a contour correction device according to a second embodiment of the present invention. In FIG. 14, 1 is an input terminal,
2 is an output terminal, 3 (1) to 3 (n + 1) are delay circuits,
Is a correction component generation circuit, 5 is a gain adjustment circuit, 6 is a waveform recognition circuit, 7 is an intermediate limit value generation circuit, 8 is a peak limit value generation circuit, 9 is an addition circuit, 10 is an amplitude limit circuit, and 100 is a contour component amount. It is a detection circuit.

Input terminal 1, output terminal 2, delay circuit 3
(1) to 3 (n + 1), correction component generation circuit 4, gain adjustment circuit 5, waveform recognition circuit 6, intermediate limit value generation circuit 7, peak limit value generation circuit 8, adder circuit 9, amplitude limit circuit 10
The connection between them has already been described in the first embodiment of the contour correction device of the present invention, and therefore the description thereof is omitted. Contour component amount detection circuit 1
00, the video signal S1 input from the input terminal 1 is supplied, and the output signal S100 of the
Are supplied to the intermediate limit value generation circuit 7 and the peak limit value generation circuit 8, respectively.

The configuration and operation of the second embodiment of the contour correction device according to the present invention will be described with reference to FIGS. The delay circuits 3 (1) to 3 (n +
The operations of 1), the correction component generation circuit 4, the gain adjustment circuit 5, and the waveform recognition circuit 6 have already been described in detail in the first embodiment of the contour correction device according to the present invention, and thus will not be described here.

The contour component amount detection circuit 100 outputs the video signal S
By inputting 1, the contour component of the video signal is accumulated for each frequency, the sharpness of the contour portion of the video signal is obtained from the accumulation result, and the intermediate limit value generation circuit 7 connected to the subsequent stage
And the operation of the peak limit value generation circuit 8 is controlled. FIG. 15 shows the configuration of the contour component amount detection circuit 100. In FIG. 15, reference numeral 101 denotes a contour part detecting circuit, 102 and 103 denote contour component extracting circuits, 104 denotes a contour component accumulating circuit, and 105 denotes a contour component accumulating circuit.
Is a contour component determination circuit.

The operation of the contour component amount detection circuit 100 is shown in FIG.
This will be described with reference to FIG. The outline portion of the input video signal S1 is detected by the outline portion detection circuit 101. Output signal S10 of the contour part detection circuit 101
When the contour component extraction circuit 102 and the contour component extraction circuit 103 detect the contour portion by the contour portion detection circuit 101, the different specific frequency components of the input video signal S1 as shown in FIG. Is extracted. The contour component accumulating circuit 104 includes the contour component extracting circuit 10
The absolute value of the amplitude data value of the output signal S102 of the second and the output signal S103 of the contour component extraction circuit 103 is converted into an absolute value and is accumulated for each predetermined unit time.

The contour component judging circuit 105 judges the sharpness of the contour portion of the video signal S1 from the respective accumulation results of the contour component accumulating circuit 104. For example, the accumulation result AC of the contour component extraction circuit 102, which is a relatively low frequency component,
From accumulated result ACM ₁₀₃ of the contour component extracting circuit 103 is a frequency component of relatively high frequency and M _102, ACM ₁₀₃ / ACM
The ratio of ₁₀₂ is defined as sharpness. If the accumulation result ACM ₁₀₃ of the contour component extraction circuit 103, which is a relatively high frequency component, is large, the sharpness of the contour portion of the video signal S1 is high, and the value of ACM ₁₀₃ / ACM ₁₀₂ is also large at that time. .
The output signal S100 of the contour component determination circuit 105 calculated in this manner is defined as the sharpness of the contour portion of the video signal S1.
It is output from the contour component amount detection circuit 100.

The intermediate limit value generation circuit 7 includes a delay circuit 3 (n
-1) output signal S3 (n-1), output signal S3 (n) of delay circuit 3 (n), output signal S3 (n + 1) of delay circuit 3 (n + 1) and output signal S6 of waveform recognition circuit 6. By inputting the output signal S100 of the contour component amount detection circuit 100, the M of the data sample of interest shown in FIG.
An amplitude data upper limit value and an amplitude data lower limit value at a point are generated. FIG. 17 shows the configuration of the intermediate limit value generation circuit 7. 17, 70 is a comparison circuit, 71 and 72 are selection circuits, 73 and 74 are multiplication circuits, 75 is an addition circuit, 7
6, 77 are multiplication circuits, 78 is an addition circuit, and 79 is an adaptive processing circuit.

The operation of the intermediate limit value generation circuit 7 will be described with reference to FIG. The operation of the intermediate limit value generation circuit 7 excluding the adaptive processing circuit 79 has been described in detail in the first embodiment of the contour correction device of the present invention with reference to FIG. The adaptive processing circuit 79 outputs the output signal S of the contour component amount detection circuit 100.
Based on 100, the constants A and B described in FIG.

For example, when the value of the output signal S100 of the contour component amount detection circuit 100 is small, that is, when the sharpness of the video signal S1 is low, the values of the constants A and B are made smaller, the upper limit of the amplitude is increased, and the lower limit of the amplitude is increased. It operates to lower the value and further enhance the sharpness of the video signal S1. Conversely, the value of the output signal S100 of the contour component amount detection circuit 100 is large,
That is, when the sharpness of the video signal S1 is high, the constant A
And the value of the constant B is increased, the upper limit of the amplitude is increased, and the lower limit of the amplitude is increased, so that the sharpness of the video signal S1 is relatively suppressed and increased. Also, the contour component amount detection circuit 100
Conversion of the constant A and the constant B from the output signal S100 of
They have a linear or non-linear relationship.

Further, the intermediate limit value generating circuit 7 shown in FIG. 18 having a configuration different from that of the intermediate limit value generating circuit shown in FIG.
Similarly, the adaptive processing circuit 79-2 varies the constants C and D shown in FIG. 18 based on the output signal S100 of the contour component amount detection circuit 100. For example, when the value of the output signal S100 of the contour component amount detection circuit 100 is small, that is, when the sharpness of the video signal S1 is low, the values of the constants C and D are made small, and the amplitude upper limit value is raised and the amplitude lower limit value is lowered. Operate to further enhance the sharpness of the video signal S1. Conversely, when the value of the output signal S100 of the contour component amount detection circuit 100 is large, that is, when the sharpness of the video signal S1 is high, the values of the constants C and D are increased to increase the amplitude upper limit and increase the amplitude lower limit. , Video signal S1
It operates so as to increase the sharpness of the image relatively. Further, a constant C is obtained from the output signal S100 of the contour component amount detection circuit 100.
The conversion of the constant D is in a linear or non-linear relationship.

The peak limit value generating circuit 8 includes a delay circuit 3
(N-1) output signal S3 (n-1) and delay circuit 3
(N) output signal S3 (n), delay circuit 3 (n + 1) output signal S3 (n + 1), and waveform recognition circuit 6 output signal S
6 and the output signal S100 of the contour component amount detection circuit 100, the data sample of interest is shown in FIG.
An amplitude data upper limit value and an amplitude data lower limit value at the + P point and the −P point of (E) are generated. FIG. 19 shows the configuration of the peak limit value generation circuit 8. 19, reference numeral 80 denotes a comparison circuit, 81 denotes a selection circuit, 82 denotes a subtraction circuit, 83 denotes a multiplication circuit, 84 denotes a comparison circuit, 85 and 86 denote selection circuits, and 8 denotes a selection circuit.
7 and 88 are addition circuits, and 89 is an adaptive processing circuit.

The operation of the peak limit value generation circuit 8 will be described with reference to FIG. The operation of the peak limit value generation circuit 8 excluding the adaptive processing circuit 89 is the same as that of the first embodiment of the contour correction device of the present invention.
This embodiment has been described in detail with reference to FIG. The adaptive processing circuit 89 varies the constants E, F and G shown in FIG. 19 based on the output signal S100 of the contour component amount detection circuit 100.

For example, when the value of the output signal S100 of the contour component amount detection circuit 100 is small, that is, when the sharpness of the video signal S1 is low, the values of the constants E, F and G are increased, and the amplitude upper limit value is increased. Lower the lower limit of the amplitude,
It operates to further enhance the sharpness of the video signal S1. Conversely, when the value of the output signal S100 of the contour component amount detection circuit 100 is large, that is, when the sharpness of the video signal S1 is high, the values of the constants E, F, and G are made smaller,
The upper limit of the amplitude is increased and the lower limit of the amplitude is increased, so that the sharpness of the video signal S1 is relatively suppressed and increased. Further, the conversion of the constant E, the constant F and the constant G from the output signal S100 of the contour component amount detection circuit 100 has a linear or non-linear relationship.

As described above, according to the second embodiment of the present invention, the contour correction for increasing the sharpness is performed on the relatively gentle contour portion, so that the entire image is uniformly sharpened. You can make the image high.

Hereinafter, a third embodiment of the contour correction device of the present invention will be described with reference to the accompanying drawings. FIG.
FIG. 9 shows a configuration diagram of a contour correction device according to a third embodiment of the present invention. In FIG. 20, reference numeral 150 denotes a first frequency conversion circuit; 151, a contour correction device described in the first and second embodiments of the present invention;
Is a frequency conversion circuit.

Video signal S1 input from input terminal 1
Is supplied to the first frequency conversion circuit 150. The output signal S150 of the first frequency conversion circuit 150 is supplied to the contour correction device 151. The output signal S151 of the contour correction device 151 is supplied to the second frequency conversion circuit 152. Output signal S152 of second frequency conversion circuit 152
Is output from the output terminal 2.

The video signal S1 has, for example, a sampling frequency f ₁
It is assumed that the signal is sampled by. The first frequency conversion circuit 150 converts the video signal S1 into a sampling frequency f _1.
Upsampling to an integral multiple of the sampling frequency f ₂ of f ₁ from. The output signal S151 of the contour correction apparatus 151 subjected to contour correction in sampling frequency f _2, the second frequency converting circuit 1
In 52, downsampling the original sampling frequency f _1.

As described above, according to the third embodiment of the present invention, the sampling frequency is changed from f ₁ to f ₂ before the contour correction device.
After the up-sampling, the contour correction described in the first and second embodiments of the present invention is performed, and the sampling frequency is down-sampled from f ₂ to f ₁ in the subsequent stage.
Further, the load on the circuit connected to the subsequent stage is not increased, and the deterioration of the image quality due to the aliasing noise of the harmonic component generated by the nonlinear processing of the contour correction device can be reduced.

[0070]

As described above, the present invention is a contour correcting device for correcting a video signal to enhance the contour of a video,
A waveform recognition unit for recognizing a waveform pattern of a signal from a difference value between a signal to be corrected of a target sample of a video signal sampled at a predetermined sample interval and signals before and after the signal to be corrected; An operation of generating an amplitude data upper limit value from one of a signal to be corrected of a sample of interest and a signal of samples before and after the signal based on the recognition result, and the other of a signal to be corrected of the sample of interest and a signal of samples before and after the sample. An intermediate limit value generating means for performing an operation of generating the lower limit value of the amplitude data from the signal, and a signal to be corrected of the sample of interest and a signal of the sample of interest before and after the signal to be corrected based on the recognition result of the waveform recognition means. An amplitude data upper limit value and an amplitude data lower limit value are generated from a signal of a sample having a smaller difference value between the signal to be processed and the amplitude data. A peak limit value generating means for performing calculations,
The upper limit value and the lower limit value of the amplitude data generated by the intermediate limit value generator or the peak limit value generator are selected based on the recognition result of the waveform recognition unit, and the selected amplitude data upper limit and By providing the amplitude limiting means for limiting the amplitude data value of the video signal by the lower limit value of the amplitude data, the correction effect is changed between a relatively steep contour portion and a comparatively gentle contour portion, and a comparatively gentle contour portion is obtained. Performs contour correction to increase sharpness. Therefore, even an image in which a relatively steep outline portion and a comparatively gentle outline portion are mixed can be formed into an image with uniform sharpness, and a higher quality outline corrected image can be obtained.

Further, first frequency conversion means for up-sampling the sampling frequency to f ₂ using the discretized video signal of the sampling frequency f ₁ as an input signal, and an output signal of the first frequency conversion means as an input signal a contour correction means for, by providing the second frequency conversion means for downsampling the an input signal sampling frequency output signal of the contour correcting means is a discretization video signal sampling frequency f ₂ to f _1, more The contour correction amount can be varied with high precision, and the deterioration of the image quality due to the aliasing noise of the harmonic component generated by the nonlinear processing in the amplitude limiting means of the contour correction device can be alleviated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a contour correction device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a correction component generation circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration example of a waveform recognition and detection unit according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration example of an intermediate limit value generation unit according to the first exemplary embodiment of the present invention.

FIG. 5 is a waveform chart showing an operation example of the intermediate limit value generating means of the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a different configuration example of an intermediate limit value generation unit according to the first exemplary embodiment of the present invention.

FIG. 7 is a waveform chart showing an operation example of a different intermediate limit value generating means according to the first embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration example of a peak limit value generation unit according to the first embodiment of this invention.

FIG. 9 is a waveform chart showing an operation example of the peak limit value generating means according to the first embodiment of the present invention.

FIG. 10 is a waveform chart showing a different operation example of the peak limit value generating means of the first embodiment of the present invention.

FIG. 11 is a waveform chart showing an operation example of the first embodiment of the contour correction device according to the present invention.

FIG. 12 is a waveform chart showing a different operation example of the first embodiment of the contour correction device according to the present invention.

FIG. 13 is a waveform chart showing an operation example of the first embodiment of the contour correction device according to the present invention.

FIG. 14 is a block diagram showing a second embodiment of the contour correction device according to the present invention.

FIG. 15 is a block diagram illustrating a configuration example of a contour component amount detecting unit according to a second embodiment of the present invention.

FIG. 16 is a distribution diagram illustrating an operation example of a contour component amount detection unit according to the second embodiment of this invention.

FIG. 17 is a block diagram illustrating a configuration example of an intermediate limit value generation unit according to the second embodiment of this invention.

FIG. 18 is a block diagram showing a different configuration example of the intermediate limit value generating means according to the second embodiment of the present invention.

FIG. 19 is a block diagram illustrating a configuration example of a peak limit value generation unit according to the second embodiment of this invention.

FIG. 20 is a block diagram showing a third embodiment of the contour correction device according to the present invention.

FIG. 21 is a block diagram showing a first conventional contour correction device.

FIG. 22 is a waveform chart showing an operation example of the conventional first contour correction device.

FIG. 23 is a block diagram showing a second conventional contour correction device.

FIG. 24 is a waveform chart showing an operation example of the second conventional contour correction device.

FIG. 25 is a waveform chart showing an operation example of the second conventional contour correction device.

[Explanation of symbols]

1 input terminal, 2 output terminal, 3 (1) to 3 (n + 1)
... delay circuit, 4 ... correction component generation circuit, 5 ... gain adjustment circuit, 6 ... waveform recognition circuit, 7 ... intermediate limit value generation circuit, 8 ...
Peak limit value generation circuit, 9 addition circuit, 10 amplitude limit circuit, 40 (1) to 40 (6) delay circuit, 41 (0)
.. 41 (6), 73, 74, 76, 77, 83... Multiplication circuits, 42, 75, 78, 74-2, 87, 88... Addition circuits, 60, 61, 73-2, 82. , 6
3 ... polarity detection circuit, 64 ... pattern recognition circuit, 71, 7
2, 71-2, 72-2, 76-2, 78-2, 81,
85, 86 ... selection circuit, 70, 70-2, 75-2, 7
7-2, 80, 84... Comparison circuit, 79, 79-2, 89
... Adaptive processing circuit, 100 ... Contour component amount detection circuit, 101
... Contour part detecting circuit, 102, 103 ... contour component extracting circuit, 104 ... contour component accumulating circuit, 105 ... contour component judging circuit, 150 ... first frequency conversion circuit, 151 ... contour correcting device, 152 ... second Frequency conversion circuit, 200: correction component generation circuit, 201, 202 ... delay circuit, 203-2
05 multiplication circuit, 206 addition circuit, 207 gain adjustment circuit, 208 delay circuit, 209 addition circuit, 300
To 303: delay circuit, 304: maximum value detection circuit, 305
... Minimum value detection circuit, 306 ... Position detection circuit, 307 ... Calculation circuit, 308 ... Average value circuit, 309 ... Subtraction circuit, 31
0: gain adjustment circuit, 311: addition circuit, 312: non-linear processing circuit.

Continued on front page F term (reference) 5B057 CE03 CH08 5C021 PA17 PA32 PA35 PA42 PA52 PA56 PA66 PA67 RA02 SA21 XB02 XB11 XC01 YC10 5C077 NP02 PP10 RR18 5C082 AA02 BA41 CA81 CB01 DA51 MM10

Claims (7)

[Claims] 1. A contour correction device for correcting a video signal to enhance a contour of a video, wherein a signal to be corrected of a target sample of a video signal sampled at a predetermined sample interval and signals of samples before and after the target sample A waveform recognition means for recognizing a waveform pattern of a signal from a difference value of the amplitude data, and an upper limit of the amplitude data from one of a signal to be corrected of a target sample and signals of samples before and after the signal based on a recognition result of the waveform recognition means. A calculation for generating a value, an intermediate limit value generation unit for performing an operation for generating an amplitude data lower limit value from the other of the signal to be corrected of the target sample and the signals of the samples before and after the correction, and a recognition result of the waveform recognition unit. Based on the signal to be corrected of the sample of interest and the signals of the samples before and after the signal to be corrected, the signal to be corrected of the sample of interest and the amplitude data Peak limit value generating means for performing an operation of generating an amplitude data upper limit value and an amplitude data lower limit value from a signal of a sample having a smaller difference value; and an amplitude generated by the intermediate limit value generating means or the peak limit value generating means. Amplitude limiting means for selecting a data upper limit value and an amplitude data lower limit value based on the recognition result of the waveform recognition means, and limiting the amplitude data value of the video signal by the selected amplitude data upper limit value and amplitude data lower limit value. A contour correction device comprising: 2. The contour correction device according to claim 1, wherein the generation of the upper limit value of the amplitude data and the lower limit value of the amplitude data in the intermediate limit value generation means is performed by setting the amplitude value of the signal to be corrected of the target sample to M _N. M _{LRG is} the amplitude value of the sample with the larger amplitude value of the sample before and after the sample of interest, M _{SML is} the amplitude value of the sample with the smaller amplitude value, M _{MH is} the upper limit value of the amplitude data, and the lower limit value of the amplitude data is M _LRG . when the M _{ML, and, M MH = M N × a} + M LRG × (1-a) M ML = M N × B + M SML × (1-B) ( provided that, a, B, is, 0 ≦ a ≦ 1 , An arbitrary constant of 0 ≦ B ≦ 1), comprising: a comparing unit, a selecting unit, a multiplying unit, and an adding unit. 3. The contour correction device according to claim 1, wherein the generation of the upper limit value of the amplitude data and the lower limit value of the amplitude data in the intermediate limit value generation means is performed by setting the amplitude value of the signal to be corrected of the target sample to M _{N. MLRG is} the amplitude value of the sample with the larger amplitude value among the signals of the samples before and after the sample of interest, M _{SML is} the amplitude value of the sample with the smaller amplitude value, and M is the upper limit value of the amplitude data.
_MH , and the lower limit of the amplitude data is M _ML , where M _MH = M _LRG -C (when M _LRG -C> M _N ) = M _N (when M _LRG -C ≦ M _N ) M _ML = M _SML + D (when M _SML + D <M _N ) = M _N (when M _SML + D ≧ M _N ) (where C, D are arbitrary constants) A contour correction device comprising: an addition unit; and a subtraction unit. 4. The contour correction device according to claim 1, wherein the generation of the upper limit value of the amplitude data and the lower limit value of the amplitude data in the peak limit value generation means is performed on a signal to be corrected of a sample of interest. The amplitude value is M _N , the amplitude value of the sample having a smaller difference value between the signal to be corrected of the target sample and the amplitude data among the signals of the samples before and after the target sample is M _PNR , and the upper limit of the amplitude data is M
Assuming that _{PH is} the lower limit value of the amplitude data and M _PL is, M _PH = M _N + (M _N −M _PNR ) × E (when (M _N −M _PNR ) × E ≦ F) = M _N + F (( M _N -M _PNR) × E> when F) M _PL = M _N -G _{or, M PH = M N + G} M PL = M N - (M PNR -M N) × E ((M PNR -M N ) × E ≦ F) = M _N− F ((M _PNR −M _N ) × E> F) (where E, F, and G are arbitrary constants). A contour correction device comprising: means, selecting means, multiplying means, adding means, and subtracting means. 5. The contour correction device according to claim 1, further comprising a contour component amount detecting means for detecting a contour component amount per arbitrary unit time of the video signal, wherein the intermediate limit value generation is performed. In the means, an arbitrary constant, A, B, C,
An adaptive processing means for varying D, wherein the peak limit value generating means has an arbitrary constant, E, F,
A contour correction device comprising adaptive processing means for changing G. 6. The contour correction device according to claim 1, wherein the contour component amount detecting means detects a contour component amount per an arbitrary unit time of the video signal. A contour part detecting means for detecting a contour part; a contour component extracting means for extracting a specific frequency component of a contour part of a video signal based on a detection result of the contour part detecting means; and an extraction result of the contour component extracting means. Contour component accumulating means for accumulating for every arbitrary unit time, and contour component judging means for judging a contour component per arbitrary unit time of the video signal based on the accumulation result of the contour component accumulating means. A contour correction device comprising: 7. The contour correction device according to claim _{1, wherein} a discretized video signal having a sampling frequency f ₁ is used as an input signal and the sampling frequency is set to f ₂ before performing further contour correction. in comprising a first frequency converting means for up-sampling, to the subsequent stage of performing outline correction, the an input signal sampling frequency output signal of the contour correcting means is a discretization video signal sampling frequency f ₂ to f ₁ An outline correction device comprising a second frequency conversion means for downsampling.