JP2000323949A - Signal input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate a voltage drop generated by the emitter series resistance and the signal current of an input transistor. SOLUTION: The signal input circuit 21 of a wide dynamic range with current input compresses the signal current Is of large current from a signal current source S1 of a photodiode with the logarithmic characteristic of an input transistor Q and it is converted into a voltage. Then, it is extended in the current conversion circuit of a post stage and it is converted into current so as to be outputted. An input transistor Q is constituted of a differential couple which has a common emitter to which signal current Is given and is formed of Q1 and Q2 of the same characteristics where bases are set to be same potentials. An error detection circuit 22 supplies collector current to Q1 and Q2 by Q3 and Q4 of an area ratio which is previously decided, has the common emitter to which constant current is given, generates correction current corresponding to the collector voltage difference of Q1 and Q2 by the differential couple of Q5 and Q6 of the area ratio opposite to that of Q3 and Q4 and corrects the output from a current conversion circuit 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wide current input, by compressing a signal current by a logarithmic characteristic of an input transistor, converting the signal current into a voltage, expanding the signal current in a subsequent transistor, converting the signal into a current, and outputting the current. The present invention relates to a signal input circuit that realizes a dynamic range.

[0002]

2. Description of the Related Art When an input current becomes several hundreds of microamperes, such as when a wide range of input current is handled, or when it is necessary to increase the input current for realizing high frequency operation, the logarithmic compression characteristic of a transistor is obtained. An input circuit using the above is conventionally used. FIG. 6 shows the configuration.

FIG. 6 is an electric circuit diagram of a differential circuit 1 which is a typical prior art signal input circuit. This differential circuit 1
Are input transistors q1 and q2
Are connected to a power source b having a constant voltage vb, and the emitters are connected to input terminals pi1 and pi2, respectively, so that the input currents of the input transistors q1 and q2
The data is compressed by the logarithmic characteristic of 2 and converted into an emitter voltage, and the emitter voltage is applied to the bases of the transistors q3 and q4 which form a differential pair, with the emitter being commonly connected to the constant current source f and forming a differential pair. An extended current conversion output is derived from the collectors of the transistors q3 and q4 to the output terminals po1 and po2. The input terminals pi1 and pi2 are connected to a photoelectric conversion element such as a photodiode used in an AF system of a camera, for example.

However, this conventional technique has a problem that the voltage drop due to the emitter series resistance, which is a parasitic element unique to the input transistors q1 and q2, increases, and the output current linearity deviates from the input current. Another conventional technique that takes into account the reduction of this effect is disclosed in Japanese Patent Application Laid-Open No. 8-340229. FIG. 7 shows the configuration.

FIG. 7 is an electric circuit diagram of a differential circuit 11 which is another conventional signal input circuit. This differential circuit 11
In the figure, portions corresponding to the above-described differential circuit 1 are denoted by the same reference numerals. The emitter series resistor is:
These are indicated by reference signs q1r and q2r. Although the emitter series resistance also exists in the emitters of the transistors q3 and q4, the bias current i of the differential circuit formed by the transistors q3 and q4 is a current set inside the integrated circuit and is usually several μA. And the resulting voltage drop is very small and has little effect.

In the differential circuit 11, the bases of the input transistors q1 and q2 are connected to their respective collectors, and the collectors are connected to the power supply b via resistors r2 and r1. Also, two transistors q3, q4
Share an emitter, and a current i flowing through the differential circuit 11 from the emitter is set by a constant current source f. The operation of this circuit is as follows. Input transistors q1, q2 and transistors q3, q4
Are matched transistors. The emitter current of each transistor q1, q2;
1, i2; i3, i4 and the base-emitter forward voltage drop are respectively vbe1, vbe2; vbe3, vbe
4, the voltage v3. Applied to the bases of the transistors q3 and q4. v4 is as follows: v3 = vb-i2 · r2-vbe1-i1 · q1r (1) v4 = vb-i1 · r1-vbe2-i2 · q2r (2) As described above, since the transistors q1 and q2 are matched transistors, q1r = q2r = q
Assuming that r1 and r1 = r2 = r, from the above equations (1) and (2), the base voltage difference between the transistors q3 and q4, that is, the base-emitter forward voltage drop difference Δvbe is: Δvbe = vbe3−vbe4 = v3 -V4 = (i1-i2) r- (i1-i2) qr + (vbe2-vbe1) = (i1-i2) (r-qr) + (KT / q) Ln (i2 / i1) = (KT / q) Ln (i3 / i4) (3) q: electric charge [C] T: absolute temperature [K] K: Boltzmann constant [J / K], and (i1-i2) r in the above equation is the emitter series resistance q1r, The error is caused by q2r.

Here, assuming that r = qr, Equation 3 is given by (KT / q) Ln (i3 / i4) = (KT / q) Ln (i2 / i1) (4) Therefore, i2 / i1 = i3 / I4 (5), and the resistances r1 and r2 are replaced by the emitter series resistance q1
It is understood that the effects of the emitter series resistances q1r and q2r can be reduced by making them equal to r and q2r.

[0008]

In the prior art differential circuit 11 configured as described above, in order to reduce the influence of the emitter series resistors q1r and q2r on the circuit configuration,
The resistors r1 and r2 having the same value must be prepared, and the resistors r1 and r2 must be of the same type as the emitter series resistors q1r and q2r in consideration of temperature characteristics and fluctuation. However, a base resistance and an emitter resistance generally used in an integrated circuit cannot be said to be the same as the emitter series resistances q1r and q2r. If the resistance of the emitter series resistance q
If the value is twice or more of 1r and q2r, there is a problem that an error becomes larger than before correction.

An object of the present invention is to provide a signal input circuit capable of compensating a voltage drop due to an emitter series resistor with high accuracy and obtaining an output signal having high linearity with respect to an input signal.

[0010]

According to a first aspect of the present invention, a signal input circuit compresses a signal current using a logarithmic characteristic of an input transistor and converts the signal current into a voltage, and then expands and converts the signal current into a current using a subsequent transistor. A current input and wide dynamic range signal input circuit, wherein the input transistor has a common emitter to which the signal current is applied, and first and second signals having the same characteristics with the same potential at the base. And a third transistor and a fourth transistor formed in a predetermined area ratio by supplying emitter currents from the power supply to the collectors of the first and second transistors, respectively. A fifth emitter having a common emitter to which a current is applied and having an area ratio opposite to that of the third and fourth transistors.
And an error detection circuit configured to generate a correction current corresponding to a difference between the collector voltages of the first and second transistors, and a current converter for converting an output voltage of the input transistor into a current. A current conversion circuit that outputs a voltage drop caused by an emitter series resistance of the input transistor and a signal current as a difference between collector voltages of the first and second transistors, and corresponds to a difference between the collector voltages of the first and second transistors. Then, the voltage drop is compensated by correcting the output current of the current conversion circuit based on the correction current output from the error detection circuit.

According to the above configuration, the voltage drop caused by the emitter series resistance and the signal current of the input transistor is reduced by the first transistor as described above.
And a second transistor, and the error detection circuit uses third and fourth transistors having a ratio in transistor size, thereby forming a differential pair.
And the collector voltage of the second transistor. Here, the error detection circuit is configured, for example, as set forth in claim 2, wherein the bias current is sufficiently smaller than the signal current, and the emitter series resistance generated by the fifth and sixth transistors and the like is provided. Is sufficiently smaller than the signal current, and hardly causes any problem.

Therefore, a voltage drop due to the emitter series resistance of the input transistor can be detected and compensated without using a passive element such as a resistor, for example, by a specific configuration as described in claim 2. As a result, the detected error voltage is less likely to be affected by variations in resistance and the like and temperature shift, and can generate a small current accurate output signal proportional to a large current input signal.

Further, the signal input circuit according to the present invention further comprises a buffer driven by a signal voltage obtained from the input transistor, and a bias current source for driving the buffer at a constant current. The circuit includes a first constant current source for supplying the constant current to the emitters of the fifth and sixth transistors, and a seventh and a fourth source for supplying the collector currents of the fifth and sixth transistors from the power source, respectively. An eighth transistor, ninth and tenth transistors forming a current mirror circuit with the seventh and eighth transistors, respectively, and extracting currents flowing through the seventh and eighth transistors, and the ninth transistor Further comprising eleventh and twelfth transistors forming a current mirror circuit which folds a current flowing through The bias current is increased or decreased by generating the correction current by a push-pull operation of ninth and twelfth transistors, and the current conversion circuit includes a thirteenth transistor driven by an output voltage of the buffer, A fourteenth transistor having a common emitter with the transistor to form a differential pair; and a second transistor for supplying an emitter current of the thirteenth and fourteenth transistors.
And a reference voltage source that holds the base of the fourteenth transistor at a predetermined reference voltage, and derives an output current from the collectors of the thirteenth and fourteenth transistors.

Furthermore, a signal input circuit according to a third aspect of the present invention includes two of the first to twelfth transistors, a buffer, a bias current source and a first constant current source. The output voltage of one buffer is applied to the base of a thirteenth transistor, and the output voltage of the other buffer is applied to the base of a fourteenth transistor in place of the reference voltage. The output voltage is proportional to the difference between the two signal currents. It is characterized in that two output currents having a difference between each other are derived.

According to the above configuration, one circuit can cope with a differential input such as a light receiving element of an optical pickup.

According to a fourth aspect of the present invention, in the signal input circuit, the signal current source is a photoelectric conversion element.

According to the above configuration, in the photoelectric conversion device such as the photodiode used as the light receiving element of the optical pickup according to the third aspect, the dynamic range of the signal current is large. Can be implemented.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 3.

FIG. 1 is an electric circuit diagram of a signal input circuit 21 according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a functional configuration of the signal input circuit 21. The signal input circuit 21 generally includes an input transistor Q for logarithmically compressing a signal current Is from a signal current source S1 realized by a photodiode or the like of an optical pickup to a signal voltage Vs, and a voltage drop due to its emitter series resistance. An error detection circuit 22 for detecting VE, and the input transistor Q
And an error correction circuit 23 for subtracting the voltage drop VE detected by the error detection circuit 22 from the signal voltage Vs including the voltage drop VE to correct the signal voltage Vs, and outputting the corrected signal voltage Vs to the output signals Io1 and Io2. And a current conversion circuit 24 that converts the current into a current.

The input transistor Q has a common emitter to which the signal current Is is applied, has a base set to the same potential as the reference voltage VREF1 by the reference voltage BI, and has the same characteristics as n: n (FIG. 1). In this case, the first and second transistors Q1 and Q2 formed at an area ratio of n = 2)
It consists of two differential pairs.

The error detection circuit 22 is diode-connected, supplies a collector current from the power supply of the voltage Vcc to each of the first and second transistors Q1 and Q2, and is formed to have an area ratio of 1: n. The third and fourth transistors Q3 and Q4 have a common emitter, and are formed to have an area ratio n: 1 opposite to the area ratio of the third and fourth transistors Q3 and Q4. Fifth and sixth transistors Q5 and Q6 to which the collector voltage of each of the transistors Q1 and Q2 is applied to the base, respectively.
And a first constant current source F1 for supplying a constant current It1 to the emitters of the fifth and sixth transistors Q5 and Q6. The first constant current source F1 is diode-connected, and is connected to the fifth and sixth transistors from the power supply. Seventh and eighth transistors Q7 and Q8 for supplying the collector currents of the transistors Q5 and Q6, respectively, and the seventh and eighth transistors Q7 and Q8.
Ninth and tenth transistors Q9, Q1 which form current mirror circuits with the transistors Q7, Q8, respectively, and extract the current flowing through the seventh and eighth transistors Q7, Q8.
0, and eleventh and twelfth transistors Q11 and Q12 forming a current mirror circuit that folds the current flowing through the ninth transistor Q9. The ninth and twelfth transistors Q9 and Q12 The correction current IH is created by the push-pull operation.

The error correction circuit 23 includes first and second transistors Q, which are output voltages of an input transistor Q.
And a buffer Q30 to which a signal voltage Vs including an emitter voltage drop VE of Q1 and Q2 is applied, and a bias current source F for supplying a constant bias current It2 to the buffer Q30.
The emitter voltage of the buffer Q30 changes according to the increase or decrease of the correction current IH, and the signal voltage Vs compensated for the voltage drop VE is output to the current conversion circuit 24.

The current conversion circuit 24 includes the buffer Q
A thirteenth transistor Q13 having an emitter voltage of 30 applied to its base; a fourteenth transistor Q14 having a common emitter with the thirteenth transistor Q13 to form a differential pair; A second constant current source F3 for supplying the emitter current It3 of the transistors Q13 and Q14, and a reference voltage source B2 for holding the base of the fourteenth transistor at a predetermined reference voltage VREF2. Output currents Io1 and Io2 are derived from the collectors of the thirteenth and fourteenth transistors Q13 and Q14 to output terminals PO1 and PO2.

Hereinafter, the operation of the signal input circuit 21 configured as described above will be described in detail.

As described above, the transistors Q1 and Q2 share a base and are transistors having the same transistor size. Therefore, if the currents flowing through the respective collectors are I1 and I2, the following equations hold.

I1 = I2 = Is / 2 (6) Also, according to Equation 6, the current of Is / 2 also flows through the diode-connected transistors Q3 and Q4 equally through the respective transistors. However, since the transistor size of transistor Q3 is 1 / n of the transistor size of transistor Q4, the base-emitter forward voltage drop Vbe3, Vbe4 of transistors Q3, Q4
Vbe3 = (kT / q) · Ln (Is / 2IO) (7) Vbe4 = (kT / q) · Ln (Is / 2nIO) (8) IO: reverse saturation current of the transistor.

Here, assuming that the resistance value of the emitter series resistor Q3R of the transistor Q3 is r, it depends on the transistor size. Therefore, in the emitter series resistors Q1R, Q2R and Q4R of the transistors Q1, Q2 and Q4, r
/ N.

Therefore, from the equations (7) and (8), the base voltages VB5, VB6 and VB of the transistors Q5, Q6 and Q30 are obtained.
30 is represented by the following equation.

VB5 = Vcc−Vbe3- (Is · r) / n = Vcc− (kT / q) · Ln (Is / 210) − (Is · r] / n (9) VB6 = Vcc−Vbe4- ( Is · r) / 2n = Vcc− (kT / q) · Ln (Is / 2nIO) − (Is · r) / 2n (10) VB30 = VREF1-Vbe1- (Is · r) / n = VREF1- ( kT / q) · Ln (Is / 2nIO) − (Is · r) / 2n (11) From Expressions 9 and 10, VB5−VB6 = − (kT / q) · Ln (1 / n) − ｛ (Is · r) · (n−1)｝ / 2n (12)

On the other hand, transistors Q5, Q6,
Although the voltage drop due to the emitter series resistance occurs also in the emitter of Q30, Is≫It1 = It2
/ 2, the effect is very small, and the emitter series resistance of the transistors Q5, Q6, Q30 can be relatively neglected.

Since the transistor sizes of the transistors Q6 and Q5 are 1: n, if the currents flowing through the respective collectors are I6 and I5, the following equation is established from the above equation (12).

I5 + I6 = It1 (13) I5 / I6 = ne ^{(q / KT) (Vbe5-Vbe6)} = ne ^{(q / KT) (VB5-VB6) 6} = e ^{-[(qrIs (n-1)) / 2nKT]} = e− ^B (14) ∵B = (qrIs · (n−1)) / 2nKT Therefore, the collector current I10 of the transistor Q10
And a correction current IH expressed by a current difference between the collector current I12 of the transistor Q12 and IH = I10-I12 = I6-I5 = {(1-e- ^B ) / (1 + e- ^B )}. It1 = {(1 −A) / (1 + A)｝ · It1 (15) where A = ^−B . When this correction current IH does not flow at all,
The constant current It2 flows through the emitter of the transistor Q30, and the forward voltage drop Vb between the base and the emitter at that time.
e30 is as follows: Vbe30 = (kT / q) · Ln (It2 / IO) = (kT / q) · Ln (It1 / 2IO) (16) When the correction current IH is flowing, the constant current It
2 flows in a direction to supplement the current of the transistor Q30.
The current of (It2-IH) flows through the emitter. At this time, the forward voltage drop Vbe30 ′ between the base and the emitter of the transistor Q30 is expressed by the following expression from Expressions 15 and 16.

Vbe30 ′ = (kT / q) · Ln {(It1 / 2−IH) / IO} (17) Accordingly, the correction voltage VH is expressed by the following equation.

VH = Vbe30−Vbe30 ′ = (kT / q) · Ln {(It1 / 2) / (It1 / 2−IH)} = − (kT / q) · Ln ｛(3A-1) / (A + 1) )｝ = − (KT / q) · Ln ｛(3e− ^B− 1) / (e− ^B + 1)｝ (18) Since 1≫B, the following approximate expressions 19 and 20 hold.

E ^-B {1-B (19) Ln (1-B)}-B (20) By substituting the approximate expressions of Expressions 19 and 20 into Expression 18, the following expression is obtained. (N−1)｝ / 2n (21), and the voltage drop caused by the emitter series resistance of the logarithmic compression transistor Q1 and the signal current, that is, the error voltage VE is obtained from the equation 11, as VE = − (Is · r) / 2n (22) Therefore, when n = 2, it is understood that the error voltage VE and the correction voltage VH are substantially equal, and the voltage drop of the error is corrected.

FIG. 3 and Table 1 show the simulation results of the present inventor.
2, the error voltage and the correction voltage with respect to the input current are calculated. n = 2, It1 = 6μ
A, It2 = 3 μA, (KT / q) = 26 mV, r = 5
Ω is changed in the range of Is = 1 μA to 1 mA. As shown in Table 1, although the polarity of the error voltage and that of the correction voltage are naturally reversed, they are plotted with the same polarity in FIG.

[0037]

[Table 1]

As can be seen from the above results, the error caused when the signal current is logarithmically compressed and converted into a voltage can be substantially corrected before expanding again and converting it into a current regardless of the magnitude of the signal current. It is understood that there is.

In this manner, the voltage drop due to the emitter series resistors Q1R and Q2R of the input transistor Q can be detected and compensated for without using a passive element such as a resistor. This makes it possible to generate accurate small-current output signals Io1 and Io2 in proportion to the large-current input signal Is.

Another embodiment of the present invention will be described below with reference to FIGS. 4 and 5.

FIG. 4 is an electric circuit diagram of a signal input circuit 31 according to another embodiment of the present invention. This signal input circuit 31
Is configured using approximately two sets of the above-described signal input circuits 21. The first set of configurations is provided with the same reference numerals as those of the above-described signal input circuit 21, and the second set of configurations is denoted by the same reference numerals. Have the same reference numerals with the addition of a suffix a. However, the current conversion circuit 24 is shared, and the emitter voltage of the buffer Q30 on the signal input circuit 21 side is equal to that of the thirteenth transistor Q13.
The base of the fourteenth transistor Q14 is supplied with the emitter voltage of the buffer Q30a on the signal input circuit 21a side, instead of the reference voltage source B2.

When the above equation 11 is applied to this circuit, the base voltages VB30, VB30 of the buffers Q30, Q30a
a is VB30 = VREF1− (kT / q) · Ln (Is / 2nIO) − (Is · r) / 2n (11) VB30a = VREF1− (kT / q) aLn (Isa / 2nIO) − (Isa · r) / 2n (23) Therefore, the base voltage difference _ΔVB30-30a between the buffers Q30 and Q30a is _ΔVB30-30a = VB30−VB30a = − (KT / q) · Ln (Is / Isa) − (r / 2n) · (Is− Isa) (24) The correction voltages VH and VHa at this time are expressed as follows from Expression 18.

[0043] VH = - (kT / q) · Ln {(3e -B1 -1) / (e -B1 +1)} ... (25) VHa = - (kT / q) · Ln {(3e -B2 -1 ^{) / (e -B2 +1)}} ... (26) ∵B1 = {qrIs · (n-1)} / 2nKT B2 = {qrIsa · (n-1)} / 2nKT compensation voltage difference △ VH is, △ VH = VH-VHa = (KT / q ) × Ln ^{[{(3e -B2 -1) · (} e -B1 +1)} / {(e -B2 +1) · (3e -B1 -1)} ] ... (27) When the above equation is approximated similarly to the above equation 21, the correction voltage difference ΔVH is as follows.

ΔVH ≒ (r / 2n) · (Isa−Is) · (n−1) (28) The base voltage difference ΔVB _13-14 between the transistors Q13 and Q14 of the differential circuit for expansion is given by the following equation (24). 27, it is expressed by the following equation.

ΔVB _13-14 = ΔVB _30-30a + _ΔVH ≒ − (KT / q) · Ln (Is / Isa) − (r / 2n) · (Is−Isa) + (r / 2n) · (Isa−) Is) · (n−1) (29) If n = 2, then ΔVB _13-14 ≒ − (KT / q) · Ln (Is / Isa) (30) Current ratio I13 / I14 flowing through the collectors of transistors Q13 and Q14
I13 / I14 = (Isa / Is) ・ e− ^{(r / 2n) (Is−Isa)} (31) When the correction is applied, the output current ratio (I13 / I13 / I14 / (I14) ′ becomes (I13 / I14) ′ ≒ (Isa / Is) (32) Here, Expression 31 is an input current ratio (Isa / Is).
On the other hand, it shows that the error due to the emitter series resistance appears in the output current ratio. On the other hand, by performing the correction, the deviation due to this error is corrected and the output current ratio (I13 / I1
4) 'indicates an ideal characteristic determined only by the input current ratio (Isa / Is).

FIG. 5 and Table 2 show the simulation results of the present inventor.
The output current and its error are calculated using 1, 32,
It shows an ideal output current ratio, an actual output current ratio, and a deviation from the ideal value. As in the case of FIG. 3 and Table 1, n = 2, It1 = 6 μA, It2 = 3 μ
A, (KT / q) = 26 mV, r = 5Ω, and Is =
It is changed in the range of 1 μA to 1 mA. The ideal value shown on the graph and the ideal output current ratio in the table below are reciprocals of the input current ratio.

[0047]

[Table 2]

From the above results, the signal current is logarithmically compressed,
When converting to a voltage, an error voltage is generated due to the effect of the emitter series resistance, which causes the output current ratio to deviate from the input current ratio after expansion.However, by performing correction, the effect of the emitter series resistance is reduced. In addition, the deviation of the output current ratio from the input current ratio can be suppressed. In this manner, one circuit can cope with differential inputs such as light receiving elements of an optical pickup.

[0049]

According to the first aspect of the present invention, a signal input circuit comprises:
The voltage drop caused by the emitter series resistance of the input transistor and the signal current is reduced by the first transistor and the second transistor having the same characteristics with the input transistor having a common emitter to which the signal current is applied and having the same potential at the base. By using a third pair and a fourth transistor which are configured by a differential pair and have a ratio in transistor size for the error detection circuit, the difference is obtained as a difference between the collector voltages of the first and second transistors, The difference between the collector voltages is formed in the error detection circuit having the area ratio opposite to the area ratio of the third and fourth transistors in the error detection circuit configured as described in claim 2, and the bias current is reduced. Fifth and sixth signals sufficiently smaller than the signal current
The voltage drop is compensated by forming a correction current by a differential pair composed of the transistors described above, and correcting the output current of the current conversion circuit based on the correction current, for example, as described in claim 2. .

Therefore, the voltage drop due to the emitter series resistance of the input transistor can be detected and compensated without using a passive element such as a resistor. As a result, the detected error voltage is less likely to be affected by variations in resistance and the like and temperature shift, and can generate a small current accurate output signal proportional to a large current input signal.

The signal input circuit according to a second aspect of the present invention further includes a buffer driven by a signal voltage obtained from the input transistor, and a bias current source for driving the buffer at a constant current. The circuit includes a first constant current source for supplying the constant current to the emitters of the fifth and sixth transistors, and a seventh and a fourth source for supplying the collector currents of the fifth and sixth transistors from the power source, respectively. An eighth transistor, ninth and tenth transistors forming a current mirror circuit with the seventh and eighth transistors, respectively, and extracting currents flowing through the seventh and eighth transistors, and the ninth transistor Further comprising eleventh and twelfth transistors forming a current mirror circuit which folds a current flowing through The bias current is increased or decreased by generating the correction current by a push-pull operation of ninth and twelfth transistors, and the current conversion circuit includes a thirteenth transistor driven by an output voltage of the buffer, A fourteenth transistor having a common emitter with the transistor to form a differential pair; and a second transistor for supplying an emitter current of the thirteenth and fourteenth transistors.
A constant current source, and a reference voltage source that holds a base of the fourteenth transistor at a predetermined reference voltage, and is configured to derive an output current from collectors of the thirteenth and fourteenth transistors. And claim 3
In the current conversion circuit, the first to twelfth transistors, the buffer, the bias current source, and the first constant current source are provided two each, and the output voltage of one buffer is supplied to the base of the thirteenth transistor in the current conversion circuit. The output voltage of the other buffer is applied to the base of the fourteenth transistor in place of the reference voltage, and two output currents having a mutual difference proportional to the difference between the two signal currents are derived.

Therefore, one circuit can cope with the differential input of the light receiving element of the optical pickup.

In the signal input circuit according to a fourth aspect of the present invention, the signal current source is a photoelectric conversion element such as a photodiode used as a light receiving element of an optical pickup.

Therefore, the above-mentioned photoelectric conversion device has a large dynamic range of the signal current, so that the present invention can be suitably implemented.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram in consideration of an emitter series resistance of a signal input circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a functional configuration of the signal input circuit shown in FIG.

FIG. 3 is a graph showing a relationship between an input current, an error voltage, and a correction voltage in the signal input circuit shown in FIGS. 1 and 2;

FIG. 4 is an electric circuit diagram in consideration of an emitter series resistance of a signal input circuit according to another embodiment of the present invention.

5 is a graph showing a relationship between an ideal output current ratio and an actual output current ratio error in the signal input circuit shown in FIG. 4;

FIG. 6 is an electric circuit diagram of a differential circuit which is a typical prior art signal input circuit.

FIG. 7 is an electric circuit diagram of a differential circuit in consideration of an emitter series resistor, which is another conventional signal input circuit.

[Explanation of symbols]

21, 21a Signal input circuit 22 Error detection circuit 23 Error correction circuit 24 Current conversion circuit B1, B2 Reference voltage source F1 First constant current source F2 Bias current source F3 Second constant current source PO1, PO2 Output terminal Q Input transistor Q1, Q1a First transistor Q2, Q2a Second transistor Q3, Q3a Third transistor Q4, Q4a Fourth transistor Q5, Q5a Fifth transistor Q6, Q6a Sixth transistor Q7, Q7a Seventh transistor Q8 , Q8a Eighth transistor Q9, Q9a Ninth transistor Q10, Q10a Tenth transistor Q11, Q11a Eleventh transistor Q12, Q12a Twelfth transistor Q13, Q13a Thirteenth transistor Q14, Q14a Fourteenth transistor Q30, Q30a buffer Q1R, Q2R, Q3R, Q4R emitter series resistor Q1Ra, Q2Ra, Q3Ra, Q4Ra emitter series resistor S1, S1a signal current source

Continued on the front page F-term (reference) 5J030 BA07 BB01 BB03 BC04 BC06 BC07 5J066 AA03 AA12 AA43 AA56 CA05 CA21 FA08 FA09 HA02 HA17 HA25 HA44 KA02 KA05 KA09 KA26 KA28 ND01 PD02 TA01 TA02 5J090 AA03 F04 HA17 HA25 HA44 HN03 KA02 KA05 KA09 KA26 KA28 SA08 TA01 TA02 5J092 AA03 AA12 AA43 AA56 CA05 CA21 FA08 FA09 HA02 HA17 HA25 HA44 KA02 KA05 KA09 KA26 KA28 SA08 TA01 TA02 UL02

Claims (4)

[Claims] 1. A signal input circuit having a wide dynamic range with a current input in which a signal current is compressed by a logarithmic characteristic of an input transistor and converted into a voltage, then expanded by a transistor in a subsequent stage, converted into a current and output. , Wherein the input transistor comprises a differential pair including first and second transistors having a common emitter to which the signal current is applied and having the same characteristics with a base at the same potential, and An emitter current is supplied to a collector of each of the first and second transistors, a third and a fourth transistor formed to have a predetermined area ratio, and a common emitter to which a constant current is applied. And a differential pair composed of fifth and sixth transistors formed in an area ratio opposite to the area ratio of the fourth transistor. An error detection circuit that generates a correction current corresponding to the collector voltage difference of the second transistor; and a current conversion circuit that converts the output voltage of the input transistor into a current and outputs the converted voltage. A voltage drop caused by the current and a collector voltage of the first and second transistors, and extracting the voltage drop based on the correction current output from the error detection circuit in accordance with the difference between the collector voltages. A signal input circuit for compensating the voltage drop by correcting an output current of the signal input circuit. 2. The semiconductor device according to claim 1, further comprising: a buffer driven by a signal voltage obtained from the input transistor; and a bias current source for driving the buffer with a constant current. A first constant current source for supplying the constant current to the emitter, a seventh and an eighth transistor for respectively supplying collector currents of the fifth and the sixth transistors from the power supply, A ninth and tenth transistor for forming a current mirror circuit with the transistor and extracting a current flowing through the seventh and eighth transistors, respectively, and a current mirror circuit for folding the current flowing through the ninth transistor are formed. Further comprising eleventh and twelfth transistors, wherein the ninth and twelfth transistors are pushed. The correction current is generated by a pull operation to increase or decrease the bias current. The current conversion circuit has a thirteenth transistor driven by an output voltage of the buffer, and an emitter common to the thirteenth transistor. A fourteenth transistor forming a differential pair, a second constant current source for supplying emitter currents of the thirteenth and fourteenth transistors, and a base of the fourteenth transistor maintained at a predetermined reference voltage. The signal input circuit according to claim 1, further comprising a reference voltage source, wherein an output current is derived from collectors of the thirteenth and fourteenth transistors. 3. The current conversion circuit according to claim 1, further comprising two of said first to twelfth transistors, a buffer, a bias current source and a first constant current source. The output voltage of the other buffer is applied to the base of the fourteenth transistor in place of the reference voltage, to derive two output currents having a mutual difference proportional to the difference between the two signal currents. 3. The signal input circuit according to claim 2, wherein: 4. The signal input circuit according to claim 1, wherein the signal current source is an optical-electrical conversion element.