JP2000315382A - Magnetic random access memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an MRAM circuit of which a characteristic does not depend on dispersion of the characteristic of a memory cell depending on a place on a wafer. SOLUTION: This circuit is provide with row decoders 102, 103 decoding one part of an address, column decoders 104, 105 decoding the residual part of the address, plural sense lines 21, 22, 21r, 22r, 24, 25 connected to decoding terminals of the row decoders 102, 103, plural word lines 2a-2c connected to the decoding terminals of the column decoders, plural memory cells 21a-21c, 22a-22c, 23a-23c, plural reference cells 2ra-2rc, and the memory cell and the reference cell are provided with a magnetic resistance element. The plural sense lines and plural word lines intersect in a matrix state, the plural memory cells are connected to the sense line and the word line of an intersection in the intersections relating to one part of sense lines out of the intersections of plural sense lines and plural word lines, the plural reference cells are connected to the sense line and the word line of the intersection in the intersections relating to the other sense lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a magnetic random access memory (MRAM).
ry) circuit (hereinafter referred to as “MRAM circuit”).

[0002]

2. Description of the Related Art In a magnetic random access memory, a plurality of storage cells are arranged at intersections of word lines and bit lines. Basically, the memory cell is composed of an insulating layer or a metal layer and two ferromagnetic layers sandwiching the insulating layer or the metal layer. Digital information is represented by the direction of magnetization of the ferromagnetic layer, and the information is held indefinitely unless intentionally rewritten. In order to rewrite the state of the storage cell, a combined magnetic field larger than a threshold is applied to the storage cell by a word current and a bit current to invert the magnetization of the ferromagnetic layer.

A first technique is disclosed in US Pat. No. 5,785,485.
No. 19 and IEEE Transaction On Components Packaging
and Manufacturing Technology-Part A Vol. 170 No.
FIG. 6 shows a simplified MRAM circuit disclosed in 3pp373-379 using a giant magnetoresistive (GMR) element as a memory cell and simplified.
This MRAM circuit is generally formed on a semiconductor substrate,
Other circuits are mixed on the same substrate. The MRAM circuit includes a memory array (a first array 604 and a second array 60).
5), decoder (row decoder 602 and column decoder 60)
3) and a comparator 606. Row decoder 60
2 and the column decoder 603 are connected to the address bus 601 respectively. First array 604 and second array 6
One of 05 is used as a reference cell at the time of reading.

A second prior art is disclosed in US Pat.
No. 0343, a magnetic tunnel junction (MT
J: Magnetic Tunnel Junction) FIG. 7 shows an MRAM circuit having a memory array in which one memory cell is arranged at the intersection of each word line and sense line using an element as a memory cell. This MRAM circuit includes row decoders 701 and 7
02, column decoders 703 and 704, and a matrix circuit having magnetic tunnel junction elements at intersections connected to these. Although this MRAM circuit operates in accordance with the stored information in accordance with the magnitude of the sense current, this disclosure does not describe a method of detecting a voltage or a method of connecting to a comparator (sense amplifier).

[0005]

In the first prior art,
Since a separate word line is required for each of the storage cell and the reference cell, the storage cell array and the reference cell array are separated,
Or they are far apart. Therefore, each comparison signal easily includes a parasitic element, and it is difficult to realize a sufficient operation margin. Therefore, uniformity of the characteristics of the storage cell on the wafer has been required. In addition, since the memory cell area is large, integration and miniaturization are difficult. Further, in the first prior art, since two cells are required for one address, the storage cell area is large, and it is difficult to integrate and reduce the size.

The present invention provides an MRA in which the characteristics do not depend on the variation in the characteristics of the magnetoresistive element depending on the location on the wafer.
It is an object to provide an M circuit. Also, the present invention
It is an object of the present invention to provide an MRAM circuit capable of highly sensitive reading while eliminating the influence of wiring resistance as much as possible. Furthermore,
The present invention relates to an MR having an effective circuit configuration for integration.
An object of the present invention is to provide an AM circuit.

[0007]

A magnetic random access memory circuit according to the present invention comprises a row decoder for decoding a part of an address, a column decoder for decoding the remaining part of the address, and a decode terminal of the row decoder. A plurality of sense lines connected thereto, a plurality of word lines connected to a decode terminal of the column decoder, a plurality of storage cells, and a plurality of reference cells, wherein the storage cells and the reference cells are magnetoresistive. An element, the plurality of sense lines and the plurality of word lines intersect in a matrix, and among the intersections of the plurality of sense lines and the plurality of word lines, the plurality of A storage cell is connected to a sense line and a word line at an intersection, and the plurality of reference cells are connected to a sense line and a word line at the intersection at an intersection related to another sense line. And wherein the door.

Further, the magnetic random access memory circuit according to the present invention is characterized in that in the above magnetic random access memory circuit, the storage cell and the reference cell further include a diode connected in series to the magnetoresistive element. I do.

Further, the magnetic random access memory circuit according to the present invention is characterized in that in the above magnetic random access memory circuit, the storage cell and the reference cell further include a transistor connected in series to the magnetoresistive element. I do.

Further, in the magnetic random access memory circuit according to the present invention, in the above magnetic random access memory circuit, there are two row decoders, two column decoders, and each of the plurality of pairs of sense lines is , The decoding terminals of the two row decoders are connected to each other, and the plurality of word lines are connected to the decoding terminals of the two column decoders.

Further, in the magnetic random access memory circuit according to the present invention, in the above magnetic random access memory circuit, at the time of writing, the two row decoders correspond to the value of information to be written to the sense line of the selected row. A current in a predetermined direction, and the two column decoders supply a current in a predetermined direction to a word line in a selected column.

Further, in the magnetic random access memory circuit according to the present invention, in the above magnetic random access memory circuit, at the time of reading, the row decoder and the column decoder are at the intersection of a selected row and a selected column. A current having the same value is supplied to a reference cell at an intersection of a storage cell, a predetermined row, and the selected column.

Further, in the magnetic random access memory circuit according to the present invention, in the magnetic random access memory circuit described above, at the time of reading, the terminal of the memory cell at the intersection of the selected row and the selected column on the sense line side is connected. The image processing apparatus further includes comparing means for comparing a voltage with a voltage of a terminal on a sense line side of a reference cell at an intersection of the predetermined row and the selected column.

Further, in the magnetic random access memory circuit according to the present invention, in the above magnetic random access memory circuit, the comparing means includes a comparator and two input terminals respectively connected to two input terminals of the comparator. Two auxiliary lines, a plurality of transistors for connecting one of the two auxiliary lines to a sense line connected to a memory cell of a selected row, and the other of the two auxiliary lines One or more transistors for connection to a sense line to which a reference cell in a row is connected.

Further, in the magnetic random access memory according to the present invention, in the magnetic random access memory circuit described above, at the time of reading, a memory cell to be read and a reference cell at an intersection of a column of the memory cell to be read and the predetermined row are read. Means for flowing a current, and means for detecting a voltage drop in a reference cell at an intersection of a storage cell to be read and a column of the storage cell to be read and the predetermined row by a four-terminal method when the current flows in the reference cell. It is characterized by the following.

Furthermore, a magnetic random access memory circuit according to the present invention is characterized in that, in the above magnetic random access memory circuit, the magnetoresistive element is a spin tunnel element.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to FIGS.

[First Embodiment] First, a first embodiment of the present invention will be described.

FIG. 1 shows an MRAM circuit according to the first embodiment. This MRAM circuit includes a memory array 106, a decoder 30, and a comparator 107. Memory array 1
06 denotes a plurality of storage cells 21a, 21b, 21c, 22
a, 22b, 22c, 23a, 23b, 23c, and reference cells 2ra, 2rb, 2rc. These memory cells are composed of word lines 2a, 2b, 2c and sense lines 21,
It is arranged at the intersection of 22, 2r and 23.

The decoder set includes the row decoders 102, 1
03 and column decoders 104 and 105,
These are connected to the address bus 101. The column decoder 104 includes switch transistors 111 and 112,
The word lines 2a, 2b, and 2c are switched to a write state or a ground level state by turning on / off these switches. The row decoder 102 includes switch transistors 131 and 132,
133, 134, 141, 142, 143, and 144, and connects the sense lines 21, 22, 2r, and 23 to a predetermined circuit in the row decoder 102.

One end of the sense line (auxiliary line) 24 is connected to the sense lines 21, 22, 23 via pass transistors 151, 152, 154. The other end of the sense line 24 is connected to the plus input terminal of the comparator 107. One end of the sense line (auxiliary line) 25 is connected to the sense line 2r via the pass transistor 153. The other end of the sense line 25 is connected to the negative input terminal of the comparator 107.

Reference numerals 21a, 21b, 21c, 22
a, 22b, 22c, 23a, 23b, and 23c are storage cells. Reference cells 2ra, 2rb, and 2rc are reference cells, and by arranging them near the storage cells, the influence of wiring resistance can be reduced.

FIG. 2 shows the structure of the memory cell 21a. Other storage cells 21b, 21c, 22a, 22b, 22c, 2
3a, 23b, 23c and reference cells 2ra, 2rb,
2rc also has the same structure as the storage cell 21a.

In the memory cell 21a, a first ferromagnetic layer 81 and a second ferromagnetic layer 82 are stacked via an insulating layer 83. For the ferromagnetic layers 81 and 82, for example, a ferromagnetic material such as Ni-Fe-Co is used, and for the insulating layer 83, for example, Al ₂ O ₃ is used. These three layers 81, 82, 83 constitute a spin tunnel effect element. An interlayer insulating film 84 is provided between the insulating layer 83 and the sense line 21. The word line 2a is arranged below the first ferromagnetic layer 81, and applies a magnetic field generated by the current to the spin tunnel effect element. The sense line 21 is connected to the second ferromagnetic layer 82.

To write information into the ferromagnetic layers 81 and 82, a word current is applied to the word lines and a sense current is applied to the sense lines, and the resultant magnetic field generated by the word lines is applied to the ferromagnetic layers 81 and 82.
This is performed by reversing the direction of magnetization of 82. Reading of information from the memory cell 21a is performed by detecting a voltage between the word line 2a and the sense line 21.

FIG. 3 shows the relationship between the resistance of the memory cell (this corresponds to the output voltage) and the applied magnetic field. The horizontal axis indicates the direction and intensity of the applied magnetic field. The vertical axis indicates the resistance value of the memory cell 21a. As shown in FIG. 3, the relationship between the resistance of the storage cell and the applied magnetic field shows hysteresis characteristics. The resistance value of the cell 21a at zero magnetic field shows the same value regardless of the magnetic field vector direction. Increasing the magnetic field from zero to H _1, rotating only the magnetization direction of one side of the ferromagnetic layer of the memory cell by a synthetic magnetic field, the magnetization directions of two ferromagnetic layers of the memory cell is opposite to each other, the resistance increases I do. Combined magnetic field strength is increasing from H ₁ to H _2, reaches the H _2, also rotates the magnetization direction of the side where the magnetization direction has not changed, H ₂
, The resistance decreases. Similarly, a similar phenomenon occurs in the zero magnetic field, H ₃ , and H ₄ by applying a magnetic field in the opposite direction.

Next, a method for writing information to the memory cell 21a will be described.

In order to select the sense line 21, the transistors 131 and 141 are turned on. Word line 2
The transistors 111 and 121 are turned on to select a. When writing information "1" into the memory cell 21a, a sense current 92 and a word current 91 are supplied to the sense line 21 and the word line 2a, respectively. Conversely, the memory cell 21
When writing the information “0” to “a”, the same word current 91 as the sense current 93 opposite to the sense current 92 is supplied to the sense line 21 and the word line 2a, respectively.

The reference cells 2ra, 2rb, and 2rc are also magnetized to a predetermined value by the same method as that for writing information to the memory cell 21a, so that the resistance value is set to a value between the minimum value and the maximum value.

Next, a method for reading information from the memory cell 21a will be described.

The transistors 131, 133 and 121 are turned on to select the sense lines 21 and 2r and the word line 2a. Next, a constant current is applied to the storage cell 21a and the reference cell 2ra. The sense current Is is a transistor 131,
The row decoder 102 and the column decoder 10 pass through the sense line 21, the memory cell 21a, the word line 2a, and the transistor 121.
Flow between 5 On the other hand, the reference sense current Ir flows between the row decoder 102 and the column decoder 105 via the transistor 133, the sense line 2r, the memory cell 2ra, the word line 2a, and the transistor 121. In this state, the transistors 151 and 153 are turned on, and the comparator 107 detects the potential on the sense line side of the storage cell 21a and the reference cell 2ra. This is a method based on the so-called four-terminal method. That is, this is a measurement method in which a path through which current flows and a path through which voltage is detected are separately provided. Regarding the four-terminal method, for example,
"Experimental Chemistry Course 9 Electric and Magnetic (4th Edition)" (edited by The Chemical Society of Japan), pages 165 to 167. Since the storage cell 21a and the reference cell 2ra are arranged close to each other, the influence of the wide variation in the wiring resistance is small, and the comparator 1
07 storage cell 21a and reference cell 21ra
Are in proportion to the resistance values of the storage cell 21a and the reference cell 21ra, respectively. Binary information determined according to the difference between the potentials input to the comparator 107 is output to the bit line 26.

As shown in FIG. 4, a spin tunnel effect element 401 is provided between a sense line and a word line as a memory cell.
And a diode 402 connected in series, the selectivity between the storage cells is further improved. That is, it is possible to reduce the influence of the unselected storage cell on the selected storage cell due to the current flowing through the unselected storage cell.

[Second Embodiment] Next, a second embodiment of the present invention will be described.

FIG. 5 is an MRAM according to the second embodiment of the present invention.
1 shows a circuit. This MRAM circuit includes a memory array 506,
It comprises a decoder set and a comparator 107. The memory array 20 includes a plurality of storage cells 31a, 31b, 31c,
32a, 32b, 32c, 33a, 33b, 33c and reference cells 3ra, 3rb, 3rc. These storage cells and reference cells are composed of a spin tunnel effect element and a pass transistor connected in series, and include word lines 2a, 2b, 2c and sense lines 21, 22, 23,
It is arranged at the intersection of 2r.

The method for writing information to the storage cells in this embodiment is the same as that in the first embodiment, and a description thereof will be omitted.

Next, a method for reading information from the storage element 31a will be described.

The transistors 131, 133 and 121 are turned on to select the sense lines 21 and 2r and the word line 2a. Next, the wiring 71 is set to a high potential state,
The transistor connected to 1 is turned on. Next, a constant current is applied to the storage cell 31a and the reference cell 3ra. The sense current Is is supplied to the transistor 131 and the sense line
1, storage cell 31a, word line 2a, transistor 12
1 flows between the row decoder 102 and the column decoder 105. On the other hand, the reference sense current Ir is
3, flows between the row decoder 102 and the column decoder 105 via the sense line 2r, the memory cell 3ra, the word line 2a, and the transistor 121. In that state, the transistor 151,
153 is turned on, and the storage cell 31a and the reference cell 3
The comparator 107 detects the potential of ra on the sense line side. This is a method based on the so-called four-terminal method.

Since the memory cell 31a and the reference cell 3ra are arranged close to each other, the influence of wiring resistance is small, and the comparator 1
07, the potential on the sense line side of the storage cell 31a and the reference cell 3ra is equal to the potential of the storage cell 31a and the reference cell 3r.
a is proportional to the resistance value on the sense line side. Binary information determined according to the difference between the potentials input to the comparator 107 is output to the bit line 26.

In the above embodiment, the reference cell row is only one row. However, a reference cell row is provided for each of a predetermined number of storage cell matrices, and a plurality of reference cell rows are provided in the entire MRAM circuit. May be included.

[0040]

As described above, the MR according to the present invention is used.
By arranging the storage cell and the reference cell close to each other, the characteristics of the AM circuit can be stabilized without depending on the wide-area variation in the characteristics of the storage cell and the reference cell on the wafer.

Further, according to the present invention, by using a measurement method based on the four-terminal method as a voltage detection method, highly sensitive information can be read out while the influence of wiring resistance and the like is extremely eliminated.

Furthermore, even if the wiring resistance is increased by miniaturizing the wiring, the influence of the wiring resistance is small, so that the MRAM circuit according to the present invention can be highly integrated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a magnetic random access memory circuit according to a first embodiment of the present invention.

2A and 2B are a cross-sectional view and a plan view illustrating a structure of a magnetoresistive element used as a storage cell and a reference cell.

FIG. 3 is a graph showing a relationship between a resistance of a magnetoresistive element and a magnetic field.

FIG. 4 is a circuit diagram of a second example of storage cells and reference cells of the magnetic random access memory circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a magnetic random access memory circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a magnetic random access memory according to a first conventional example.

FIG. 7 is a circuit diagram showing a configuration of a magnetic random access memory according to a second conventional example.

[Explanation of symbols]

2a, 2b, 2c Word lines 21, 21r, 22, 22r, 24, 25 Sense lines 21a, 21b, 21c, 22a, 22b, 22c, 2
3a, 23b, 23c Storage cell 2ra, 2rb, 2rc Reference cell 26 Bit line 31a, 31b, 31c, 32a, 32b, 32c, 3
3a, 33b, 33c Storage cell 3ra, 3rb, 3rc Reference cell 111, 112, 113, 121, 122, 123 Transistor 131, 132, 133, 134 Transistor 141, 142, 143, 144 Transistor 101 Address line 102, 103 Row decoder 104, 105 column decoder 106, 506 memory array 107 comparator

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[Procedure amendment]

[Submission date] April 30, 1999 (1999.4.3)
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

[Title of the Invention] Magnetic random access memory circuit

Claims (10)

[Claims] A row decoder for decoding a part of the address; a column decoder for decoding the remaining part of the address; a plurality of sense lines connected to a decode terminal of the row decoder; A plurality of word lines connected to terminals, a plurality of storage cells, and a plurality of reference cells, wherein the storage cells and the reference cells include a magnetoresistive element, the plurality of sense lines and the plurality of words. The lines cross in a matrix, and among the intersections of the plurality of sense lines and the plurality of word lines, the plurality of storage cells are connected to the sense lines and the word lines at the intersections at intersections related to some of the sense lines, 2. The magnetic random access memory circuit according to claim 1, wherein the plurality of reference cells are connected to the sense line and the word line at the intersection at another intersection. 2. The magnetic random access memory circuit according to claim 1, wherein said storage cell and said reference cell further include a diode connected in series with said magnetoresistive element. . 3. The magnetic random access memory circuit according to claim 1, wherein said storage cell and said reference cell further include a transistor connected in series to said magnetoresistive element. . 4. The magnetic random access memory circuit according to claim 1, wherein there are two row decoders, two column decoders, and each of said plurality of pairs of sense lines. Is connected between respective decode terminals of said two row decoders, and each of said plurality of word lines is connected between respective decode terminals of said two column decoders. . 5. The magnetic random access memory circuit according to claim 4, wherein at the time of writing, the two row decoders pass a current in a direction corresponding to a value of information to be written to a sense line of a selected row, A magnetic random access memory circuit, wherein the two column decoders supply a current in a predetermined direction to a word line of a selected column. 6. The magnetic random access memory circuit according to claim 1, wherein at the time of reading, the row decoder and the column decoder operate at an intersection of a selected row and a selected column. A magnetic random access memory circuit characterized in that a current of the same value flows through a reference cell at an intersection of a certain storage cell, a predetermined row, and the selected column. 7. The magnetic random access memory circuit according to claim 6, wherein at the time of reading, a voltage of a terminal on a sense line side of a memory cell at an intersection of a selected row and a selected column and the predetermined row A magnetic random access memory circuit, further comprising comparing means for comparing a voltage of a terminal on a sense line side of a reference cell at an intersection of the selected cell and the selected column. 8. The magnetic random access memory circuit according to claim 7, wherein said comparing means includes: a comparator; and two auxiliary lines each connected to each of two input terminals of said comparator. A plurality of transistors for connecting one of the two auxiliary lines to a sense line to which a memory cell of a selected row is connected, and a reference cell of the predetermined row connecting the other of the two auxiliary lines. 1 for connecting to the sense line
Or, a magnetic random access memory circuit comprising: two or more transistors. 9. The magnetic random access memory circuit according to claim 1, wherein at the time of reading, a reference at an intersection of a storage cell to be read, a column of the storage cell to be read, and the predetermined row. Means for passing a current through the cell, and means for detecting a voltage drop in the memory cell to be read and a voltage drop in the reference cell at an intersection of a certain column of the memory cell to be read and the predetermined row by a four-terminal method. A magnetic random access memory circuit comprising: 10. The magnetic random access memory circuit according to claim 1, wherein said magnetoresistive element is a spin tunnel element.