JP2000315173A - Memory control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control device that processing time is improved by preventing the same bank in an SDRAM from being continuously accessed. SOLUTION: Relating to the memory control device 3 for controlling the SDRAM 2 having two banks 0, 1 and capable of executing continuous accesses by a bank division mode for alternately and continuously inputting the addresses of respective banks 0, 1 by individually precharging the banks 0, 1, memory addresses obtained from respective blocks 4, 5 for accessing the SDRAM 2 through the device 3 are address-converted so that these address are alternately inputted to respective banks 0, 1 of the SDRAM 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory control device for controlling a synchronous dynamic random access memory (hereinafter abbreviated as SDRAM).

[0002]

2. Description of the Related Art In recent years, SDRAMs capable of performing high-speed burst transfer of a cache memory frequently used in personal computers in synchronization with a clock have been used. This SDRAM can be switched between a continuous access mode and a random access mode by a bank division mode. In this bank division mode, the MSB (most significant bit) of a memory address is “0” as two memory areas. 0 and the bank 1 whose MSB of the memory address is "1". The bank 0 and the bank 1 are alternately accessed by clock control, and while the data of one bank is being read, the other is being read. It is possible to take in bank addresses.

[0003] As a memory control device for controlling the SDRAM, for example, those described in JP-A-8-111090 and JP-A-8-212170 are generally known. The memory control device 11 for controlling the SDRAM described in Japanese Patent Application Laid-Open No. 8-212170 has a structure shown in FIG.
As shown in FIG. 5, the memory control unit 12 and the arbitration / Wait signal generation unit 13 are provided.
The access to the SDRAMs 4 to 17 is controlled.

A memory address signal (MADD), a data signal (DATA), and a read / write control signal (RD / WR) are sent from a plurality of blocks 14 to 17 to memory control units 18a to 18d corresponding to the respective blocks. Is input to The memory access request signal (CS) from each of the blocks 14 to 17 is input to the arbitration / wait signal generation means 13, and the arbitration / wait signal generation means 13 returns a wait signal (Wait) to each of the blocks 14 to 17. .

[0005] The memory control unit corresponding to the block receiving the memory access permission signal (Enable) from the arbitration / Wait signal generating means 13 is an SDRAM of the permitted block.
2 is controlled. An example of the read access timing of the SDRAM 2 using the memory control device 11 will be described. Here, the SDRAM 2 is in the bank split mode.

If the MSB of the memory address from the block is "0", bank 0 is selected, and if the MSB is "1", bank 1 is selected. As shown in FIG.
According to K, the row address R0 and column address C0 of bank 0 and the row address R1 and column address C1 of bank 1 are alternately loaded into the SDRAM. Bank 0
Data D00 and D01 of row 1 are stored in row address R of bank 1.
1, output at the clock timing when the column address C1 is input. D01 is data at an address following D00, which means that two-word data can be output with one address input. If only one word is required, D01 is not required.

[0007] The precharge of each bank consists of final data,
That is, in the case of 2-word output, it is automatically executed at the output timing of the data D01. The same applies to bank 1. As described above, the access to the banks 0 and 1 of the SDRAM is performed alternately so that the access is continuously performed without any gap.

[0008]

However, in the conventional memory control device, when the SDRAM is set to the bank division mode and a single block accesses the SDRAM, it is continuously connected to the same bank (for example, bank 0). If a memory address to be accessed is continuously output from this single block, access to bank 0 will continue. At this time, no address can be output to bank 0 until the precharge operation for bank 0 is completed. That is, there is a problem that a useless cycle in which the SDRAM cannot be accessed occurs.

Therefore, when a single block accesses the SDRAM, it is conceivable to solve the above-mentioned problem by generating a memory address so as to alternately access each bank on the single block side. However, when a plurality of blocks access the SDRAM, it is extremely difficult to correlate the memory addresses from each block. Therefore, since there is no correlation between the memory addresses from each block, there is a possibility that the same bank is accessed continuously.

For example, immediately after block A accesses bank 0, when block B attempts to access bank 0, access to the same bank continues. At this time, no address can be output to bank 0 until the precharge operation for bank 0 is completed. That is, there is a problem that a useless cycle in which the SDRAM cannot be accessed occurs.

An object of the present invention is to provide a memory control device which prevents continuous access to the same bank of an SDRAM and improves processing time.

[0012]

SUMMARY OF THE INVENTION A memory control device according to the present invention is configured to convert a memory address from a block so that the address is alternately input to each bank of the SDRAM. According to the present invention, SD
It is possible to provide a memory control device which prevents continuous access to the same bank of the RAM and improves processing time.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to a first aspect of the present invention is directed to a bank dividing mode in which a plurality of banks are individually precharged so that address inputs of the banks are alternately continued without gaps. A memory control device for controlling a synchronous dynamic random access memory (hereinafter abbreviated as SDRAM) capable of continuous access by the SDRAM via the memory control device
A memory controller configured to convert a memory address from a block accessing M into an address such that an address is alternately input to each bank of the SDRAM. Even when a memory address is output from a block, the memory address from the block can be converted so that the banks are alternated, the banks can always be accessed alternately, and the SDRAM cannot be accessed. It is possible to eliminate unnecessary cycles, issue commands continuously to the SDRAM, improve processing time, and generate memory addresses without regard to banks for each block that generates memory addresses. can do.

According to a second aspect of the present invention, the internal address is divided into at least two banks, and the precharge is executed individually so that the address input of each bank is alternately continued without gaps. Synchronous dynamic random access memory (hereinafter abbreviated as SDRAM) that enables switching between continuous access and random access mode by the enabled bank division mode.
An arbiter for arbitrating a memory access request from a plurality of blocks accessing the SDRAM via the memory control device;
A command generation block for generating a memory command to the SDRAM, and a memory address from a block to which the arbiter has given access,
The SDRAM performs address conversion to a row and column address in which an address is alternately input to each bank of the AM.
And a block to which the access right is given by temporarily latching the write data from the block to which the access right is given by the arbiter or the read data from the SDRAM.
A data latch block for transferring data between RAMs, and controlling the SDRAM as a pair of different banks in units of memory access from each block so that the banks of the SDRAM are alternated. Even if there is no correlation between the memory addresses from a plurality of blocks,
Multiple banks can be accessed alternately without having to access the same bank of the DRAM consecutively, memory access in the bank split mode is easily guaranteed, and commands are continuously issued to the memory. Therefore, the processing time can be improved.

According to a third aspect of the present invention, in the case where the memory block from the block to which the access right is given is not a pair of different banks, the number of memory accesses from the block is not excessive. 3. The memory control device according to claim 2, wherein the memory control device is configured to generate and output a mask signal for disabling the access data for the SDRAM in the SDRAM. Since resetting is unnecessary, it is only necessary to control only the mask signal without changing the memory access unit of the bank, so that the control can be simplified and the circuit can be simplified accordingly. it can.

Hereinafter, a memory control device according to the present invention will be described based on specific embodiments. (Embodiment 1) The memory control device according to the embodiment 1 shown in FIG. 1 has two banks 0 and 1 as in the conventional example, and executes a precharge individually to each bank 0. , 2 which can be continuously accessed by a bank division mode in which address inputs of.
As shown in FIG. 1, a memory address from blocks 4 and 5 that access the SDRAM 2 via the memory controller 3 is stored in the SDRA as shown in FIG.
The difference from the prior art is that the address conversion is performed so that the address is alternately input to each bank of M2.

As shown in FIG. 1, the memory control device 3 includes a plurality of blocks 4 and 5 for accessing the SDRAM 2.
An arbiter 6 for arbitrating a memory access request from
A command generation block 7 for generating a memory command to the SDRAM 2, and a memory address from a block to which an access right is given by the arbiter 6 is converted into a row and column address such that an address is alternately input to each bank of the SDRAM 2. An address conversion block 8 that outputs the data to the SDRAM 2 from the block to which the access right has been given by the arbiter 6 or a read data from the SDRAM 2 to temporarily latch the write data from the block to which the access right has been given. It comprises a data latch block 9 for transferring data.

The blocks 4 and 5 include a computer and an error correction block. For example, data transfer between the host computer and the microcomputer is executed via the SDRAM 2 or erroneous data is deleted by the error correction block. Or make corrections. Here, the operation of the memory control device 3 when writing data from the block 4 to the SDRAM 2 in the bank split mode will be described below.

Here, when the mode setting provided for the SDRAM 2 is Burst-Length "2", that is, when a certain address is specified, data of a total of two words of data for the address and data for the next address are obtained. It is assumed that access is set. When the block 4 accesses the SDRAM 2, the address, data, and control signals are transferred via the memory control device 3.

The block 4 outputs a write request signal to the arbiter 6 of the memory control device 3. Arbiter 6
Returns a permission signal to the block 4 if no other block is accessing the SDRAM 2, and if the block 5 outputs a request signal simultaneously with the request signal of the block 4, the priority signal is returned. A permission signal is returned to the block having the higher right. Here, it is assumed that the block 4 has the highest priority and the arbiter 6 permits the block 4 to access the SDRAM 2.

The arbiter 6 instructs the address conversion block 8 to fetch a memory address output from the permitted block 4 and instructs the data latch block 9 to fetch data to be written output from the block 4. . At the same time, RAS (Row
Address Strobe), CAS (Column Address Strobe)
The command generation block 7 is also instructed to generate a memory command group starting with.

Here, the address conversion processing in the address conversion block 8 will be described. The address conversion block 8 converts the memory address from the block 4 into an SDRAM
The address conversion is performed such that the address is alternately input to each of the banks 0 and 1 of the second bank. SDRAM2 is Burst-Length
Since “2” is set, the memory address output from the block 4 is a memory address incremented by two as shown in FIG. 2A. The MSB of the memory address is a bank address.
Is "0", bank 0 is selected, and if "1", bank 1 is selected. Therefore, the MSBs of the memory address before conversion shown in FIG. 2A are all "0". The bank 0 of the SDRAM 2 is continuously selected.

Therefore, the second bit from the LSB (least significant bit) of the memory address before conversion shown in FIG. 2A is set as the MSB of the converted memory address as shown in FIG. 2 (a), the upper side of the third bit from the LSB of the memory address before the conversion is bit-shifted to the lower side by one bit to convert the address into the converted memory address as shown in FIG. 2 (b). .

As shown in FIG. 2B, since the MSB of the converted memory address is 0 and 1 alternately, the banks 0 and 1 can always be accessed alternately, and the memory address is generated. For each block, a memory address can be generated without being aware of the bank. As described above, the address conversion block 8 converts the address of the memory address as described above, and outputs the row and column addresses generated based on the converted memory address shown in FIG.

The data latch block 9 outputs the latched write data to the SDRAM 2, respectively.
The command generation block 7 converts the memory command into S
Output to DRAM2. Here, the access timing to each bank of the SDRAM 2 will be described. As shown in FIG. 3, the row address R00 and the column address C00 of the bank 0, and the row address R10 and the column address C10 of the bank 1 are alternately taken in according to the clock CK. The data D00 and D01 of the bank 0 are output at the clock timing when the row address R10 and the column address C10 of the bank 1 are input. D01 is data of an address following D00, and 2 bits are input by one address input.
This means that word data can be output. The precharge of each bank is automatically executed at the output timing of the final data, that is, data D01, D11, D03, etc. at the time of outputting two words. The same applies to bank 1.

With this configuration, even when a memory address that continuously accesses the same bank of the SDRAM 2 is output from the block, the memory address from the block is changed so that the bank is alternated. Can be converted to prevent continuous access to the same bank. That is, the bank can always be accessed alternately, and unnecessary cycles in which the SDRAM 2 cannot be accessed can be eliminated.
A command can be issued to the AM2, processing time can be improved, and a memory address can be generated without regard to a bank for each block that generates the memory address.

In the first embodiment, the SDRAM 2
Although the case where rst-Length is set to “2” has been described as an example, for example, when it is set to Burst-Length “4”, as shown in FIG. 4B is set as the MSB of the converted memory address as shown in FIG.
4B, the upper side of the 4th bit from the LSB of the memory address before conversion may be bit-shifted by 1 bit lower to obtain the converted memory address as shown in FIG. 4B.

When Burst-Length is set to "1", the LSB of the memory address before conversion is changed as shown in FIG. 5A, and the LSB of the memory address after conversion is changed as shown in FIG. The MSB of the memory address is used, and the LSB of the memory address before conversion shown in FIG. 5A is shifted one bit lower from the LSB of the second bit to the LSB of the memory address after the conversion as shown in FIG. Memory address.

(Embodiment 2) A memory control device according to a second embodiment of the present invention is different from the memory control device 3 according to the first embodiment in that each block 0, 1 of the SDRAM 2 is alternated with each block. This embodiment differs from the first embodiment only in that a function of controlling the SDRAM 2 as a pair of different banks in units of memory access from 4 and 5 is added.

The memory control device 3 controls the SDRAM 2 by using a memory access unit from each block as one pair of bank 0 and bank 1 so that the banks are always different. For example, when the SDRAM 2 is in the bank split mode,
When t-Length is set to “2”, as shown in FIG. 6, the access unit of each of the blocks 4 and 5 is set to 4 so that the bank 0 is accessed in two words and the bank 1 is accessed in two words as a pair. It is in word units.

Here, the SDRA in the bank division mode
M2 is accessed by a plurality of blocks (for example, blocks 4 and 5), and data from these blocks 4 and 5 is transmitted to this S.
The operation of the memory control device 3 when writing to the DRAM 2 will be described. Note that SDRAM2
Is a mode setting of Burst-Length “2”. The command generation block 7 and the address conversion block 8
And each data from the data latch block 9 is S
Until the data is output to the DRAM 2, the operation is the same as that of the first embodiment, and the description is omitted here.

As shown in FIG. 6, block 4 is an SDRA
After accessing M2, block 5
Even if M2 is accessed, the access unit of each of the blocks 4 and 5 is accessed in units of 4 words in which the bank 0 is 2 words and the bank 1 is 2 words. Even at the time of switching, banks are always alternated.

With this configuration, even when a plurality of blocks 4 and 5 access the SDRAM 2 and the memory addresses of the blocks 4 and 5 have no correlation, the SDRA
It is possible to prevent continuous access to the same bank of M2. That is, it is possible to always access the bank alternately, and it is possible to eliminate a useless cycle in which the SDRAM 2 cannot be accessed. And the processing time can be improved.

(Embodiment 3) The memory control device 3 according to Embodiment 3 of the present invention uses the command generation block 7 of Embodiment 2 described above in such a manner that the memory access from the block to which the access right is given is different from that of the bank to which the memory access is different. If not a pair of
The second embodiment is different from the second embodiment only in that the SDRAM 2 additionally has a function of generating and outputting a mask signal for disabling access data corresponding to excess or deficiency of memory access from the block in the SDRAM 2.

Here, as shown in FIG. 7, for the SDRAM 2 in the bank split mode, block 4 accesses only bank 0, and block 5 accesses banks 0 and 1 continuously. Data from this SDR
The operation of the memory control device 3 when writing (writing) to the AM 2 will be described. The SDRAM 2 has a Bu
It is assumed that the mode setting is rst-Length “2”.

The block 4 accesses with two words as a unit smaller than the memory access unit (4 words) in the second embodiment. The memory control device 3 accesses the memory command (WRITE) and address (R10, R10, R10) corresponding to the bank 1 regardless of whether a random address is accessed or the block 4 accesses two words as shown in FIG. C10).

If the command generation block 7 is a write as in this example, the write data (D10, D1
A mask signal for disabling 1) in the SDRAM 2 is generated and output to the SDRAM. Note that the write data (D10, D11) shown in FIG. 7B may be any value data.

The SDRAM 2 does not execute only the writing of the write data (D10, D11) in the section where the mask signal is at the high level. With this configuration, conventionally, R
Control not to issue memory commands and addresses including AS and CAS, that is, not to issue memory commands (WRITE) and addresses (R10, C10) to bank 1 of block A as shown in FIG. Memory command must be transmitted to the SDRAM 2 using a plurality of signals (/ CS, / RAS, / CAS, / WE, address, etc.).
Therefore, it is necessary to control all these signals or reset the Burst-Length, and the circuit becomes very complicated. In the control device 3, it is not necessary to control a plurality of signals as in the related art, and it is not necessary to reset Burst-Length. Therefore, it is sufficient to control only the mask signal without changing the memory access unit. Therefore, the control can be simplified, and the circuit can be simplified accordingly.

In each of the above embodiments, the case where data from a block is written to the SDRAM 2 has been described. However, the same effect can be obtained even when data read from the SDRAM 2 is output to the block. Have.

[0040]

As described above, according to the memory control device of the present invention, the memory address from the block accessing the SDRAM via the memory control device is stored in the SDRAM.
The address conversion is performed so that the address is alternately input to each of the banks. Therefore, even if the memory address for accessing the same bank continuously is output from the block, the address is converted from the block. Can be converted so that the banks alternate, and the banks can always be accessed alternately.
It is possible to eliminate a useless cycle in which the RAM cannot be accessed, issue a command continuously to the SDRAM, improve processing time, and without being aware of a bank for each block that generates a memory address. A memory address can be generated.

An arbiter for arbitrating memory access requests from a plurality of blocks accessing the SDRAM, a command generation block for generating a memory command to the SDRAM, and a command generation block for generating a memory command to the SDRAM. When the memory address is
The address is converted to a row and column address so that an address is alternately input to each bank of the DRAM, and
An address translation block to be output to the AM, and a transfer of data between the block to which the access right is granted and the SDRAM by temporarily latching write data from a block to which the access right is given by the arbiter or read data from the SDRAM. And a data latch block for performing the above operation, and when the memory control device is configured to control the SDRAM as a pair of different banks with a unit of memory access from each block so that the banks of the SDRAM are alternately arranged, Even when there is no correlation between memory addresses from blocks, multiple banks can be accessed alternately without continuous access to the same bank, facilitating memory access in bank split mode Command to memory continuously. Since it is Rukoto, it is possible to improve the processing time.

When the memory access from the block to which the access right is given is not a pair of different banks,
In a case where a mask signal for disabling access data corresponding to excess or deficiency of memory access from the block in the SDRAM is generated and output, it is possible to control a plurality of signals and reset Burst-Length as in the related art. Can be made unnecessary, and it is only necessary to control only the mask signal without changing the memory access unit of the bank. Therefore, the control can be simplified, and the circuit can be simplified accordingly.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory control device according to a first embodiment of the present invention;

FIG. 2 is an explanatory diagram showing address conversion in an address conversion block according to the first embodiment;

FIG. 3 is a timing chart showing access timing to each bank according to the first embodiment;

FIG. 4 is an explanatory diagram showing another example of address conversion different from the first embodiment;

FIG. 5 is an explanatory diagram showing another example of address conversion different from that of the first embodiment;

FIG. 6 is a timing chart showing a memory access unit of each block according to the second embodiment of the present invention;

FIG. 7 is a timing chart showing a case where a memory access unit is different according to the third embodiment of the present invention;

FIG. 8 is a block diagram showing a configuration of a conventional memory control device.

FIG. 9 is a timing chart showing access timing to each bank of the conventional memory control device.

[Explanation of symbols]

 2 SDRAM 3 Memory controller 4, 5 Block 6 Arbiter 7 Command generation block 8 Address conversion block 9 Data latch block

Claims (3)

[Claims] A synchronous dynamic random access memory (hereinafter, referred to as a memory) having a plurality of banks and capable of continuous access in a bank division mode in which address inputs of the respective banks are alternately continued without gaps by individually executing precharge. , SDRAM). A memory address from a block that accesses the SDRAM via the memory control device is transferred to the SDRAM.
A memory control device configured to perform address conversion such that an address is alternately input to each of the banks. 2. A continuous access in a bank division mode in which the interior is divided into at least two banks and precharges are individually executed, so that address inputs of each bank can be alternately continued without a gap. A synchronous dynamic random access memory (hereinafter referred to as S
Abbreviated as DRAM. An arbiter that arbitrates memory access requests from a plurality of blocks that access the SDRAM via the memory control device; and a command generation block that generates a memory command to the SDRAM. An address conversion block for converting a memory address from a block to which the access right is given by the arbiter into a row and column address such that an address is alternately input to each bank of the SDRAM and outputting the row and column addresses to the SDRAM; A data latch block for temporarily latching write data or read data from the SDRAM to which the access right has been given by the arbiter and transferring data between the SDRAM and the block to which the access right has been given; A memory control device, wherein the SDRAM is controlled by setting a memory access unit from each block as a pair of different banks so that each bank of the SDRAM is alternated. 3. A method according to claim 1, wherein when the memory access from the block to which the access right is given is not a pair of different banks, the command generation block disallows access data corresponding to excess or deficiency of the memory access from the block in the SDRAM. 3. The memory control device according to claim 2, wherein the memory control device is configured to generate and output a mask signal to be generated.