JP2000312009A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having low on-resistance and improved breakdown voltage characteristic, and to provide the manufacturing method of the semiconductor device. SOLUTION: This semiconductor device is provided with a first silicon epitaxially grown layer 2, having an impurity density lower than that of a silicon substrate 1, is formed on a one-conductive type high impurity density silicon substrate 1, a second epitaxially grown layer 9 having low impurity density, is formed on the first silicon epitaxially grown layer 2, and a source layer 8 and a gate layer 9 are formed on the second silicon epitaxially grown layer 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an electrostatic induction transistor (hereinafter, referred to as SIT) or an electrostatic effect transistor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A manufacturing process of a surface gate type SIT in a conventional semiconductor device will be described with reference to FIGS.

FIG. 3A shows a step of forming a silicon epitaxial growth layer on a silicon substrate 11. The impurity density (N type) is 1 × on the N ⁺ type silicon substrate 11 having the impurity density of 1 × 10 ¹⁸ cm ^{−3 as} the drain layer.
10 ¹⁴ cm ⁻³ silicon epitaxial growth layer 21
Is grown to 50 μm.

FIG. 3B shows a mask forming process using a SiO ₂ film. The surface of the silicon epitaxial growth layer 21 is thermally oxidized to form a SiO ₂ film as thick as about 7000 Å on the entire surface. Then, the SiO ₂ formed on the surface of the silicon epitaxial growth layer 21 is formed.
An opening is formed in the film by a general photolithography method and an etching method, and an SiO ₂ film 3e is formed.

FIG. 3C shows a silicon pit manufacturing process. The silicon substrate 11 is etched by a predetermined thickness of 2 μm in the vertical direction by a reactive ion etching method (referred to as an RIE method) using the SiO ₂ film as a mask to form a silicon pit 41.

[0006] Here, the thickness of the SiO ₂ film as a mask is reduced from 7000 angstroms to 5000 angstroms, as shown in FIG. 3 (c), the SiO ₂ film 3
f.

FIG. 3D shows a step of forming a thermal oxide film.
By heating the entire substrate in an oxygen atmosphere and performing thermal oxidation, a 3000 Å SiO ₂ film 31 c is formed on the entire surface of the silicon epitaxial growth layer 21. Here, the thickness of the already formed SiO ₂ film was 5000 Å, but 800
0 Å and 3 g of SiO ₂ film.

FIG. 3E shows an etching process by the RIE method. The SiO ₂ film is etched over the entire surface of the silicon epitaxial growth layer 21 by using the RIE method. Etching by RIE method, due to the strong directionality along the direction of the electric field to be applied, since only the SiO ₂ film in a plane perpendicular to the electric field direction of the RIE is etched, SiO ₂
In the film 31c, the SiO ₂ film corresponding to the bottom portion of the silicon pit 41 is etched.

[0009] Therefore, with respect to the SiO ₂ film, by performing the etching of 3000 angstroms, SiO ₂ film 3g
Has a thickness of 8000 Å to 5,000 Å, and becomes a SiO ₂ film 3 h. The SiO ₂ film on the side wall of the silicon pit 41 is not etched by 3000 Å, while the SiO ₂ film at the bottom of the silicon pit 4 is entirely etched. Lost by
Silicon appears on the surface. Finally, as the SiO ₂ film, the SiO ₂ film 3h and the SiO ₂ film 31d are formed.

FIG. 3F shows a gate layer forming step.
A non-doped polysilicon layer 51a is formed on the entire surface of the silicon epitaxial growth layer 21 by a CVD method,
Then, P-type impurities are thermally diffused by performing thermal diffusion of boron using boron trichloride (BCl ₃ ), and the non-doped polysilicon layer 51a becomes a P ⁺ polysilicon layer and further thermally diffused. Is continued, a P ⁺ gate layer 61 is formed at the bottom of the silicon pit 41.

FIG. 3G shows a polysilicon wiring step. After the resist is applied, a pattern is formed by photolithography, and then the P ⁺ polysilicon layer is subjected to wet etching to remove unnecessary portions of the P ⁺ polysilicon layer. A P ⁺ polysilicon layer 51b is formed as shown in FIG.

FIG. 4 is an explanatory view of the steps subsequent to FIG. 3 (g). FIG. 4A shows a mask forming process using a resist. In order to form an N ⁺ source layer, a resist 71 is formed by a photolithography method. Next, the SiO ₂ film 3g is etched by the RIE method using the resist 71 as a mask, and an opening is formed in the SiO ₂ film 3g.

FIG. 4B shows a process of forming an N ⁺ source layer. Using the resist 71 as a mask and a gas serving as a doping source of phosphorus (for example, PF ₅ ), an ion implantation method is used.
Phosphorus is implanted into the silicon epitaxial growth layer 21 and N ⁺
A source layer 81 is formed.

In the resist removing step shown in FIG.
The resist 71 is removed by a resist removing device. Thereby, the conventional surface-gate type SIT 101 is completed.
Actually, thereafter, a metal wiring and a passivation film are formed, and an SIT is manufactured (not shown).

[0015]

The conventional surface gate type S
In IT, in order to increase the breakdown voltage, the impurity density of the silicon epitaxial growth layer must be reduced. However, when the impurity density of the epitaxial growth layer is reduced, there is a disadvantage that on-resistance, which is another characteristic, increases. That is, in the conventional surface gate type SIT, it has been difficult to improve the breakdown voltage characteristics and reduce the on-resistance.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a reduced on-resistance and improved withstand voltage characteristics, and a method of manufacturing the same.

[0017]

According to the present invention, a source region and a gate region of the same conductivity type as a silicon substrate are formed on a main surface of a silicon substrate of one conductivity type, and a back surface of the silicon substrate is formed on the back surface of the silicon substrate. Forming a first silicon epitaxial growth layer and a second silicon epitaxial growth layer in a method of manufacturing a surface gate type static induction transistor in which a drain region of the same conductivity type as that of the silicon substrate is formed; The thickness of the substrate required to obtain the first epitaxial growth layer is formed. On the other hand, in order to reduce the electric field concentration on the surface, a high withstand voltage is realized by reducing the substrate concentration of the second silicon epitaxial growth layer.

Further, silicon pits are formed in the second silicon epitaxial growth layer. Further, since the impurity density of the second silicon epitaxial growth layer is low, the depletion layer is easily spread, the height of the potential barrier can be increased, the withstand voltage characteristics can be improved, and the blocking voltage can be increased. Furthermore, in the first silicon epitaxial growth layer, the on-resistance can be reduced because the impurity density is relatively high.

Further, since the second silicon epitaxial growth layer has a low impurity concentration but a small thickness, it is possible to provide a semiconductor device in which increase in on-resistance is minimized.

That is, the present invention relates to a semiconductor device in which a first silicon epitaxial growth layer and a second silicon epitaxial growth layer having the same conductivity type as a silicon substrate are formed on the surface of a silicon substrate of one conductivity type. The conductive silicon substrate is a silicon substrate having a high impurity concentration, a first silicon epitaxial growth layer having an impurity concentration lower than that of the silicon substrate is formed, and an impurity concentration is further formed on the first silicon epitaxial growth layer. A semiconductor device in which a second epitaxial growth layer having a reduced thickness is formed, and a source layer and a gate layer are formed in the second silicon epitaxial growth layer.

According to the present invention, there is provided the semiconductor device described above, wherein a silicon pit is formed in the second silicon epitaxial growth layer, and a gate layer is formed at the bottom of the silicon pit.

According to the present invention, in the semiconductor device, the impurity concentration of the silicon substrate is 1 × 10 ¹⁸ cm ^−3.
To 2 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the first silicon epitaxial growth layer is 1 × 10 ¹⁵ cm ^−3.
−3 to 2 × 10 ¹⁵ cm ⁻³ , and the impurity concentration of the second silicon epitaxial growth layer is 1 × 10 ¹³ cm ^−3.
The semiconductor device has a range from cm ⁻³ to 2 × 10 ¹³ cm ⁻³ .

Further, in the semiconductor device according to the present invention, in the semiconductor device, the region near the gate layer is a layer having a high conductivity concentration of a reverse conductivity type, a layer having a low impurity concentration of a conductivity type, and This is a semiconductor device formed in the order of layers having the impurity concentration of the conductivity type layer.

The present invention also relates to a method of manufacturing a semiconductor device in which a first silicon epitaxial growth layer and a second silicon epitaxial growth layer of the same conductivity type as a silicon substrate are formed on the surface of a silicon substrate of one conductivity type. The one-conductivity-type silicon substrate is a high-impurity-concentration silicon substrate, and forms a first silicon epitaxial growth layer having an impurity concentration lower than that of the silicon substrate, and is formed on the first silicon epitaxial growth layer. And forming a second epitaxial growth layer having a further lower impurity concentration, and forming a source layer and a gate layer in the second silicon epitaxial growth layer.

Further, the present invention is the method for manufacturing a semiconductor device, wherein a silicon pit is formed in the second silicon epitaxial growth layer and a gate layer is formed at the bottom of the silicon pit.

According to the present invention, in the method of manufacturing a semiconductor device, the impurity concentration of the silicon substrate may be 1 × 10 ^18.
cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the first silicon epitaxial growth layer is 1 × 10 ¹⁸
From ¹⁵ cm ^-3 in the range of ^{2 × 10 1 5 cm -3,} 1 × impurity concentration of the second silicon epitaxial layer
This is a method for manufacturing a semiconductor device in a range from 10 ¹³ cm ⁻³ to 2 × 10 ¹³ cm ⁻³ .

Further, according to the present invention, in the method of manufacturing a semiconductor device, the region near the gate layer may be formed in the vertical direction from the surface side in a layer having a high impurity concentration of a reverse conductivity type and a layer having a low impurity concentration of a negative conductivity type. This is a method for manufacturing a semiconductor device in which a layer and a layer having an impurity concentration of a conductivity type layer are formed in this order.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described below with reference to examples.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 and 2 are explanatory views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Here, as the semiconductor device, a surface gate type SIT
Is taken as an example.

FIG. 1A shows that a first silicon substrate 1 is
Forming a silicon epitaxial growth layer 2
You. Impurity concentration is 1 × 10¹⁸cm^-3From 2 × 10
¹⁸cm ^-3Range N⁺On the silicon substrate 1 of the mold,
Impurity concentration is 1 × 10^Fifteencm^{− 3}From 2 × 10^Fifteenc
m^-3N-type first silicon epitaxial in the range
The growth layer 2 is grown to a thickness of 30 μm. Where silico
Substrate 1 is used as a drain layer and has an impurity concentration of
1 × 10¹⁸cm^-3If it is below, the specific resistance will be high and
And the impurity concentration is 2 × 10¹⁸cm^-3Above
If it is, the specific resistance will be low, making it unsuitable for the drain layer.
It becomes out of date. Also, a first silicon epitaxial growth layer
2 is 1 × 10^Fifteencm^-3Is below
And the specific resistance is within the specific resistance range for obtaining the predetermined internal resistance.
Higher, the impurity concentration is 2 × 10 ^Fifteencm^-3Less than
If it is above, the specific resistance is shifted to a low value.

FIG. 1B shows a step of forming the second silicon epitaxial growth layer 9. The impurity concentration of the first silicon epitaxial growth layer 2 is 1 × 10
An N-type silicon epitaxial growth layer in the range of ¹⁵ cm ⁻³ to 2 × 10 ¹⁵ cm ⁻³ and an impurity concentration of 1
The N ⁻ -type second silicon epitaxial growth layer 9 in the range of × 10 ¹³ cm ⁻³ to 2 × 10 ¹³ cm ⁻³ is
grow by μm.

FIG. 1C shows a mask forming step using an SiO ₂ film. Second silicon epitaxial growth layer 9
A SiO ₂ film is formed to a thickness of 7000 angstroms on the entire surface by thermal oxidation. Thereafter, S formed on the surface of the second silicon epitaxial growth layer 9 is formed.
An opening is formed in the SiO ₂ film by a general photolithography method and an etching method in the iO ₂ film.
An iO ₂ film 3a is formed.

FIG. 1D shows a silicon pit forming step. Using the SiO ₂ film 3a as a mask by the RIE method,
The silicon substrate 1 is vertically etched by a predetermined thickness of 2 μm to form a silicon pit 4. Here, the depth of the silicon pit 4 is formed so as not to reach the first silicon epitaxial growth layer 2. Here, the thickness of the SiO ₂ film serving as the mask is reduced from 7000 Å to 5000 Å, and is slightly reduced to become the SiO ₂ film 3d.

The steps from FIG. 1 (e) to FIG. 1 (k)
This is the same as the steps shown in FIGS. 3D to 3G in the conventional example. Therefore, a detailed description is omitted here. The gate layer 6 is formed by the same method as in the related art.

FIG. 2 is an explanatory view of a method of manufacturing a semiconductor device according to an embodiment of the present invention, which is a continuation of the step shown in FIG. 1 (h).

FIG. 2A shows a mask forming step using a resist. In order to form an N ⁺ source layer, a resist 7 is formed by a photolithography method. Next, using the resist 7 as a mask, the SiO ₂ film 3d is etched by RIE, and an opening is formed in the SiO ₂ film 3d.

FIG. 2B shows a process of forming an N ⁺ source layer. Using the resist 7 as a mask, phosphorus is implanted into the second silicon epitaxial growth layer 9 by ion implantation using a gas serving as a doping source of phosphorus (for example, PF ₅ ).
⁺ Source layer 8 is formed.

FIG. 2C shows a resist removing step.
The resist 7 is removed by a resist removing device. Thereby, the semiconductor device according to the present invention, the surface gate type SIT1
00 is completed.

FIG. 2D shows the surface gate type SIT.
FIG. 3 is a diagram showing a state of a channel depletion layer 10 around a gate in FIG.

The channel depletion layer 10 near the gate layer
The main portion is formed in the second silicon epitaxial growth layer 9, and the second silicon epitaxial growth layer 9 has an impurity concentration of 1 × 10 ¹³ cm ⁻³ to 2 × 1
Since the resistivity is low in the range of 0 ¹³ cm ^-3 , the specific resistance is high, and when a reverse bias is applied between the gate and the source, the depletion layer 10 of the channel tends to greatly expand. As a result, the height of the potential barrier between the gate and the source is increased, and high withstand voltage characteristics such as blocking current between the source and the drain are obtained. Here, the impurity concentration of the second silicon epitaxial growth layer 9 is 1 × 10 ¹³ cm ^−3.
If it is less than or equal to, the specific resistance shifts to a higher value than the specific resistance range for obtaining a predetermined high withstand voltage characteristic, and the impurity concentration becomes 2 or less.
If it is × 10 ¹³ cm ⁻³ or more, the specific resistance is shifted to a lower one.

Conversely, when a forward current flows between the gate and the source, the depletion layer 10 of the channel shrinks, the height of the potential barrier decreases, and the current between the source and the drain flows more easily or the ON state decreases. Resistance tends to decrease.

With this structure, since the impurity concentration of only the gate layer is low, the on-resistance can be reduced, and the high withstand voltage characteristics can be achieved.

In consideration of the breakdown voltage between the gate and the drain, the lower the impurity concentration on the surface, the higher the breakdown voltage because of the planar structure. Here, the second silicon epitaxial growth layer 9 is the surface, and since the impurity concentration of the second silicon epitaxial growth layer 9 is low, the withstand voltage can be increased.

By combining such steps, a high breakdown voltage surface type SIT having a small on-resistance and excellent blocking characteristics is completed.

[0045]

As described above, according to the present invention, it is possible to provide a semiconductor device having a reduced on-resistance and improved withstand voltage characteristics and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a view showing a step of forming a first silicon epitaxial growth layer, FIG. 1B is a view showing a step of forming a second silicon epitaxial growth layer, and FIG. shows a mask forming step by ₂ film, FIG. 1 (d) shows the step of forming the silicon pits, Fig 1 (e) is a diagram showing a thermal oxide film formation step, and 1 (f) show the subimages, RIE method FIG.
FIG. 1G is a diagram showing a gate layer forming step, and FIG.
9 is a diagram showing a polysilicon wiring step.

FIG. 2 is a view showing a step subsequent to FIG. 1 in the method of manufacturing the semiconductor device according to the embodiment of the present invention; FIG. 2A is a view showing a mask forming step using a resist, and FIG.
FIG. 2C is a diagram illustrating a source layer forming process, FIG. 2C is a diagram illustrating a resist removing process, and FIG. 2D is a diagram illustrating a state of a depletion layer near a gate layer.

FIG. 3 is a diagram showing a conventional method of manufacturing a semiconductor device, and FIG.
FIG. 3A is a diagram illustrating a process of forming a silicon epitaxial growth layer, FIG. 3B is a diagram illustrating a mask forming process using a SiO ₂ film, FIG. 3C is a diagram illustrating a process of forming a silicon pit, FIG. 3D is a view showing a thermal oxide film forming step, FIG. 3E is a view showing an etching step by RIE, FIG. 3F is a view showing a gate layer forming step,
(G) is a figure which shows the polysilicon wiring process.

FIG. 4 shows a conventional method for manufacturing a semiconductor device.
FIG. 4 is a view showing a step that follows the step in FIG. 3; 4A is a view showing a mask forming step using a resist, FIG. 4B is a view showing a source layer forming step, and FIG. 4C is a view showing a resist removing step.

[Explanation of symbols]

1,11 (N ⁺ ) silicon substrate 2 (N ⁻ ) first silicon epitaxial growth layer 9 (N ⁻ ) second silicon epitaxial growth layer 21 (N ⁻ ) silicon epitaxial growth layer 3a, 3b, 3c, 3d, 3e, 3f , 3g, 3h
SiO ₂ films 31a, 31b, 31c, 31d SiO ₂ films 4,41 Silicon pits 5a, 51a (Non-doped) polysilicon layers 5b, 51b (P ⁺ ) polysilicon layers 6,61 (P ⁺⁾ gate layers 7 , 71 resist 8, 81 (N ⁺⁾ source layer 10 channel depletion layer 100, 101 surface gate type SIT

Claims (8)

[Claims] 1. A semiconductor device in which a first silicon epitaxial growth layer and a second silicon epitaxial growth layer of the same conductivity type as a silicon substrate are formed on a surface of a silicon substrate of one conductivity type, The substrate is a silicon substrate having a high impurity concentration, a first silicon epitaxial growth layer having a lower impurity concentration than the silicon substrate is formed, and a first silicon epitaxial growth layer having a lower impurity concentration is further formed on the first silicon epitaxial growth layer. A semiconductor device, wherein two epitaxial growth layers are formed, and a source layer and a gate layer are formed in the second silicon epitaxial growth layer. 2. The semiconductor device according to claim 1, wherein a silicon pit is formed in the second silicon epitaxial growth layer, and a gate layer is formed at a bottom of the silicon pit. 3. The semiconductor device according to claim 1, wherein the silicon substrate has an impurity concentration of 1 × 10 ^18.
cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the first silicon epitaxial growth layer is 1 × 10 ¹⁸
The range is from ¹⁵ cm ⁻³ to 2 × 10 ¹⁵ cm ⁻³ , and the impurity concentration of the second silicon epitaxial growth layer is 1 ×
A semiconductor device having a range of 10 ¹³ cm ⁻³ to 2 × 10 ¹³ cm ⁻³ . 4. The semiconductor device according to claim 1, wherein the region near the gate layer is a layer having a high impurity concentration of an opposite conductivity type in a vertical direction from the surface side, A semiconductor device comprising: a layer having a low impurity concentration; and a layer having an impurity concentration of a conductivity type layer. 5. A method for manufacturing a semiconductor device, comprising forming a first silicon epitaxial growth layer and a second silicon epitaxial growth layer of the same conductivity type as a silicon substrate on a surface of a silicon substrate of one conductivity type. The conductive type silicon substrate is a high impurity concentration silicon substrate, in which a first silicon epitaxial growth layer having an impurity concentration lower than that of the silicon substrate is formed, and an impurity concentration is further formed on the first silicon epitaxial growth layer. Forming a second epitaxial growth layer having a reduced thickness, and forming a source layer and a gate layer in the second silicon epitaxial growth layer. 6. The method according to claim 5, wherein a silicon pit is formed in the second silicon epitaxial growth layer, and a gate layer is formed at a bottom of the silicon pit. apparatus. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the impurity concentration of the main substrate is 1 × 1.
0 ¹⁸ cm ⁻³ to 2 × 10 ¹⁸ cm ⁻³ ,
The impurity concentration of the first silicon epitaxial growth layer is set to 1
The range is from × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁵ cm ⁻³ , and the impurity concentration of the second silicon epitaxial growth layer is from 1 × 10 ¹³ cm ⁻³ to 2 × 10 ¹³ cm ^−3.
A method for manufacturing a semiconductor device. 8. The method for manufacturing a semiconductor device according to claim 5, wherein the region near the gate layer is formed in a vertical direction from the surface side to a layer of a high conductivity concentration of a reverse conductivity type, A method of manufacturing a semiconductor device, comprising: forming a conductive type layer having a low impurity concentration; and forming a conductive type layer having an impurity concentration in this order.