JP2000306822A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To align a target with a reference position with high accuracy, even after a wafer is subjected to CMP(chemical-mechanical polishing) process. SOLUTION: At exposure of a resist film, formed on a wafer which carries Cu wiring formed by damascene method and is subjected to a CMP process to the original image of a reticle by projecting the image in reduction upon the resist film, the wafer is aligned by using a target 8 constituted by alternately arranging a plurality of lines 8a, each of which is composed of a dot pattern 8c and a plurality of spaces 8b. Since each line 8a of the target 8 is formed by using the dot pattern 8c, the occurrence of defective shapes can be prevented, even after the wafer is subjected to the CMP process. Therefore, the alignment accuracy of the target with a reference position can be improved, because the target 8 can be recognized with accuracy at performing of the alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor device, and more particularly to a technique for aligning mutually superposed patterns. For example, in a semiconductor device manufacturing process, a semiconductor wafer (hereinafter, referred to as a wafer) is used. The present invention relates to a technique effective for transferring an integrated circuit pattern (hereinafter, referred to as a circuit pattern) including a semiconductor element formed on a photomask as an exposure master.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing factory, a step-and-repeat type reduction projection exposure apparatus (hereinafter, referred to as a stepper) is widely used to transfer a circuit pattern of a photomask onto a wafer. Since a semiconductor device is manufactured by sequentially superposing and exposing a plurality of types of circuit patterns related to each other on a wafer, a stepper uses an enlarged photomask (hereinafter, referred to as a reticle) and a wafer to be exposed. Alignment is extremely important for maintaining the quality and reliability of semiconductor devices and promoting ultra-miniaturization.

In a conventional stepper, the following alignment is performed instead of directly aligning the reticle with the wafer. First, the reticle is positioned to a preset reference position. The wafer-side coordinate system and the alignment marks formed on the wafer (hereinafter referred to as
The target. ) For observing the
It is called an alignment optical system. ) To the reference position. An error (deviation) from the reference position of the alignment optical system to the target is measured. Statistical processing of measured values,
The X, Y, and Θ positions of the wafer are corrected based on the processing result, and then the wafer is exposed.

As a target, a pattern unique to each model of a stepper such as a cross or a line and space is used, and this target pattern is formed simultaneously with a circuit pattern on a wafer by lithography.

[0005] Japanese Patent Application Laid-Open No. Hei 3-96219 discloses an example of a method of aligning a stepper.

[0006]

Incidentally, with the miniaturization of semiconductor integrated circuits, the use of copper (Cu) wiring has been considered. In order to realize the use of the Cu wiring, it has been proposed to form the Cu wiring by damascene technology. Further, as a technology for realizing the formation of the Cu wiring by damascene technology, chemical mechanical polishing (hereinafter referred to as C
MP. It has been proposed to use a) process.

However, it has been revealed by the present inventors that when a wafer target undergoes a CMP process, a shape error of the target pattern occurs, so that there is a problem that alignment with a stepper cannot be performed. .

It is an object of the present invention to provide a positioning technique capable of performing positioning with high accuracy even after a CMP process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the alignment is performed by using a target constituted by alternately arranging a plurality of lines and spaces, wherein each of the lines is constituted by a dot pattern. Features.

According to the above-mentioned means, by forming each line of the target by a dot pattern, C
Since it is possible to prevent a shape defect from occurring even after the MP process, it is possible to accurately recognize the target when aligning the target with the reference position, thereby improving the alignment accuracy. Can be.

[0013]

1A and 1B show a target used in a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view, FIG. 1B is an enlarged partial plan view,
(C) is sectional drawing which follows the cc line of (b). FIG. 2 is a perspective view showing a stepper used in the reduction projection exposure step of the semiconductor device manufacturing method according to one embodiment of the present invention. FIG. 3 shows a wafer, (a) is a plan view,
(B) is a cross-sectional view of a chip portion, and (c) is a cross-sectional view of a target portion. FIG. 4 et seq. Are diagrams for explaining the operation.

The method of manufacturing a semiconductor device according to the present embodiment includes a CMP process for forming Cu wiring by damascene, and a target for realizing alignment of a wafer having undergone the CMP process is provided. An exposure step performed by the alignment method used is provided. In other words, the target is used in a positioning method for positioning the wafer and the reticle in the exposure step of exposing the original pattern of the reticle onto the resist on the wafer by using the stepper 10 to expose the lower layer pattern. Hereinafter, a description will be given mainly of a reduction projection exposure step of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, the stepper 10 shown in FIG. 2 used for performing the reduction projection exposure step will be described.
An original image of the circuit pattern is drawn on the reticle 14, and this image is projected on the wafer 1 via the reduction projection lens 15 of the stepper 10 in the exposure step. The reduction projection lens 15 is configured so that the wafer side becomes a telecentric system. The wafer 1 is automatically conveyed from a cassette 16 onto a loading table 17, is roughly positioned by a pre-alignment device 18, and is vacuum-adsorbed to a chuck 13 on an XY stage 12 by a transfer arm 11.

On the other hand, the reticle 14 is aligned by the reticle alignment optical system 20 so that the center of the reticle 14 coincides with the center of the reduction projection lens 15. This stepper includes a through-the-lens type position detection X system 21 and a position detection Y system 22 for positioning the reticle 14 and the wafer 1. Both detection systems 21, 2
The illumination optical device 2 is provided with an illumination optical device and a half mirror 24. The illumination optical device is configured to irradiate light having a wavelength at which the resist is not exposed to the target 8 to be described later through the half mirror 24. The half mirror 24 transmits the illumination light of the illumination optical device, and
Is reflected on the position detection X system 21 and the position detection Y system 22. Position detection X system 2
The 1 and position detection Y system 22 is configured to scan a slit with a specular reflection image from the target 8 and detect the image with a photomultiplier tube, and also detect a window pattern of the reticle 14.

A laser beam 31 is provided outside the XY stage 12.
Laser interferometer 3 for measuring the position of wafer 1
The laser beam 31 emitted from the laser interferometer 30 is divided into two systems by a spectroscope 32. One of the laser beams 31 is the XY stage 1
The light is applied to the X-axis mirror 33 attached to the second mirror 2. This irradiation light is reflected by the X-axis mirror 33 and returns to the laser interferometer 30 where the X coordinate of the XY stage 12 is detected. The other laser beam 31 is applied to the Y-axis mirror 36 attached to the XY stage 12 via both mirrors 34 and 35, respectively. The laser beam 31 irradiated and reflected on the Y-axis mirror 36 passes through both mirrors 34 and 35 and the spectroscope 32 to reach the laser interferometer 30 so that the Y coordinate of the XY stage 12 is detected. .

The XY stage 12 is configured to be controlled to move in the X-axis direction with high precision by an X-axis motor 37 and to be controlled to move in the Y-axis direction with high precision by a Y-axis motor 38.

The wafer 1 on the chuck 13 after the operation is completed
Is the unloading table 4 by the transfer arm 11
Transferred to 0. For example, the wafers 1 transferred onto the unloading table 40 are sequentially accommodated in the collection cassette 41 by an air bearing mechanism configured on the unloading table 40.

Next, a description will be given of an alignment method in the reduction projection exposure step of the method of manufacturing a semiconductor device according to one embodiment of the present invention. Here, in order to make the explanation easy to understand, in this alignment method, the alignment of the wafer that has undergone the CMP process for realizing the formation of the Cu wiring by the damascene technique uses a target that has been CMPed together with the Cu wiring. The case in which the positioning is performed will be specifically described.

That is, as shown in FIG. 3 (a), a plurality of chip portions 2 are regularly and vertically arranged on a wafer 1 and defined by scribe lines 3. A desired circuit pattern is formed every two. As shown in FIG. 3B, the insulating film 6 deposited on the main surface of the substrate 4 in the chip portion 2 of the wafer 1 on the side of the active area 5 has a Cu wiring by the damascene technique. (Hereinafter referred to as Cu wiring) 7 is embedded. As shown in FIG. 3C, a target 8 is formed on the insulating film 6 in the scribe line 3 of the wafer 1 by lithography and CMP together with the Cu wiring 7. A resist film 9 is applied on the insulating film 6 on which the Cu wiring 7 and the target 8 are formed.

In this embodiment, the target 8 is shown in FIG.
It is configured as shown in FIG. That is, FIG.
As shown in (a), the target 8 has a plurality of lines 8a and a plurality of spaces 8b arranged at both ends in parallel and alternately with each other, and is formed in a rectangular shape as a whole. Each line 8a and each space 8b
Are formed identically, and the width L of the line 8a is 6 μm.
m, and the pitch P is set to 12 μm.

As shown in FIG. 1B, each line 8a is constituted by a dot pattern 8c in which a large number of dots 8d are regularly arranged vertically and horizontally and arranged in a line shape. The dots 8d are formed to be square in plan view. As shown in FIG. 1C, assuming that the width of one dot 8d is W, the thickness is t, and the minimum line width of a rule for forming a circuit pattern is S, the width of one dot 8d Is set to satisfy S ≦ W <t. However, the relationship between the width W and the thickness t satisfies the aspect ratio of the damascene groove with respect to the formation of Cu when forming the dots 8d by the damascene technique.
That is, by making the width W of the dot 8d smaller than the depth of the damascene groove corresponding to the thickness t of the dot 8d,
The damascene groove is set to be completely filled with a Cu material for forming the dots 8d.

As described above, the wafer 1 sent to the stepper 10 in the state where the resist film 9 has been applied through the CMP process is used by the pre-alignment device 18 using the two targets 8 in the wafer 1. Thus, coarse positioning in the XY directions and the rotation direction is performed. At this time, in the case of the stepper 10, since there is no rotation mechanism on the XY stage 12, the stepper 10 is positioned on the pre-alignment device 18 such that a rotation error is minimized.

The pre-aligned wafer 1 is transferred onto the chuck 13 by the transfer arm 11. The wafer 1 transported and adsorbed on the chuck 13 is subjected to optical alignment using a plurality of targets 8 in the wafer 1. Here, since the targets 8 are arranged on the scribe lines 3 of the respective chip sections 2, the targets 8 are evenly arranged in the entire wafer 1.

For example, the target 8 of the chip unit 2 arranged at the upper left corner in FIG.
Is moved and positioned by the XY stage 12 below. The movement of the XY stage 12 is controlled based on the design data of the Cu wiring 7 to be exposed.
At this time, since the wafer 1 is pre-aligned by the pre-alignment device 18, as shown in FIG. 4A, the target 8 actually formed on the scribe line 3 has the mark M indicating the reference position. Very close to. That is, a situation where the target 8 is not photographed in the visual field 19 shown in FIG. 4A does not occur, and the following measurement process is always ensured.

When the target 8 is observed by the position detection X system 21 and the position detection Y system 22, the target 8 and the mark M indicating the reference position are completely overlapped as shown in FIG. The XY stage 12 is moved. As the XY stage 12 moves, an error amount with respect to a design value (design shot) in the X direction is obtained based on the data of the position detection X system 21, and the Y direction is determined based on the data of the position detection Y system 22. Is obtained.

Next, for example, the target 8 of the chip portion 2 arranged at the lower right corner in FIG. 3A is moved and positioned below the reduction projection lens 15 by the XY stage 12. As in the case of the target 8 of the chip portion 2 at the upper left corner, the target 8 is in a state very close to the reference position (see FIG. 4A).

The target 8 at the lower right corner is the position detecting X system 21.
When observed by the position detection Y system 22, the XY stage 12 is moved so that the target 8 at the lower right corner and the mark M indicating the reference position completely overlap (see FIG. 4B). As the XY stage 12 moves, an error amount with respect to a design value (design shot) in the X direction is obtained based on the data of the position detection X system 21, and the Y direction is determined based on the data of the position detection Y system 22. Is obtained.

In FIGS. 3 and 4, both the target 8 and the mark indicating the reference position are shown only with outlines. However, in actual measurement, outline processing is not required. Is obtained, the error amount can be measured.

Thereafter, errors are similarly obtained for a plurality of targets 8 specified in advance in the wafer 1.

From the position measurement results for the plurality of targets 8, components such as the rotation of the wafer 1, the offset (off) in the XY directions, and the expansion and contraction in the XY directions are calculated by statistical processing. Based on this calculation, the XY stage 12 moves and positions the wafer 1 in a step-and-repeat manner, and the original image of the reticle 14 is sequentially transferred to the resist film 9 of the wafer 1 for each shot.

By the way, it has been revealed by the present inventor that when the target of the wafer undergoes the CMP process, an abnormal shape of the target pattern occurs. That is, as shown in FIG. 5A, in the case of the conventional target 80 formed by the line 81 having the width L of 6 μm or more, the line 81 is formed by the depression 82 due to dishing by CMP. 5B, or a line 81 as shown in FIG.
Shape defects due to the slurry 84 remaining on the edge portion 83 of the above. Line 81 of target 80
If a shape defect occurs in the target 80,
When aligning the target and the reference position, the accuracy of recognition of the target 80 is reduced, so that the alignment accuracy is reduced. As a result, the quality and reliability of the exposure process are reduced.

However, in the present embodiment, since each line 8a of the target 8 is formed by the dot pattern 8c, a shape defect does not occur even after the CMP process. That is, when the line 8a of the target 8 is formed by the dot pattern 8c, as shown in FIG. 5C, since the width W of the single dot 8d is narrow, the drop due to dishing in the CMP is reduced. No slurry is generated, and no slurry remains on each dot 8d. As described above, since the shape defect does not occur in each line 8a of the target 8, the target 8 can be recognized with high accuracy when the target 8 is aligned with the reference position, and the alignment accuracy can be improved. As a result, the quality and reliability of the exposure process can be improved.

According to the above embodiment, the following effects can be obtained.

1) By forming each line of the target with a dot pattern, it is possible to prevent a shape defect from occurring even after a CMP process. The target can be accurately recognized, and the alignment accuracy can be improved.

2) When aligning the target with the reference position, the quality and reliability of the reduced projection exposure process can be improved by accurately recognizing the target and improving the alignment accuracy. The quality and reliability of the manufacturing method can be improved.

FIGS. 6A and 6B show a target according to a second embodiment of the present invention, wherein FIG. 6A is a plan view and FIG.
It is sectional drawing which follows the -b line.

This embodiment is different from the above embodiment in that
The point is that each line of the target 8 is formed by a narrow line 8e. According to the present embodiment, since the target 8 is formed by a group of narrow lines 8e, it is possible to prevent a shape defect from occurring even after a CMP process. The same operation and effect as described above can be obtained.

FIGS. 7A and 7B show a target according to a third embodiment of the present invention. FIG. 7A is a plan view, and FIG.
It is sectional drawing which follows the -b line.

This embodiment is different from the above embodiment in that
Each line of the target 8 is formed by a narrow line 8e, and a pair of reinforcing lines 8 is provided at both ends of the line 8e group.
f and 8f are formed. According to the present embodiment, since the target 8 is formed by a group of narrow lines 8e, it is possible to prevent a shape defect from occurring even after a CMP process. The same operation and effect as described above can be obtained. Moreover, since the reinforcing lines 8f are reinforced by the reinforcing lines 8f, it is possible to prevent each of the narrow lines 8e from peeling off from the insulating film 6.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, the present invention can be applied not only to the step-and-repeat exposure method but also to an exposure method using a step-and-scan type reduction projection exposure apparatus.

Further, when a means for reading a pattern is provided, it can be used for an electron beam exposure method using an electron beam direct drawing apparatus. That is, the alignment method according to the present invention is not limited to the light exposure method, and can be used for all exposure methods such as an electron beam exposure method.

[0045]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

By forming each line of the target with a dot pattern, it is possible to prevent a shape defect from occurring even after a CMP process. Therefore, when aligning the target with the reference position, Can be recognized with high accuracy, and the alignment accuracy can be improved.

[Brief description of the drawings]

1A and 1B show a target used in a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is an enlarged partial plan view, and FIG. Cc
It is sectional drawing which follows a line.

FIG. 2 is a perspective view showing a stepper used in a reduction projection exposure step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

3A and 3B show a wafer, wherein FIG. 3A is a plan view, FIG. 3B is a sectional view of a chip portion, and FIG. 3C is a sectional view of a target portion.

FIG. 4 is a diagram for explaining an alignment method;
(A) is a screen diagram showing a state where the target and the reference position are shifted, and (b) is a screen diagram showing a state where the target and the reference position are matched.

FIGS. 5A and 5B are enlarged partial cross-sectional views for explaining the operation, in which FIGS. 5A and 5B show the case of the conventional example, and FIG. 5C shows the case of the present embodiment, respectively.

6A and 6B show a target used in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, wherein FIG. 6A is a plan view and FIG. 6B is a cross-sectional view taken along line bb of FIG. It is.

7A and 7B show a target used in the method for manufacturing a semiconductor device according to the third embodiment of the present invention, wherein FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along line bb of FIG. It is.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Chip part, 3 ... Scribe line, 4
... Substrate, 5 ... Active area, 6 ... Insulating film, 7 ... Cu wiring (circuit pattern), 8 ... Target,
8a: line, 8b: space, 8c: dot pattern, 8d: dot, 8e: narrow line, 8f: reinforcement line, 80: target, 81: line, 82: depression, 83: edge, 84: slurry .. 9 resist film 10 stepper 11 transfer arm 12 XY
Stage, 13 chuck, 14 reticle (exposure original), 15 reduction projection lens, 16 cassette, 17
Loading table, 18 ... Pre-alignment device,
19: visual field, 20: reticle alignment optical system, 21
... Position detection X system, 22 ... Position detection Y system, 24 ... Half mirror, 30 ... Laser interferometer, 31 ... Laser light, 32
... Spectroscope, 33 ... X-axis mirror, 34, 35 ... Mirror,
36: mirror for Y axis, 37: motor for X axis, 38: motor for Y axis, 40: unloading table, 41: cassette for collection.

Claims (10)

[Claims] 1. A target comprising a plurality of lines and spaces alternately arranged, wherein each of the lines is constituted by a dot pattern, and alignment is performed using a target. A method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein each of the dots forming the dot pattern is formed by a damascene method, and a damascene groove is completely filled with a material for forming the dots. Of manufacturing a semiconductor device. 3. Each dot constituting the dot pattern is formed in a square shape in plan view, and the width is W, the thickness is t, and the minimum line width of a rule for forming a circuit pattern is S. 3. The method according to claim 1, wherein the width is set to satisfy S ≦ W <t. 4. The line according to claim 1, wherein each of the lines and each of the spaces are formed in the same manner, the line width is set to 6 μm, and the pitch is set to 12 μm. 13. The method for manufacturing a semiconductor device according to item 5. 5. A method in which alignment is performed using a target configured by alternately arranging a plurality of lines and spaces, wherein each of the lines has a narrow target. A method for manufacturing a semiconductor device. 6. The method according to claim 5, wherein the line is formed by a damascene method, and a damascene groove is completely filled with a material for forming the line. . 7. Assuming that the width of the line is W, the thickness is t, and the minimum line width of a rule for forming a circuit pattern is S, the width is set to satisfy S ≦ W <t. 7. The method of manufacturing a semiconductor device according to claim 5, wherein 8. The apparatus according to claim 5, wherein each of the lines and each of the spaces are formed identically, the width of the line is set to 6 μm, and the pitch is set to 12 μm. 13. The method for manufacturing a semiconductor device according to item 5. 9. A line according to claim 5, wherein a reinforcing line is connected to the line group so as to intersect.
9. A method for manufacturing a semiconductor device according to item 8. 10. The method according to claim 9, wherein a pair of reinforcing lines are connected to both ends of the line group so as to be orthogonal to each other.