JP2000305864A - Method for diagnosing bus interface circuit and bus interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute various diagnoses on a bus interface circuit and to prevent other devices connected to a bus from being adversely affected by diagnosis. SOLUTION: A diagnosis instruction circuit 125 outputs an instruction signal for instructing the start of the diagnosis of a bus interface circuit 104 to a bus interface control circuit 124 and a bus output control circuit 123. The circuit 123 instructs a control bus 103 to execute the output of a control signal other than a start signal, i.e., the output of a command signal from a command output register, and the output of an enable signal from an enable signal output register. The circuit 124 sets up the data pattern of diagnosis testing data in each of an address output register 115, a data output register 117 and a bus control output register 119 and instructs the output of the data pattern to respective buses 101 to 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit diagnosing method for diagnosing a bus interface circuit in a bus interface circuit comprising a series of circuits for interfacing with a bus in an information processing device or the like. And a bus interface circuit embodying the bus interface circuit diagnosis method.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a bus interface circuit for realizing a bus interface circuit diagnostic method according to an example of the prior art. Here, the bus connected to the bus interface circuit 10 constitutes, for example, a bidirectional bus A0. As shown in FIG. 6, the bidirectional bus A0 includes a data bus A1 through which data is transmitted, and a data bus A1. An address bus A2 for transmitting a device address of a partner device as a transfer destination, and a bus control line A for controlling data writing to the partner device and data reading from the partner device.
And 3. The bus interface circuit 10 connected to the bidirectional bus A0 includes a receiver 11a,
11b, three-state drivers 12a and 12b,
Data input register 13 and data output register 14
, Address output register 15 and address comparison circuit 1
6, an input / output control circuit 17, and a bus interface control circuit 18. Here, the bus control line A3 is common to the devices connected to the bidirectional bus A0, and is connected to the input / output control circuit 17 of the bus interface circuit 10. The input / output control circuit 17
It receives an address match signal D1 from the address comparison circuit 16 and outputs an input / output control signal D2. here,
The input / output control signal D2 includes an input strobe signal input to the data input register 13 and a signal for controlling each output enable terminal of the three-state drivers 12a and 12b.

The bus interface control circuit 18 is a bus interface circuit 1 connected to the bidirectional bus A0.
0 controls the input / output operation. The bus interface control circuit 18 sends the data input line B
1, the data to be transferred to the partner device via the data output line B2 is set in the data output register 14, and the device address for specifying the partner device via the address output line B3 is set in the address output register 15. Is set. Further, the bus interface control circuit 18 exchanges an input / output operation control signal D3 with the input / output control circuit 17. Bus interface control circuit 18
Is connected to a diagnosis notification line A4.
In this case, an instruction signal for notifying the start of diagnosis of the bus interface circuit 10 and a signal for notifying the diagnosis result are transmitted.

Next, the operation of the bus interface circuit diagnosing method in the bus interface circuit 10 having the above configuration, particularly the diagnosis of the data write / transfer operation, will be described. First, when the bus interface control circuit 18 receives a diagnosis start instruction signal via the diagnosis notification line A4, the bus interface control circuit 18 sets the write data for the diagnostic test in the data output register 14 and sets itself, that is, The device address of the device provided with the bus interface circuit 10 is set in the address output register 15, and the input / output operation control signal D3 is sent to the input / output control circuit 17 to instruct data communication transfer to the communication partner, that is, itself. Next, the input / output control circuit 1
7 outputs an input / output control signal D2 to enable the outputs of the three-state drivers 12a and 12b, thereby connecting the data output register 14 to the data bus A1.
And outputs the device address in the address output register 15 to the address bus A2. Further, the input / output control circuit 17 outputs a control signal for notifying the data write transfer to the bus control line A3. Next, the address comparing circuit 16 compares the device address on the address bus A2 with itself, that is, the device address of the device having the bus interface circuit 10, and when the comparison result matches, outputs the address match signal D1. Output to the input / output control circuit 17. Next, when the input / output control circuit 17 receives, from the bus control line A3, a control signal notifying that it is a data write transfer to itself, the input / output control circuit 17 sends the input / output control signal D3 to the bus interface control circuit 18 to transmit the data. Notify input. Next, the bus interface control circuit 18 receives the data received by the data input register 13 from the data bus A1 via the data input line B1, and compares the data with the write data for the diagnostic test. This comparison result is output to the diagnosis notification line A4.

Next, an EISA (Extended Industry Standa
The operation for performing a diagnosis on the (rd Architecture) bus will be described with reference to FIGS. FIG. 7 is a timing chart when diagnosing the EISA bus by the bus interface circuit diagnostic method according to the prior art. Here, the MREQ signal is a signal of negative logic (invalid at "1" level, valid at "0" level) for requesting the arbitration circuit (not shown) of bus A0 to use the bus A0. , Are signals that are associated one-to-one with each device (hereinafter, referred to as an agent) connected to the bus A0 and the arbitration circuit. An arbitration circuit (not shown)
Is installed between a CPU such as an information processing apparatus provided with the bus A0 and the bus A0, and designates a priority in using the bus A0 to each agent. MAC
The K signal is used to notify the agent that has requested the right to use the bus by the MREQ signal that the use of the bus A0 is permitted from the arbitration circuit of the bus A0. This is a signal of negative logic associated with one to one. The START signal is a signal of negative logic notifying that the agent that has acquired the bus A0 starts a bus transaction. The W_R signal indicates whether the started bus transaction is a read transaction or a write transaction. M
The _IO signal indicates the type of the started bus transaction. The BE <3: 0> signal (“<3: 0>”
>, <2>, <1>, <0>) are 4
It indicates a valid byte position in the D <31: 0> signal which is byte-width data. The LA <31: 2> signal is an address. Here, the LA <31: 2> signal corresponds to a signal on the address bus A2, the D <31: 0> signal corresponds to a signal on the data bus A1, and other signals, that is, the W_R signal and the M_IO signal. , BE <3: 0> signals, ST
The ART signal corresponds to the signal on the bus control line A3.

As shown in FIG. 7, first, the bus interface circuit 10 outputs an MREQ signal to the arbitration circuit of the bus A0 in order to request the right to use the bus A0 in the T0 cycle, and the arbitration circuit in the T2 cycle. The use of the bus A0 is permitted by the MACK signal from. Next, the bidirectional bus interface circuit 10 starts the bus transaction in the T3 cycle.
Signal and other control signals W_R signal and M_I
The O signal and the BE <3: 0> signal are output to the bus control line A3, and the LA <31: 2> signal is output to the address bus A2. Next, the bidirectional bus interface device 10 outputs the data D <31: 0> in the T4 cycle.
The signal is output to the data bus A1. Next, when the bus transaction is completed in the T4 cycle, the bus interface circuit 10 relinquishes the right to use the bus A0 and
In order to release 0, the MREQ signal is invalidated in the T5 cycle. Next, the bus interface circuit 10
In six cycles, the MACK signal is invalidated and the bus A0 is released.

[0007]

However, in the bus interface circuit diagnosis method in the bus interface circuit 10 having the above-described structure, the data pattern among the data output to the bidirectional bus A0 for the diagnosis for the sake of bus control is included. Can be freely set, only the D <31: 0> signal for the data bus A1, and other signals, for example, the LA <31: 2> signals output to the address bus A2, are fixed pattern signals. For this reason, a complete diagnosis cannot be performed on the bidirectional bus A0, and a failure may not be found during the diagnosis. Furthermore,
When a failure occurs in the address bus A2, for example, if a bus transaction is executed for another device connected to the bidirectional bus A0, the data of this device is destroyed and the device becomes inoperable. There is a risk that it will. The present invention has been made in view of the above circumstances, and, when diagnosing a bus interface circuit, sets an arbitrary data pattern and a bus transaction type to diagnose a bus including an address bus and a control bus in addition to a data bus. It is another object of the present invention to provide a bus interface circuit diagnostic method and a bus interface circuit capable of performing the bus interface circuit without adversely affecting other devices connected to the bus.

[0008]

In order to solve the above-mentioned problems and achieve the above object, a bus interface circuit diagnostic method according to the present invention according to the first aspect of the present invention provides a method for diagnosing output data output to a bus of an information processing apparatus. A bus interface circuit diagnostic method for performing a diagnosis by comparing the input data received from the bus with a diagnostic instruction signal for instructing the start of the diagnosis, and converting the output data having an appropriate data pattern When outputting to the bus, a start signal for validating a bus cycle is not output to the bus.

Further, according to a second aspect of the present invention, there is provided a bus interface circuit diagnostic method for diagnosing a bus interface circuit by comparing output data output to a bus of an information processing apparatus with input data received from the bus. A method for transmitting a diagnostic instruction signal for instructing a device connected to the bus to start diagnosis, and a notification signal for notifying that any of the devices is under diagnosis. A second process for transmitting to all the devices connected to the bus, and a third process for receiving the diagnosis instruction signal and outputting the output data having an appropriate data pattern to the bus, When the notification signal is received while the diagnosis instruction signal is not received, all inputs from the bus are invalidated.

A bus interface circuit according to a third aspect of the present invention is a bus interface circuit that performs diagnosis by comparing output data output to a bus of an information processing device with input data received from the bus. An input / output buffer connected to the bus for outputting the output data and receiving the input data; a diagnostic instruction circuit for transmitting a diagnostic instruction signal for instructing start of a diagnosis; A bus interface control circuit that receives an instruction signal and sends out the output data having an appropriate data pattern to the input / output buffer; and receives the diagnostic instruction signal and outputs an output from the input / output buffer to the bus. And a bus output control circuit for controlling the bus cycle. Is characterized in that does not output the start signal to enable the bus.

Further, the bus interface circuit according to claim 4 is a bus interface circuit for performing a diagnosis by comparing output data output to a bus of an information processing device with input data received from the bus. A diagnostic instruction circuit connected to the bus interface circuit, wherein the diagnostic instruction circuit transmits a diagnostic instruction signal for instructing a start of diagnosis for each device connected to the bus; Second means for transmitting a diagnostic monitoring signal notifying that any of the devices is being diagnosed to all the devices connected to the bus, wherein the bus interface circuit comprises: An input / output buffer connected to the input / output port for outputting the output data and receiving the input data; A bus interface control circuit for sending the output data having the input signal to the input / output buffer, and a bus input for receiving the diagnostic monitoring signal from the diagnostic instruction circuit and controlling an input from the bus to the input / output buffer. A control circuit, wherein the bus input control circuit, when not receiving the diagnostic instruction signal from the diagnostic instruction circuit, receives the diagnostic monitoring signal and invalidates all inputs from the bus. It is characterized by doing.

Further, the bus interface circuit according to a fifth aspect is a bus interface circuit for performing a diagnosis by comparing output data output to a bus of an information processing device with input data received from the bus. The input / output buffer connected to the bus for outputting the output data and receiving the input data, and transmitting a diagnosis instruction signal for instructing start of diagnosis, and starting diagnosis. A diagnostic instruction circuit that sends a diagnostic notification signal to notify all the devices connected to the bus via a diagnostic notification bus, and receives the diagnostic instruction signal, and outputs the output data having an appropriate data pattern. A bus interface control circuit for transmitting the signal to the input / output buffer; A bus input control circuit that controls input from the bus to the input / output buffer, wherein the bus input control circuit does not receive the diagnostic instruction signal from the diagnostic instruction circuit, Upon receiving the diagnostic notification signal, all inputs from the bus are invalidated.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bus interface circuit embodying a bus interface circuit diagnostic method according to the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a block diagram of a bus interface circuit embodying a method of diagnosing a bus interface unit according to an embodiment of the present invention, and FIG. 2 is a configuration of a main part connected to a control bus in the bus interface circuit shown in FIG. FIG. 3 is a block diagram showing the configuration. Note that the same reference numerals are assigned to the same portions as those of the above-described conventional technology, and the description is omitted or simplified. The bus 100 according to the present embodiment includes an address bus 101 for transmitting an address, a data bus 102 for transmitting data, and a control bus 103 for transmitting bus control data for controlling the bus. The bus interface circuit 104 that implements the bus interface circuit diagnostic method according to the present embodiment includes
I / O buffers 111, 112, and 113 for interfacing with 102 and 103, an address input register 114, an address output register 115, a data input register 116, a data output register 117, a bus control input register 118, a bus Control output register 11
9, a comparison circuit 120, 121, 122, a bus output control circuit 123, and a bus interface control circuit 124.
Diagnostic instruction circuit 125 and diagnostic result holding register 12
6 and an internal logic 127.

The address output to the address bus 101 is set in the address output register 115 from the internal logic 127 via the bus interface control circuit 124, and is set via the input / output buffer 111.
Output to The address input from the address bus 101 is stored in the address input register 114 through the input / output buffer 111. Data output register 11
7 stores data to be output to the data bus 102, and the data input register 116 stores data input from the data bus 102. The bus control output register 119 stores bus control data to be output to the control bus 103, and the bus control input register 118 stores bus control data input from the control bus 103. The diagnosis instruction circuit 125
An instruction signal for instructing the bus interface circuit 104 to start diagnosis is output to the bus interface control circuit 124 and the bus output control circuit 123. The bus interface control circuit 124 sets the data pattern of the diagnostic test data on the bus 100 in the address output register 115, the data output register 117, and the bus control output register 119. The bus output control circuit 123 controls each input / output buffer 1 based on an instruction signal from the diagnosis instruction circuit 125.
11 and 112, and instructs the input / output buffer 113 to output bus control data other than the signal for validating the bus cycle to the control bus 103.

The comparing circuit 120 compares the address stored in the address output register 115 output to the address bus 101 with the address input from the address bus 101 and stored in the address input register 114. Here, when the input / output buffer 111 is out of order, the comparison result becomes inconsistent, and information for notifying the fault of the bus interface circuit 104 is stored in the diagnosis result holding register 126. Similarly, the comparison circuit 121 compares the data in the data input register 116 with the data in the data output register 117. If the comparison results do not match, the comparison circuit 121 outputs the information notifying the failure of the bus interface circuit 104 to the diagnosis result holding register 126. To hold. Comparison circuit 1
Reference numeral 22 compares the bus control data of the bus control input register 118 with the bus control data of the bus control output register 119. If the comparison results do not match, information for notifying the failure of the bus interface circuit 104 is stored in the diagnosis result holding register. 126.

As shown in FIG. 2, the control bus 103 includes a command signal 201 indicating the type of a bus transaction issued to the bus 100, and which byte of a plurality of bytes constituting data transmitted on the data bus 102 It includes an enable signal 202 indicating validity, and a start signal 203 indicating the start of a bus transaction on the bus 100 and indicating that a valid bus cycle is started. Here, when an instruction signal instructing the start of diagnosis of the bus interface circuit 104 is sent from the diagnosis instruction circuit 125 to the bus output control circuit 123, the bus output control circuit 123 outputs the command signal 201 from the command output register 211 and , Enable output register 21
4 to output the enable signal 202. The output of the start signal 203 from the start output register 216 is not instructed.

The bus interface circuit 10 embodying the bus interface circuit diagnostic method according to the present embodiment.
4 has the above-described configuration. Next, the operation of the bus interface circuit diagnostic method in the bus interface circuit 104, particularly, the operation when performing diagnosis on the EISA bus will be described with reference to FIGS. . FIG. 3 is a timing chart at the time of diagnosing the EISA bus. Here, the LA <31: 2> signal corresponds to an address on the address bus 101, and the D <31: 0> signal.
> Signal corresponds to data on the data bus 102, and other signals, that is, W_R signal, M_IO signal, BE
The <3: 0> signal and the START signal correspond to signals on the control bus 103. That is, the command signal 201 is W_
The enable signal 20 corresponding to the R signal and the M_IO signal
2 corresponds to the BE <3: 0> signal, and the start signal 203
Corresponds to the START signal.

As shown in FIG. 3, first, the bus interface circuit 104 outputs an MREQ signal to the arbitration circuit of the bus 100 in order to request the right to use the bus 100 in the T0 cycle, and the arbitration circuit in the T2 cycle. MA from
Upon receiving the CK signal, use of the bus 100 is permitted. After obtaining the right to use the bus 100, in a diagnostic cycle consisting of three cycles from T3 to T5, the bus interface circuit 104 outputs a START signal under the control of the bus output control circuit 123 without outputting a START signal. Each signal other than the START signal, that is, the W_R signal, the M_IO signal, and the BE <3: 0> signal is transmitted to the control bus 10.
3 and LA <3 on the address bus 102.
1: 2> signal, and D <31:
0> output signal. Here, for each of the BE <3: 0> signal, the LA <31: 2> signal, and the D <31: 0> signal, diagnostic data of a plurality of patterns, for example, data of all “0” or all of Is output as "1". Next, the bus interface circuit 104 invalidates the MREQ signal in the T6 cycle after completion of the diagnosis, and
When the bus 100 is released in the cycle, a series of diagnostic processing ends.

A bus interface circuit 10 embodying the bus interface circuit diagnostic method according to the present embodiment.
According to No. 4, even after the MACK signal is output and the right to use the bus 100 is obtained, the START signal is not output under the control of the bus output control circuit 123.
Does not recognize that the bus cycle of the bus 100 has started, and does not take in the data on the bus 100. Therefore, a free data pattern is set for each signal other than the START signal, and the bus 1
00, and various diagnostics can be performed on the bus interface circuit 104 by a signal of a free data pattern, and it is possible to prevent a failure from being overlooked. Further, even if a failure occurs in the bus interface circuit 104 and, for example, unexpected data is output on the bus 100, data on the bus 100 is not input to other devices.
It does not adversely affect other devices connected to the device, and does not execute meaningless bus transactions on other devices to destroy data of other devices. Further, since the diagnostic cycle can be continued until the bus interface circuit 104 releases the bus 100, the diagnosis of the bus interface circuit 104 can be efficiently executed.

In this embodiment, the bus 10
Although the EISA bus has been described as 0, the present invention is not limited to this, and other standards such as PCI (Peripheral Component
Interconnect) bus. In this case, EI
The START signal of the SA bus is the FRAME of the PCI bus.
(Cycle frame) signal. In the present embodiment, the address bus 101 and the data bus 1
02 is separate from, but not limited to, an address / data shared bus using a common signal line for address and data.

Next, a first modification of the bus interface circuit which embodies the bus interface circuit diagnostic method according to the present embodiment will be described with reference to FIG.
FIG. 4 is a block diagram of a bus interface circuit 501 that embodies a bus interface circuit diagnostic method according to a first modification of the present embodiment. The same parts as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted or simplified. As shown in FIG. 4, the bus interface device 501 includes input / output buffers 111, 112, and 113.
, An address input register 114, an address output register 115, a data input register 116, a data output register 117, a bus control input register 118,
A bus control output register 119 and comparison circuits 120 and 12
1, 122 and a bus interface control circuit 124
, Diagnosis result holding register 126, and internal logic 127
And a bus input control circuit 502. Also, one diagnostic instruction circuit 503 is provided for the bus 100, and the diagnostic instruction circuit 503 is common to each device connected to the bus 100. Diagnosis instruction circuit 503
Transmits a diagnostic instruction signal for instructing the start of diagnosis to each device connected to the bus 100 via a diagnostic instruction signal line 511 provided for each device, and is shared by each device. A diagnostic monitoring signal for notifying that any device is being diagnosed via the diagnostic monitoring signal line 512 is transmitted to the bus 10.
Notify each device connected to “0”.

The bus input control circuit 502 receives the diagnosis instruction signal from the diagnosis instruction signal line 511,
When it is detected that the diagnosis has been started in any of the devices by the diagnosis monitoring signal from the diagnosis monitoring signal line 512, the input buffers 111, 112, and 113 transmit the signals from the address bus 101, the data bus 102, and the control bus 103, respectively. Disable input of. On the other hand, when the diagnosis of itself, that is, the bus interface device 501 is performed by the diagnosis instruction signal from the diagnosis instruction signal 511, the input from each of the buses 101, 102, and 103 is made valid. In this case, the input from each of the buses 101, 102, and 103 to each of the input buffers 111, 112, and 113 is performed by the diagnosis instruction circuit 5
03, the bus input control circuit 50
2 can output a start signal for validating a bus cycle to the start signal line 203, and diagnosis including the start signal can be performed.

Next, a second modification of the bus interface circuit which embodies the bus interface circuit diagnosis method according to the present embodiment will be described with reference to FIG.
FIG. 5 is a block diagram of a bus interface circuit 601 that embodies a bus interface circuit diagnosis method according to a second modification of the present embodiment. The same parts as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted or simplified. As shown in FIG. 5, the bus interface circuit 601 includes input / output buffers 111, 112, 113,
602, an address input register 114, an address output register 115, a data input register 116, a data output register 117, and a bus control input register 11
8, the bus control output register 119, and the comparison circuit 12
0, 121, 122, bus interface control circuit 124, diagnosis instruction circuit 125, diagnosis result holding register 126, internal logic 127, bus input control circuit 60
And 3. The bus 605 includes an address bus 101, a data bus 102, and a control bus 103.
And a diagnosis notification bus 606.

When the diagnosis instructing circuit 125 instructs the start of the diagnosis of the bus interface circuit 601, the bus interface circuit 601 receives an input signal to notify another device that the bus interface circuit 601 is under diagnosis. Diagnostic notification bus 60 via output buffer 602
6 outputs a diagnosis notification signal. Bus input control circuit 603
When the diagnostic notification signal is received from the diagnostic notification bus 606 via the input / output buffer 602 when the diagnostic instruction signal from the diagnostic instruction circuit 125 is not received,
Recognizes that another device connected to
In each of the input buffers 111, 112, and 113, the input from each of the address bus 101, the data bus 102, and the control bus 103 is invalidated. On the other hand, according to the instruction from the diagnosis instruction circuit 125, when the bus interface device 601 itself is performing the diagnosis, the bus input control circuit 603 validates the input from each of the buses 101, 102, and 103. In this case, a diagnosis instruction signal for performing a diagnosis and a diagnosis monitoring signal for notifying that any device is performing a diagnosis are provided by a diagnosis notification bus 606 including one signal line.
Therefore, even a general-purpose bus such as an EISA bus or a PCI bus can be connected to the diagnostic notification bus 606 by using one unused pin, for example. The inputs from the buses 101, 102, and 103 to the input buffers 111, 112, and 113 are controlled by the diagnostic notification signal.
Reference numeral 03 can output a start signal 203 for validating a bus cycle, and diagnosis including the start signal 203 can be performed.

[0025]

As described above, according to the bus interface circuit diagnosing method of the first aspect of the present invention, since the start signal for validating the bus cycle is not output to the bus at the time of diagnosis, the bus interface circuit is connected to the bus. Other devices do not recognize that the bus cycle of the bus has started, and do not take in data on the bus. As a result, a free data pattern can be set for the output data to be output to the bus without adversely affecting other devices connected to the bus, and a failure can be overlooked by performing various diagnoses. Can be prevented. Further, since the self-diagnosis can be continued until the bus interface circuit releases the bus, the diagnosis can be performed efficiently. Further, according to the bus interface circuit diagnosis method of the present invention, when any of the devices connected to the bus does not receive the diagnosis instruction signal for instructing the start of diagnosis from the diagnosis instruction circuit, Upon receiving a notification signal notifying that the diagnosis is being performed, all inputs from the bus are invalidated, so that devices other than the device being diagnosed do not take in input data from the bus. As a result, a free data pattern can be set for output data to be output to the bus without adversely affecting other devices connected to the bus. In addition, in this case, a free data pattern can be set for the start signal that makes the bus cycle valid, and diagnosis can be performed. By performing various diagnoses, it is possible to prevent failures from being overlooked Becomes

According to the bus interface circuit of the third aspect, there is provided a bus output control circuit for controlling an output from the input / output buffer to the bus when a diagnostic instruction signal is received from the diagnostic instruction circuit, During the diagnosis, control is performed so that the start signal that enables the bus cycle among the bus control signals is not output to the bus, so that other devices connected to the bus do not recognize that the bus cycle of the bus has started. No input data is taken in from the bus. As a result, a free data pattern can be set for the output data to be output to the bus without adversely affecting other devices connected to the bus, and a failure can be overlooked by performing various diagnoses. Can be prevented. According to the bus interface circuit of the fourth aspect, a diagnosis instruction circuit is provided outside the bus interface circuit, and the diagnosis instruction circuit individually instructs start of diagnosis for each device connected to the bus. A diagnostic instruction signal is transmitted, and a diagnostic monitoring signal notifying that any of the devices connected to the bus is performing a diagnosis is transmitted to all the devices connected to the bus. Here, the bus input control circuit of the bus interface circuit is
If a diagnostic monitoring signal is received without receiving a diagnostic instruction signal from the diagnostic instruction circuit, all inputs from the bus will be invalidated, so devices other than the device under diagnosis must take input data from the bus. There is no. As a result, a free data pattern can be set for output data to be output to the bus without adversely affecting other devices connected to the bus. Also, in this case, diagnosis can be performed by setting a free data pattern even for the start signal that enables the bus cycle, and it is possible to prevent failures from being overlooked by performing various diagnosis. Becomes

According to the bus interface circuit of the present invention, the diagnostic instruction circuit for transmitting a diagnostic notification signal for notifying the start of diagnosis to all devices connected to the bus via the diagnostic notification bus is provided. The bus input control circuit of the bus interface circuit is provided with a bus input control circuit that, when not receiving a diagnostic instruction signal from the diagnostic instruction circuit, receives a diagnostic notification signal and invalidates all inputs from the bus. A free data pattern can be set for output data including a start signal that enables a bus cycle without adversely affecting other devices connected to the Can be prevented from being overlooked. Further, in this case, since the diagnostic notification signal is transmitted via the diagnostic notification bus, there is no need to secure a transmission path connecting the diagnostic instruction circuit and the device for each device connected to the bus. A general-purpose bus such as a bus or a PCI bus can be connected to the diagnostic notification bus using one unused pin.
It can be easily implemented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a bus interface device embodying a bus interface unit diagnosis method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing in detail a configuration of a main part connected to a control bus in the bus interface device shown in FIG.

FIG. 3 is a timing chart when an EISA bus is diagnosed by the bus interface device shown in FIG. 1;

FIG. 4 is a block diagram of a bus interface circuit embodying a bus interface circuit diagnostic method according to a first modification of the embodiment.

FIG. 5 is a block diagram of a bus interface circuit embodying a bus interface circuit diagnostic method according to a second modification of the embodiment.

FIG. 6 is a block diagram of a bus interface circuit that implements a conventional bus interface circuit diagnostic method.

FIG. 7 is a timing chart when diagnosing an EISA bus by a conventional bus interface circuit diagnostic method.

[Explanation of symbols]

 Reference Signs List 100 bus 101 address bus 102 data bus 103 control bus 104 bus interface device 111, 112, 113, 602 input / output buffer 114 address input register 115 address output register 116 data input register 117 data output register 118 bus control input register 119 bus control output Registers 120, 121, 122 Comparison circuit 123 Bus output control circuit 124 Bus interface control circuit 125 Diagnosis instruction circuit 126 Diagnosis result holding register 127 Internal logic 201 Command signal 202 Enable signal 203 Start signal 211 Command input register 212 Command output register 213 Enable input Register 214 Enable output register 215 Start input register 216 Star Output register

Claims (5)

[Claims] 1. A bus interface circuit diagnostic method for diagnosing by comparing output data output to a bus of an information processing device with input data received from the bus, comprising: a diagnostic instruction for instructing a start of a diagnostic; A bus interface circuit diagnostic method, comprising: not receiving a start signal for validating a bus cycle to the bus when receiving the signal and outputting the output data having an appropriate data pattern to the bus. 2. A bus interface circuit diagnosing method for performing a diagnosis by comparing output data output to a bus of an information processing device with input data received from the bus, comprising: First processing for transmitting a diagnosis instruction signal for instructing start of diagnosis, and transmitting a notification signal for notifying that any of the devices is being diagnosed to all the devices connected to the bus A second process of receiving the diagnosis instruction signal and outputting the output data having an appropriate data pattern to the bus, and a third process of receiving the diagnosis instruction signal. A bus interface circuit diagnostic method, comprising: upon receiving a notification signal, invalidating all inputs from the bus. 3. A bus interface circuit for performing diagnosis by comparing output data output to a bus of an information processing device with input data received from the bus, wherein the bus interface circuit is connected to the bus. An input / output buffer for outputting the output data and receiving the input data, a diagnostic instruction circuit for transmitting a diagnostic instruction signal for instructing the start of a diagnosis, and receiving the diagnostic instruction signal to obtain an appropriate data pattern. A bus interface control circuit that sends the output data to the input / output buffer, and a bus output control circuit that receives the diagnostic instruction signal and controls output from the input / output buffer to the bus. At the time of diagnosis, the bus output control circuit does not output a start signal for validating a bus cycle to the bus. Bus interface circuit according to claim. 4. A bus interface circuit for performing a diagnosis by comparing output data output to a bus of an information processing device with input data received from the bus, wherein the bus interface circuit includes a diagnosis instruction circuit. Being connected, the diagnostic instruction circuit is configured to transmit a diagnostic instruction signal for instructing start of diagnosis for each of the devices connected to the bus, and one of the devices is performing a diagnosis. A second means for transmitting a diagnostic monitoring signal notifying the above to all the devices connected to the bus, wherein the bus interface circuit is connected to the bus and outputs the output data and the output data. An input / output buffer that receives input data, and receives the diagnostic instruction signal, and outputs the output data having an appropriate data pattern to the input / output buffer. And a bus interface control circuit to be out,
A bus input control circuit that receives the diagnosis monitoring signal from the diagnosis instruction circuit and controls an input from the bus to the input / output buffer. A bus interface circuit that invalidates all inputs from the bus when the diagnostic monitoring signal is received without receiving a diagnostic instruction signal. 5. A bus interface circuit for performing diagnosis by comparing output data output to a bus of an information processing device with input data received from the bus, wherein the bus interface circuit is connected to the bus. An input / output buffer for outputting the output data and receiving the input data, and transmitting a diagnosis instruction signal for instructing start of diagnosis,
A diagnostic instruction circuit for transmitting a diagnostic notification signal for notifying the start of diagnosis to all the devices connected to the bus via a diagnostic notification bus; and receiving the diagnostic instruction signal and forming an appropriate data pattern. A bus interface control circuit that sends the output data to the input / output buffer, a bus input control circuit that receives the diagnosis notification signal from the diagnosis notification bus, and controls input from the bus to the input / output buffer; When the bus input control circuit receives the diagnosis notification signal while not receiving the diagnosis instruction signal from the diagnosis instruction circuit, the bus input control circuit invalidates all inputs from the bus. Bus interface circuit characterized.