JP2000347627A - Liquid crystal display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disturbance of a screen by eliminating dispersion of electric fields of each pixel when a power is off. SOLUTION: When a DCG is on, each of CMOS type FETs 80 turns on sequentially, and each of CMOS type FETs 90 turns off simultaneously. Thus, a video signal is supplied to all data lines 20 from external. A scanning line 30 turns on by a single line sequentially and a general display operation is executed. When the DCG is off, each of the CMOS type FETs 80 turns off simultaneously, and each of the CMOS type FETs 90 turns on simultaneously. Thus, a video signal from external to all the data lines is completely interrupted. Instead, a common signal (Vcom) is supplied and all of the gate lines 30 turn on. Therefore, potential difference of all of the pixels is eliminated and disturbance of an image when the power is off can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having improved screen quality when power is turned off.

[0002]

2. Description of the Related Art Conventionally, a plurality of pixel driving elements are arranged corresponding to liquid crystal pixels, a plurality of data lines connected to each pixel driving element arranged in a vertical scanning direction, and a plurality of pixel driving elements are arranged in a horizontal scanning direction. A plurality of scan lines connected to the pixel drive element, and sequentially supplies a vertical synchronization signal to the scan line and a video signal to the data line, thereby driving the pixel drive element and driving the liquid crystal pixel. There is known a liquid crystal display device for controlling the speed.

[0003]

In the above-described conventional liquid crystal display device, when a DC voltage is applied to the liquid crystal, the specific resistance of the liquid crystal is degraded. Common voltage V applied to electrodes
com. Therefore, in each pixel driven by the liquid crystal, there are a pixel that holds a high-level potential in AC driving and a pixel that holds a low-level potential. Therefore, when the power is turned off, the voltage (Vcom) of the counter electrode gradually decreases to Vss. At this time, the pixel holding the high-level potential and the low-level potential are held. A difference is generated in the DC electric field between the pixels that have been used, and the image is disturbed due to the variation in the DC electric field. This disturbance also depends on the leak characteristics of each pixel when the power is turned off. If the characteristics vary, the manner of the disturbance becomes random, and the disturbance on the screen becomes more severe.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a liquid crystal display device capable of eliminating variations in the electric field of each pixel when the power is turned off and preventing screen disturbance.

[0005]

In order to achieve the above object, a liquid crystal display device according to the present invention has a plurality of pixel driving elements arranged in a matrix corresponding to liquid crystal pixels and arranged in a vertical scanning direction. A plurality of data lines connected to each pixel driving element, and a plurality of scan lines connected to each pixel driving element arranged in the horizontal scanning direction,
A liquid crystal display device that controls a liquid crystal pixel by driving the pixel driving element by supplying a video signal to the data line while sequentially supplying a vertical synchronization signal to the scan line. And a collective control means for simultaneously turning on all of the scan lines, and immediately before turning off the power, the collective control means sets the potential of the pixel driving element corresponding to each pixel. It is characterized by common control.

In the liquid crystal display device of the present invention, the collective control means supplies a common signal to all of the data lines and simultaneously turns on all of the scan lines. Thereby, the potentials of the respective pixel driving elements can be unified by the common signal. Therefore, by controlling the potentials of the pixel driving elements corresponding to the respective pixels in common just before the power is turned off by the collective control means, it is possible to eliminate the variation in the electric field of each pixel when the power is turned off and prevent the screen from being disturbed. .

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the liquid crystal display device according to the present invention will be described. FIG. 1 is a block diagram showing a configuration of an active matrix type liquid crystal display device according to an embodiment of the present invention. In this liquid crystal display device, a plurality of thin film transistors (TFTs) as pixel driving elements
10, a plurality of data lines 20, a plurality of scan lines (gate lines) 30, and a vertical shift register (V
−S / R) 40 and a plurality of NAs as the first gate element
ND gate 50 and horizontal shift register (HS / R)
60, a plurality of NAND gates 70 as second gate elements, a plurality of CMOS type FETs 80 as video signal supply elements, and a plurality of CMOs as common signal supply elements.
And an S-type FET 90.

Each TFT 10 is arranged in a matrix corresponding to a liquid crystal pixel, each source terminal of each TFT 10 in the vertical scanning direction is connected by each data line 20, and each scanning line 30 is connected by each scanning line 30 in the horizontal scanning direction. Each gate terminal of each TFT 10 is connected. The drain terminal of each TFT 10 is connected to a counter electrode (not shown) via a liquid crystal (not shown).

The vertical shift register 40 is connected to each scan line 30 via a NAND gate 50, and sequentially supplies a vertical synchronization signal to each scan line 30. Each shift output of the vertical shift register 40 is input to one input terminal of each NAND gate 50, and an external control signal (DCG) from an external input terminal (not shown) is input to the other input terminal. I have. The output terminal of each NAND gate 50 is connected to each scan line 30. With such a configuration, the gate terminal of each TFT 10 is scanned in the vertical scanning direction by the vertical synchronization signal, and each TFT 10 is sequentially turned on in the vertical scanning direction.
Each CMOS type FET 80 is connected to each data line 20.
, And selectively supplies a video signal to each data line 20.

The horizontal shift register 60 stores each CM.
It is connected to the OS type FET 80 via the NAND gate 70, and sequentially supplies a horizontal synchronization signal to each CMOS type FET 80. Each shift output of the horizontal shift register 60 is input to one input terminal of each NAND gate 70, and an external control signal (D) from an external input terminal is input to the other input terminal.
CG) has been entered. Each NAND gate 70
Is input to one gate terminal (inverting terminal) of each CMOS FET 80 and connected to the other gate terminal of each CMOS FET 80 via an inverter 82 provided corresponding to each CMOS FET 80. Is entered. A video signal is supplied to a source terminal of each CMOS FET 80. With such a configuration, each CMOS type FET 80 is sequentially turned on by the horizontal synchronization signal at the source terminal of each TFT 10, and each TFT 1
The video signal is supplied to the source terminal of 0.

On the other hand, an external control signal (DCG) from an external input terminal is input to one gate terminal (inverting terminal) of the CMOS type FET 90, and an inverted signal of the external control signal (DCG) is input to the other gate terminal. Has been entered. Also,
A common signal (in this example, Vcom) is input to the source terminal of the CMOS type FET 90. With such a configuration, a signal of a common potential (Vcom in this example) can be supplied to the source terminal of each TFT 10.

Next, the operation of the liquid crystal display device having the above configuration will be described. FIG. 2 is a timing chart showing the on / off operation of the power supply and the on / off operation of the DCG in this example. FIG. 3 is a block diagram showing an operation of the liquid crystal display device of the present example at the time of normal driving, and FIG. 4 is a block diagram showing an operation immediately before power-off of the liquid crystal display device of the present example.

In the liquid crystal display of this embodiment, the following control is performed by using the DCG signal from the external input terminal to drive the liquid crystal display. That is, in this example, DCG
The signal constitutes a control signal by the collective control means. The DCG signal has a certain time lag with respect to the power on / off timing.
The shift time is determined based on the delay of the gate line and the time required for writing to each pixel, and is usually about 5 μsec. That is, as shown in FIG. 2, the DCG signal is applied for about 5 μs
ON with a delay of ec, and about 5μ
It turns off early.

When the DCG signal is logic "H" = ON, as shown in FIG.
Are sequentially turned on, and the switches of the respective CMOS FETs 90 are simultaneously turned off. Therefore, a video signal from the outside is supplied to all data lines 20.
The scan lines 30 are sequentially turned on for each line. In this way, a normal display operation is performed.

Next, when the DCG signal is in the state of logic "L" = OFF, as shown in FIG. 4, the switches of each CMOS type FET 80 are turned off all at once, and the switches of each CMOS type FET 90 are turned on all at once. . Therefore, in this state, the external video signal is completely cut off for all the data lines 20, and another common signal (Vcom in this example) is supplied instead. Also, all the gate lines 30 are turned on. As a result, a common potential can be supplied to all the pixels, so that there is no potential difference between the odd-numbered lines and the even-numbered lines, and the disturbance of the image when the power is turned off can be eliminated. However, the DCG signal at this time is, as shown in FIG. 2, immediately before the power is turned off (about 5 μsec before in this example).
When the power is turned on, on the contrary, immediately after the power is turned on (in this example, about 5 μsec
After) the DCG signal must be turned on. It is assumed that such timing control is performed by, for example, the operation of a CPU that controls the entire liquid crystal display device.

When the DCG signal is set to logic "L", the potential of the common signal supplied to each pixel is CMO
Vdd to Vss, which is the output voltage range of the S-type FET
It is sufficient that the potential is within the range described above. In the above description, the DCG signal and the Vcom signal are used to match the potential of each pixel when the power is turned off. However, the control may be performed by using another signal having the same function.
In addition, each CMOS FE for obtaining the above operation
Regarding the specific configuration of the T80, 90, the NAND gates 50, 70, etc., a configuration combining other switch elements and gate elements that can obtain the above-described functions may be adopted.

[0017]

As described above, in the liquid crystal display device of the present invention, a common signal is supplied to all of the data lines, and collective control means for simultaneously turning on all of the scan lines is provided. Immediately before the power is turned off, the collective control means commonly controls the potentials of the pixel driving elements corresponding to the respective pixels. Therefore, according to the present invention, by immediately controlling the potential of the pixel driving element corresponding to each pixel immediately before the power is turned off, it is possible to eliminate the variation in the electric field of each pixel when the power is turned off and prevent the screen from being disturbed. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an active matrix type liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a power on / off operation of the liquid crystal display device shown in FIG.
5 is a timing chart showing an off operation and an on / off operation of DCG.

FIG. 3 is a block diagram showing an operation during normal driving of the liquid crystal display device shown in FIG.

FIG. 4 is a block diagram showing an operation of the liquid crystal display device shown in FIG. 1 immediately before power is turned off.

[Explanation of symbols]

10 thin film transistor (TFT), 20 data line, 30 scan line, 40 vertical shift register, 50, 70 NAND gate, 60 horizontal shift register, 80, 90 CMOS FET .

Continued on the front page F term (reference) 2H093 NA16 NA43 NC10 NC12 ND05 ND35 5C006 AA01 AA02 AA11 AC24 AF59 AF67 BB16 BC03 BC11 BF26 BF34 FA22 5C080 AA10 BB05 DD01 DD30 EE26 FF11 GG02 GG12 JJ02 JJ03

Claims (10)

[Claims] A plurality of pixel driving elements arranged in a matrix corresponding to the liquid crystal pixels; a plurality of data lines connected to each pixel driving element arranged in a vertical scanning direction; and a plurality of data lines arranged in a horizontal scanning direction. A plurality of scan lines connected to each of the pixel driving elements, and sequentially supplies a vertical synchronizing signal to the scan lines and supplies a video signal to the data lines to drive the pixel driving elements. A liquid crystal display device that controls a liquid crystal pixel by supplying a common signal to all of the data lines, and collectively controlling all of the scan lines at a time. Immediately before, the collective control means commonly controls a potential of a pixel driving element corresponding to each pixel. 2. A vertical shift register for supplying a vertical synchronization signal to a scan line of the pixel driving element, and a vertical shift register provided in correspondence with a data line of the pixel driving element,
A plurality of video signal supply elements for supplying a video signal to each data line, a horizontal shift register for supplying a horizontal synchronization signal to each of the video signal supply elements, and controlling the on / off of each of the video signal supply elements in turn; A plurality of common signal supply elements provided corresponding to the data lines of the pixel driving transistors and supplying a common signal to each data line; and the vertical synchronization signal provided between the vertical shift register and the scan line. And a plurality of second gates provided between the horizontal shift register and the video signal supply element, for controlling on / off of the supply of the horizontal synchronization signal. And the collective control means performs on / off control of the first and second gate elements and the common signal supply element collectively. A means for supplying a control signal, the liquid crystal display device according to claim 1, wherein a. 3. The liquid crystal display device according to claim 1, wherein said collective control means is an external input means for externally inputting a control signal. 4. The liquid crystal display device according to claim 1, wherein the common signal is a common voltage signal supplied to a counter electrode that is disposed to face the pixel driving element via a liquid crystal. 5. The liquid crystal display device according to claim 1, wherein the pixel driving element is a thin film transistor. 6. The first and second gate elements are NAND gates, wherein one input terminal receives a synchronization signal from a shift register and the other input terminal receives the control signal. The liquid crystal display device according to claim 2. 7. The common signal supply element is a CMOS type FE.
T, the common signal is input to a source terminal of the CMOS type FET, the control signal is input to one gate terminal, and an inverted signal of the control signal is input to the other gate terminal. The liquid crystal display device according to claim 2, wherein 8. The video signal supply element is a CMOS type F
ET and an inverter, the CMOS type FET
3. The video signal is input to a source terminal of the second input terminal, the control signal is input to one gate terminal, and a signal obtained by inverting the control signal by an inverter is input to the other gate terminal. Liquid crystal display device. 9. Immediately after the power is turned off, the collective control means commonly controls on the potentials of the pixel driving elements corresponding to the respective pixels. Immediately before the power is turned off, the collective control means controls the potential of each pixel. 2. The liquid crystal display device according to claim 1, wherein the potentials of the pixel driving elements are turned off in common. 10. A predetermined minute time after the power is turned off,
The collective control means commonly controls the potentials of the pixel drive elements corresponding to the respective pixels to be on, and a predetermined short time before the power is turned off, the collective control means commonly controls the potentials of the pixel drive elements corresponding to the respective pixels. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is turned off.