JP2000347598A - Active matrix type semiconductor display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of elements such as TFT, and reduce power consumption by dividing a counter electrode into two, applying different potentials to the two respective counter electrodes, and mutually inverse-driving them. SOLUTION: When a 1st line G1 scanning period starts, an image signal having a positive potential is sequentially inputted to the odd-numbered source signal lines S1, S3,..., and an image signal having a negative potential is sequentially inputted to the even-numbered source signal lines S2, S4,..., and the source lines are inverse-driven. An image signal is sequentially written in pixel TFTs (1, 1)-(1, n). At this time, the negative potential is applied to a counter electrode 1 corresponding to the odd-numbered source signal line, and the positive potential is applied to a counter electrode 2 corresponding to the even-numbered source signal line. In the 2nd frame, the potential of the image signal to be supplied to each source signal line and that of the counter electrode are both inverted from those in the 1st frame in polarity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix type semiconductor display device. In particular, it relates to an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, an active matrix type semiconductor display device has become popular in the market as an FPD (flat panel display). Among them, active matrix liquid crystal display devices have been widely used as display devices for personal computers. In addition, large-screen active-matrix liquid crystal display devices are being used not only for notebook personal computers but also for desktop personal computers.

An active matrix type liquid crystal display device used for a personal computer is required to be able to display a plurality of information at a time in addition to a large screen. Therefore, an active matrix type liquid crystal display device capable of full-color display with a large screen, high definition and high image quality has been demanded.

[0004] Among active matrix type liquid crystal display devices, a TN (twisted nematic) liquid crystal display device using a nematic liquid crystal is most frequently marketed. Here, a schematic configuration diagram of a conventional active matrix TN liquid crystal display device is shown in FIG. In FIG. 20, 3001
Denotes a source signal line driving circuit, 3002 denotes a gate signal line driving circuit, and 3003 denotes an active matrix circuit. The active matrix circuit 3003 includes a plurality of pixel TFTs.
Reference numeral 3004 denotes a circuit arranged in a matrix. A gate signal line and a source signal line are connected to a gate electrode and a source electrode of each pixel TFT 3004, respectively. A pixel electrode is connected to a drain electrode of the pixel TFT. Generally, a substrate having a drive circuit and an active matrix circuit is called an active matrix substrate. A liquid crystal 3006 is sandwiched between an active matrix substrate and a counter substrate (not shown) having a counter electrode formed on one surface.

A selection signal is sequentially supplied from the gate signal line driving circuit to the gate signal line. All pixel TFTs connected to the gate signal line to which the selection signal is supplied are ON
The source signal line driving circuit 3001 sequentially supplies image signals to the source signal lines, thereby
(That is, the liquid crystal and the storage capacitor) are written with the image signal.

[0006]

In general, when a material having a history with respect to an applied voltage such as a nematic liquid crystal is used, an electric field in a reverse direction is applied to the liquid crystal at regular intervals in order to prevent "burn-in" on the screen. Is performed. This driving method is called an inversion driving method. Here, the "history" with respect to the applied voltage means that the change in the electro-optical characteristics of the liquid crystal when a voltage is applied does not match the change in the electro-optical characteristics of the liquid crystal when the voltage is removed. . Further, “burn-in” on the screen refers to display disorder caused by this history.

In order to prevent the above-mentioned "burn-in" on the screen,
A driving method called an inversion driving method is often used,
Among the inversion driving methods, a method of inverting the direction of the electric field applied to the liquid crystal every time the display screen is rewritten is called a frame inversion method, and is a driving method that can be easily performed among the inversion driving methods. The frame inversion method has been most often used in an active matrix type liquid crystal display device.

In recent years, with the demand for a high-resolution, high-definition active matrix type liquid crystal display device, the problem of the frame inversion method has emerged. In order to realize a high-resolution and high-definition active matrix liquid crystal display device, it is necessary to shorten a period for charging the liquid crystal and the storage capacitor with an image signal. Due to the performance of the driving circuit, there is a limit in shortening the charging period, and a time division driving method has been newly adopted. However, when the liquid crystal is driven by the frame inversion method, when the time-division driving method is used, a so-called crosstalk phenomenon that lowers the quality of the display screen due to parasitic capacitance that cannot be avoided in design may occur.

In order to reduce the crosstalk phenomenon, a gate line (row) inversion method for inverting the direction of an electric field applied to the liquid crystal with respect to an image signal for every one to several rows, A source line (column) inversion method, which is a method of inverting the direction of the electric field applied to the liquid crystal with respect to the image signal, has begun to be adopted.

[0010] In particular, active matrix type liquid crystal display devices for notebook personal computers are required to have low power consumption. However, in the case of using any of the above three inversion driving methods, a high-potential-side power supply and a low-potential-side power supply are prepared, and an image signal having a potential on the high-potential-side power supply and a potential on the low-potential-side power supply are used. It is necessary to create an image signal having For this reason, the difference between the high-potential-side power supply and the low-potential-side power supply of the drive circuit is about twice as large as that in the case where the inversion driving method is not used. As a result, the reliability of elements such as TFTs forming the driving circuit and the active matrix circuit is reduced, and the power consumption of the driving circuit is increased. In addition, when a higher-voltage power supply with a higher voltage is used as a part of the drive circuit, a booster circuit for converting a higher-voltage signal necessary for screen display is required.
As a result, there arises a problem that the area of the drive circuit becomes large.

[0011]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object the realization of an active matrix type semiconductor display device which eliminates the adverse effects of using the inversion driving method.

In the active matrix type semiconductor display device of the present invention, the opposing electrodes are divided into two, different potentials are respectively applied to the two opposing electrodes, and the two opposing electrodes are driven to invert each other. By doing so, the voltage of the image signal can be reduced, so that the voltage required for operating the driving circuit can be reduced. As a result, it is possible to improve the reliability of the elements such as the TFTs constituting the driving circuit and the active matrix circuit and to reduce the power consumption. Further, since the voltage of the timing pulse supplied from the driving circuit can be reduced, the boosting circuit can be omitted, and the area of the driving circuit can be reduced.

Therefore, in the active matrix type semiconductor display device of the present invention, addressing modes such as gate line (row) inversion driving, source line (column) inversion driving, and dot (point) inversion driving can be effectively adopted. The display screen can be prevented from deteriorating.

The configuration of the active matrix type semiconductor display device of the present invention will be described below.

According to the present invention, a source signal line driving circuit for supplying an image signal to a plurality of source signal lines, a gate signal line driving circuit for supplying a selection signal to a plurality of gate signal lines, a pixel TFT and the pixel TFT Pixels having pixel electrodes connected to the drain electrodes are arranged in a matrix, the source signal lines are connected to the source electrodes of the pixel TFTs, and the gate signal lines are connected to the gate electrodes of the pixel TFTs. An active matrix circuit, an active matrix circuit, two counter electrodes, and a display medium sandwiched between the pixel electrode and the counter electrode. Among the source signal lines, the pixels are arranged corresponding to the pixels corresponding to each source signal line. Corresponding potential of the image signal supplied to the source signal line to the opposite potential is an active matrix type semiconductor display device provided each of which is provided.

According to the present invention, a source signal line driving circuit for supplying an image signal to a plurality of source signal lines, a gate signal line driving circuit for supplying a selection signal to a plurality of gate signal lines, a pixel TFT, Pixels having pixel electrodes connected to the drain electrodes of the pixel TFTs are arranged in a matrix, the source signal lines are connected to the source electrodes of the pixel TFTs, and the gate signal lines are connected to the gate electrodes of the pixel TFTs. An active matrix type semiconductor display device including a connected active matrix circuit, two counter electrodes, and a display medium sandwiched between the pixel electrode and the counter electrode, wherein the two counter electrodes are: The plurality of source signal lines are respectively arranged corresponding to pixels corresponding to every two source signal lines, and The corresponding potential of the image signal supplied to the source signal line to the opposite potential is an active matrix type semiconductor display device provided each of which is provided.

According to the present invention, a source signal line driving circuit for supplying an image signal to a plurality of source signal lines, a gate signal line driving circuit for supplying a selection signal to a plurality of gate signal lines, a pixel TFT, Pixels having pixel electrodes connected to the drain electrodes of the pixel TFTs are arranged in a matrix, the source signal lines are connected to the source electrodes of the pixel TFTs, and the gate signal lines are connected to the gate electrodes of the pixel TFTs. An active matrix type semiconductor display device including a connected active matrix circuit, two counter electrodes, and a display medium sandwiched between the pixel electrode and the counter electrode, wherein the two counter electrodes are: Of the plurality of source signal lines, a plurality of source signal lines are arranged corresponding to pixels corresponding to z source signal lines. The corresponding potential of the image signal supplied to the source signal line to the opposite potential is an active matrix type semiconductor display device provided each of which is provided.

The display medium may be a liquid crystal.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The active matrix type semiconductor display device of the present invention will be described below with reference to embodiments. However, the following examples are merely some embodiments of the active matrix semiconductor display device of the present invention, and the active matrix semiconductor display device of the present invention is not limited to these examples.

[0020]

(Embodiment 1) In this embodiment, an active matrix type display device of the present invention will be described using an active matrix type liquid crystal display device using liquid crystal as a display medium.

Referring to FIG. FIG. 1 is a schematic configuration diagram of an active matrix type liquid crystal display device of the present embodiment. 101 is a source signal line drive circuit, 102 is a gate signal line drive circuit, and 103 is an active matrix circuit. The active matrix circuit 103 is a portion for displaying an image, and is configured by a plurality of pixels.
The active matrix type liquid crystal display device of this embodiment is
It has (m × n) pixels. Both n and m are natural numbers, and in this embodiment, n is an even number (m may be an even number or an odd number). For convenience of explanation, (1, 1,
1) to (m, n).

Each of the pixels (1, 1) to (m, n) has a pixel TFT 104. Each pixel TFT10
In FIG. 4, for convenience of description, the reference numerals assigned to the pixels are cited. That is, the pixel TFT in the pixel (1, 1)
Is described as a pixel TFT (1, 1).

The pixel TFT (1, 1), the pixel TFT (1,
2),..., A gate signal line G1 is connected to a gate electrode of the pixel TFT (1, n). The pixel T
FT (2, 1), pixel TFTs (2, 2),..., Pixel TFT (2, n) have gate signal lines G2
Is connected. Similarly, a gate signal line Gm is connected to the gate electrodes of the pixel TFTs (m, 1), (m, 2),..., And pixel TFTs (m, n).

The pixel TFT (1, 1), the pixel TFT
(2, 1),..., The source signal line S1 is connected to the source electrode of the pixel TFT (m, 1). Further, pixel TFTs (2, 1), pixel TFTs (2, 2),.
A source signal line S2 is connected to a source electrode of the pixel TFT (m, 2). Similarly, the pixel TFT (1,
n), pixel TFT (2, n),..., pixel TFT
The source signal line Sn is connected to the (m, n) source electrode.

The source signal line driving circuit 101 has a shift register circuit, a buffer circuit, a sampling circuit, and the like, and receives a clock signal, a start pulse, an image signal, and the like from the outside. Also, the gate signal line drive circuit 10
Reference numeral 2 includes a shift register circuit, a buffer circuit, and the like, and receives a clock signal, a start pulse, and the like from the outside. The source signal line driving circuit 101 includes a source signal line S
An image signal is supplied to 1 to Sn. The gate signal line drive circuit supplies a selection signal to the gate signal lines G1 to Gm.

All pixel TFTs (1, 1) to pixel TFT
A pixel electrode (not shown) is provided for the drain electrode of (m, n).
Is connected. On the counter substrate (not shown) side, a counter electrode 1 (not shown) and a counter electrode 2 (not shown) are formed. The counter electrode 1 is connected to the potential COM1. The counter electrode 2 is connected to the potential COM2. The counter electrode 1 and the counter electrode 2 do not have the same potential, and different potentials, more precisely, opposite potentials are supplied. The liquid crystal 106 is sandwiched between an active matrix substrate having a driving circuit and an active matrix circuit and a counter substrate. Also, 1
Reference numeral 07 denotes a storage capacitor connected to the drain electrode of each pixel TFT 104 and the common electrode 1 or the common electrode 2.

FIG. 2 is referred to in order to describe the active matrix type liquid crystal display device of this embodiment in more detail.
FIG. 2 schematically shows a portion of the active matrix circuit 103 in the schematic configuration diagram of the active matrix type liquid crystal display device of the present embodiment shown in FIG.

In FIG. 2, pixel TFTs (1, 1) to
The pixel TFT (m, n), the pixel electrode 105, the counter electrode 1 and the counter electrode 2 are particularly schematically shown. As shown in FIG. 2, in the active matrix type liquid crystal display device of the present embodiment, the opposing electrodes 1 and 2
It has a shape that fills the gap between each other. The counter electrode 1 is connected to the odd-numbered source signal lines (S1, S3,
.., Sn-1) connected to pixel TFTs (1, 1) to
(M, 1), (1, 3) to (m, 3), ..., (1,
n-1) to (m, n-1), and are arranged above the corresponding pixels. The counter electrode 1 is connected to odd-numbered source signal lines (S1, S3,..., Sn-
Pixel TFTs (1, 1) to (m, 1) connected to 1),
(1, 3)-(m, 3), ..., (1, n-1)-
Pixel electrode 105 connected to each of (m, n-1)
It can also be said that they are arranged at the upper part of them.
The counter electrode 2 is connected to even-numbered source signal lines (S2, S2).
4,..., Sn) connected to the pixel TFT (1, 2)
~ (M, 2), (1,4) ~ (m, 4), ...,
It is arranged corresponding to the pixel electrode 105 connected to each pixel having (1, n) to (m, n). The counter electrode 2 is connected to even-numbered source signal lines (S2, S2).
4,..., Sn) connected to the pixel TFT (1, 2)
~ (M, 2), (1,4) ~ (m, 4), ...,
It can be said that they are arranged corresponding to the pixel electrodes 105 connected to (1, n) to (m, n), respectively.

Therefore, the pixels (1, 1) to (m, 1), (1, 3) to (m,
3),..., (1, n−1) to (m, n−1), a voltage is applied by the pixel electrode 105 and the counter electrode 1. Pixels (1, 2) to (m, 2), (1, 4) to (1) corresponding to the even-numbered source signal lines.
A voltage is applied to the liquid crystal at (m, 4),..., (1, n) to (m, n) by the pixel electrode 105 and the counter electrode 2.

FIG. 3 is an enlarged view of the active matrix circuit portion of the active matrix type liquid crystal display device of the present embodiment. For convenience of explanation, the scale of the figure is different between the vertical and horizontal directions. According to FIG. 3, it is well understood that the opposing electrode 1 and the opposing electrode 2 are shaped so as to fill the gap therebetween. Note that, in FIG. 3, black portions indicate portions where the semiconductor active layer 106-1 and the source signal line are in contact with each other,
In addition, portions where the semiconductor active layer 106-1 and the pixel electrode 105 are in contact with each other are shown.

In this embodiment, the pixel TFT 1
04 has a L / W (channel length / channel width) of 4 μm ×
3 (triple gate) / 4 μm. The size of one pixel (length × width) was 144 μm × 48 μm. Further, the distance D of the gap formed between the counter electrode 1 and the counter electrode 2
Was set to D = 4.5 μm.

Here, a driving method of the active matrix type liquid crystal display device of this embodiment will be described. FIGS. 4 and 5 show drive timing charts of the active matrix type liquid crystal display device of the present embodiment.

First, reference is made to FIG. FIG. 4 shows a timing chart for displaying the first frame of the active matrix liquid crystal display device of the present embodiment. In this specification, a frame refers to a display of all pixels (pixels (1, 1) to (m, n)), and a frame scanning period refers to all pixels (pixels (1, 1) to (m). m, n))
Refers to a period required to write an image signal to the memory. A line refers to a pixel connected to one gate signal line, and a line scanning period refers to (1, 1) to (1, n).
Alternatively, it is a period required for writing an image signal to the pixels (2, 1) to (2, n) and the like.

CLK is a clock signal, and T1 to Tn are timing signals input to the analog switches of the source signal line drive circuit. S1 to Sn are source signal lines S1 to
An image signal input to Sn is shown, and G1 to Gn are selection signals input to the gate signal lines G1 to Gn. COM1 and COM2 indicate the potentials of the counter electrode 1 and the counter electrode 2, respectively.

Next, the circuit operation of the active matrix type liquid crystal display of this embodiment will be described. The clock signal is input to the shift register circuit of the source signal line driver circuit. The shift register circuit operates by a clock signal and a start pulse input at the beginning of a line scanning period, and generates timing signals (T1, T2,..., Tn). The timing signal is amplified by a buffer circuit or a level shifter circuit, and is sequentially input to an analog switch. An image signal input from the outside is sampled based on the timing signal input to the analog switch, and the corresponding source signal line (S1, S2,..., S
Output to n). Note that how the source signal line driving circuit generates the timing signal is arbitrary.

When the first line (G1) scanning period (period for writing a pixel corresponding to the gate signal line G1) starts, an image signal having a positive potential is sequentially supplied to the odd-numbered source signal lines. An image signal having a negative potential is supplied to the even-numbered source signal lines. Therefore, the writing of the image signal is sequentially performed on the pixel TFTs (1, 1) to (1, n) connected to G1, and the liquid crystal is driven. At this time, the counter electrode 1 corresponding to the odd-numbered source signal line
A negative potential is applied to (COM1), and a positive potential is applied to the counter electrode 2 (COM2) corresponding to the even-numbered source signal lines.

The pixel TFT (1,...) Connected to G1
When the writing of the image signal to 1) to (1, n) is completed,
Next, a second line (G2) scanning period is started, and an odd-numbered source signal line is supplied with an image signal having a positive potential, and an even-numbered source signal line is sequentially supplied with an image signal having a negative potential. Is supplied. Therefore, the image signal is sequentially written into the pixel TFTs (2, 1) to (2, n) connected to G2, and the liquid crystal is driven. At this time, the counter electrode 1 (COM1) corresponding to the odd-numbered source signal line
Is supplied with a negative potential, and a positive potential is supplied to the counter electrode 2 (COM2) corresponding to the even-numbered source signal line.

The pixel TFT (2, 2) connected to G2
When the writing of the image signal to 1) to (2, n) is completed,
Next, a third line (G3) scanning period starts, and an odd-numbered source signal line is sequentially supplied with an image signal having a positive potential, and an even-numbered source signal line is sequentially supplied with an image signal having a negative potential. Is supplied. Therefore, the writing of the image signal is sequentially performed on the pixel TFTs (3, 1) to (3, n) connected to G3, and the liquid crystal is driven. At this time, the counter electrode 1 (COM1) corresponding to the odd-numbered source signal line
Is supplied with a negative potential, and a positive potential is supplied to the counter electrode 2 (COM2) corresponding to the even-numbered source signal line.

The above operation is sequentially performed for all pixel TFTs in one frame (first to n-th lines). Therefore, the odd-numbered source signal lines (S1, S3, S5,..., Sn-1)
, And the image signals having a negative potential are sequentially input to the even-numbered source signal lines (S2, S4, S6,..., Sn). A so-called source line (column) inversion drive is performed.

During the first frame scanning period, that is, from the start of the first line scanning period to the end of the n-th line scanning period, the odd-numbered source signal lines (S1, S3, S5,...)
, Sn-1), a negative potential continues to be applied to the potential COM1 of the counter electrode 1 and the even-numbered source signal lines (Sn-1)
2, S4, S6,..., Sn), a positive potential is continuously applied to the potential COM2 of the opposite electrode 2. In this manner, the voltage of the image signal can be reduced by setting the potential of the counter electrode to a potential having the opposite sign to the potential of the image signal applied to the pixel electrode.

For example, consider a case where a liquid crystal having a saturation voltage of 5 V is used in the active matrix type liquid crystal display device of the present embodiment. When the image signal has a positive potential, a negative potential is applied to the counter electrode. In this case, the maximum value of the image signal can be 3 V by applying a potential of, for example, -2 V to the counter electrode. When the image signal has a negative potential, a positive potential is applied to the counter electrode. In this case, by applying a potential of, for example, 2 V to the counter electrode, the maximum value of the image signal may be -3 V.
Therefore, the maximum amplitude of the image signal can be reduced,
Power consumption can be reduced.

Next, writing of the image of the second frame will be described. Please refer to FIG. After the writing of the image of the first frame is completed, the writing of the image of the second frame is started.

When the first line (G1) scanning period of the second frame starts, an image signal having a negative potential is sequentially supplied to the odd-numbered source signal lines, and a positive image signal is supplied to the even-numbered source signal lines. An image signal having a potential is supplied. Therefore, the pixel TFTs (1, 1) to (1,
The writing of the image signal is sequentially performed on n), and the liquid crystal is driven. At this time, a positive potential is applied to the counter electrode 1 (COM1) corresponding to the odd-numbered source signal line, and the counter electrode 2 (C1) corresponding to the even-numbered source signal line.
OM2) is given a negative potential. Therefore, in the second frame, both the potential of the image signal supplied to each source signal line and the potential of the counter electrode are given potentials opposite to those in the first frame.

The pixel TFT (1, 1) connected to G1
When the writing of the image signal to 1) to (1, n) is completed,
Next, the second line (G2) scanning period starts similarly.

The above operation is sequentially performed for all pixel TFTs in one frame (first to n-th lines). Therefore, the odd-numbered source signal lines (S1, S3, S5,..., Sn-1)
, Image signals having a negative potential are sequentially input, and image signals having a positive potential are sequentially input to even-numbered source signal lines (S2, S4, S6,..., Sn).

An image is formed as described above. Usually, an image of 60 frames is formed in one second.

In this embodiment, in successive frames, the screen is displayed such that the potentials of the image signal supplied to each source signal line and the potential of the counter electrode are given the opposite signs. . However, in successive frames, the screen may be displayed such that the potential of the image signal supplied to each source signal line and the potential of the counter electrode are given the same potential.

Further, in the scanning of the continuous line, the screen may be displayed such that the potential of the image signal supplied to each source signal line and the potential of the counter electrode are given the opposite potentials. Good.

In this embodiment, n (the number of pixels in the horizontal direction) is an even number, but n may be an odd number.

In this embodiment, the image is written to the active matrix circuit by the dot sequential driving method. However, the image may be written by the line sequential driving method.

FIG. 6 shows the result of simulating the potential distribution characteristics of the pixels of the active matrix circuit of the active matrix type semiconductor display device of the present invention.
The axes of the graph shown in FIG. 6 indicate the potential V, a direction Y perpendicular to the substrate on which the pixel electrode and the counter electrode are formed, and a direction X horizontal to the substrate on which the pixel electrode and the counter electrode are formed. . Since the scale is arbitrary, it does not directly correspond to the actual value. For example, the potential V
In the above, "5" does not mean 5V. In the direction x horizontal to the substrate on which the pixel electrode and the counter electrode are formed, 0 to 20 represent the size of one pixel (called pixel 1),
40 correspond to the size of one pixel (referred to as pixel 2). Further, in the direction y perpendicular to the substrate on which the pixel electrode and the counter electrode are formed, it is set that the pixel electrode is at the position of 10 and the counter electrode is at the position of 20. Further, in the direction y perpendicular to the substrate on which the pixel electrode and the counter electrode are formed, the calculation is performed assuming a potential of 0 V at positions 0 and 30. Also, what is shown on the XY plane are the contour lines of the potential (the values of the contour lines of the potential are displayed at the upper right of the figure).

In the simulation shown in FIG.
A positive potential image signal is applied to the pixel electrodes of
A negative potential is applied to the corresponding counter electrode.
Further, a negative potential image signal is applied to the pixel electrode of the pixel 2, and a positive potential is applied to the corresponding counter electrode.

From the simulation results of FIG. 6, it is understood that the potential between the pixel electrode and the counter electrode changes approximately linearly in both the pixel 1 and the pixel 2. Therefore, between the pixel electrode and the counter electrode,
It can be seen that a uniform potential distribution occurs. That is, it can be understood from the simulation results that in the active matrix type liquid crystal display device having the configuration and the driving method as in the present embodiment, the voltage is uniformly applied to the liquid crystal of each pixel. It is also understood that there is almost no interaction between adjacent pixels and no influence such as crosstalk occurs.

(Example 2)

In the present embodiment, an active matrix type liquid crystal display device which is different from the active matrix type liquid crystal display device of Example 1 in the shape of the counter electrode and the driving method is different.

Referring to FIG. FIG. 7 is a schematic configuration diagram of the active matrix type liquid crystal display device of the present embodiment. 701 is a source signal line driving circuit, 702 is a gate signal line driving circuit, and 703 is an active matrix circuit. The active matrix liquid crystal display device of this embodiment has m × 4n (vertical × horizontal) pixels. n,
m is a natural number. For convenience of description, reference numerals (1, 1) to (m, 4n) are assigned to the respective pixels. Since the configuration of the active matrix circuit is the same as that of the first embodiment, refer to the first embodiment.

All pixel TFTs (1, 1) to pixel TFT
A pixel electrode (not shown) is provided for the drain electrode of (m, 1).
Is connected. On the counter substrate (not shown) side, a counter electrode 1 (not shown) and a counter electrode 2 (not shown) are formed. The counter electrode 1 is connected to the potential COM1. The counter electrode 2 is connected to the potential COM2. The active matrix liquid crystal display device of this embodiment is different from the active matrix liquid crystal display device of the first embodiment in the shape of the counter electrode.

FIG. 8 is referred to in order to describe the active matrix type liquid crystal display device of this embodiment in more detail.
FIG. 8 schematically shows a part of an active matrix circuit 703 in the schematic configuration diagram of the active matrix type liquid crystal display device of the present embodiment shown in FIG. In FIG. 8, pixel TFTs (1, 1) to pixel TF
T (m, 4n), pixel electrode 705, counter electrode 1 and counter electrode 2 are particularly schematically shown. As shown in FIG. 8, in the active matrix type liquid crystal display device of the present embodiment, the counter electrode 1 and the counter electrode 2 correspond to every two source signal lines so as to fill the gap therebetween. It has a shape. That is, the counter electrode 1
Are the source signal lines (S1, S2, S5, S6,..., S4n
-3, pixel TFT (1, 1) connected to S4n-2) to
(M, 1), (1, 2)-(m, 2), (1, 5)-
(M, 5), (1, 6) to (m, 6), ..., (1,
4n-3) to (m, 4n-3), (1, 4n-2) to
(M, 4n-2) are arranged corresponding to the respective pixels. The counter electrode 1 is connected to the source signal line (S
1, S2, S5, S6,..., S4n-3, S4n-2) connected to the pixel TFTs (1, 1) to (m, 1), (1, 2) to
(M, 2), (1, 5)-(m, 5), (1, 6)-
(M, 6), ..., (1, 4n-3) to (m, 4n-
3) It can also be said that they are arranged corresponding to the pixel electrodes 705 connected to each of (1, 4n-2) to (m, 4n-2). The counter electrode 2 is connected to the source signal line (S
, S4, S7, S8,..., S4n−1, S4n) connected to the pixel TFTs (1, 3) to (m, 3), (1, 4).
~ (M, 4), (1, 7) ~ (m, 7), (1, 8) ~
(M, 8), ..., (1, 4n-1) to (m, 4n-
1) and (1, 4n) to (m, 4n). The counter electrode 2 is connected to the source signal lines (S3, S4, S7, S8,..., S4n-
1, S4n) connected to pixel TFTs (1, 3) to (m,
3), (1, 4) to (m, 4), (1, 7) to (m,
7), (1, 8) to (m, 8), ..., (1, 4n-
1) to (m, 4n-1), (1, 4n) to (m, 4n)
It can be said that they are arranged corresponding to the pixel electrodes 705 connected to each of them.

The counter electrode 1 and the counter electrode 2 are supplied with different potentials, more precisely, opposite potentials, as in the first embodiment.

In this embodiment, an active matrix type liquid crystal display device having m × 4n (vertical × horizontal) pixels will be described. However, the number of pixels is not limited to this.

Next, the operation of the active matrix type liquid crystal display of this embodiment will be described. First, reference is made to FIG. FIG. 9 shows a timing chart for displaying the first frame of the active matrix liquid crystal display device of the present embodiment. Note that, as in the first embodiment, the first frame includes all pixels (pixels (1, 1) to (m, 4n))
The first frame scanning period is a period required to write an image signal to all pixels (pixels (1, 1) to (m, 4n)).

When the first line (G1) scanning period (period for writing pixels corresponding to the gate signal line G1) starts, the (4n-3) -th and (4n-2) -th source signal lines are sequentially turned on. Are supplied with an image signal having a positive potential, and the (4n-1) th and 4nth source signal lines are supplied with an image signal having a negative potential. Therefore G1
Pixel TFTs (1, 1) to (1, 4n) connected to
The writing of the image signal is performed in order, and the liquid crystal is driven. At this time, a negative potential is applied to the counter electrode 1 (COM1) corresponding to the (4n-3) th and (4n-2) th source signal lines, and the (4n-1) th and 4nth source signal lines are provided. The counter electrode 2 (COM) corresponding to the source signal line
In 2), a positive potential is applied.

The pixel TFT (1,...) Connected to G1
When the writing of the image signal to 1) to (1, n) is completed,
Next, a second line (G2) scanning period starts, and
An image signal having a positive potential is supplied to the (4n-3) th and (4n-2) th source signal lines, and (4n-
An image signal having a negative potential is supplied to the 1) th and 4nth source signal lines. Therefore, the writing of the image signal is sequentially performed on the pixel TFTs (2, 1) to (2, 4n) connected to G2, and the liquid crystal is driven. At this time, a negative potential is applied to the counter electrode 1 (COM1) corresponding to the (4n-3) th and (4n-2) th source signal lines, and the (4n-1) th and 4nth source signal lines are provided. The counter electrode 2 (COM2) corresponding to the source signal line has:
A positive potential is applied.

The pixel TFT (2, 2) connected to G2
When the writing of the image signal to 1) to (2, n) is completed,
Next, the third line (G3) scanning period starts, and in order,
An image signal having a positive potential is supplied to the (4n-3) th and (4n-2) th source signal lines, and (4n-
An image signal having a negative potential is supplied to the 1) th and 4nth source signal lines. Therefore, the writing of the image signal is sequentially performed on the pixel TFTs (3, 1) to (3, 4n) connected to G3, and the liquid crystal is driven. At this time, a negative potential is applied to the counter electrode 1 (COM1) corresponding to the (4n-3) th and (4n-2) th source signal lines, and the (4n-1) th and 4nth source signal lines are provided. The counter electrode 2 (COM2) corresponding to the source signal line has:
A positive potential is applied.

The above operation is sequentially performed for all pixel TFTs in one frame (first to fourth nth lines). Therefore,
Image signals having a positive potential are sequentially input to the (4n-3) th and (4n-2) th source signal lines, and
Image signals having negative potentials are sequentially input to the -1) th and 4nth source signal lines. A so-called source line (column) inversion drive is performed for every two source signal lines.

The above operation is performed for all the pixel TFTs in one frame (first to fourth nth lines).

Therefore, also in this embodiment, the voltage of the image signal can be reduced by setting the potential of the counter electrode to a potential having the opposite sign to the potential of the image signal applied to each pixel electrode.

In the second frame, as shown in FIG. 10, an image signal having a code opposite to that of the first frame scanning period is supplied to each source signal line. Further, the opposite electrode 1 and the opposite electrode 2 are each supplied with a potential having a sign opposite to that of the first frame scanning period.

In the present embodiment, in successive frames, the screen is displayed such that the potential of the image signal supplied to each source signal line and the potential of the counter electrode are given the opposite signs. . However, in successive frames, the screen may be displayed such that the potential of the image signal supplied to each source signal line and the potential of the counter electrode are given the same potential.

Further, in the scanning of the continuous line, the screen display may be performed such that the potential of the image signal supplied to each source signal line and the potential of the counter electrode are given the opposite signs. Good.

The number of pixels of the active matrix type liquid crystal display device may be other than m × 4n.

In this embodiment, two counter electrodes corresponding to two source signal lines are used. However, two counter electrodes corresponding to z source signal lines may be used.

In this embodiment, the image is written into the active matrix circuit by the dot sequential driving method. However, the image may be written by the line sequential driving method.

(Embodiment 3)

In this embodiment, an example of a method for manufacturing the active matrix liquid crystal display device described in Embodiments 1 and 2 will be described. In this embodiment, FIGS. 3 to 5 show examples in which a plurality of TFTs are formed on a substrate having an insulating surface, and an active matrix circuit, a driving circuit, a logic circuit, and the like are monolithically formed. In this embodiment, a state in which a CMOS circuit which is a basic circuit such as a driving circuit or a logic circuit is formed is shown. A CMOS circuit in which a P-channel TFT (PTFT) and an N-channel TFT (NTFT) each have one gate electrode will be described. However, a plurality of gate electrodes such as a double gate type and a triple gate type are used. A CMOS circuit using the provided TFT can be similarly manufactured. The pixel TFT is also an N-channel TFT.
Composed of

First, a base film made of a silicon oxide film 1102 was formed on a glass substrate 1101 to a thickness of 200 nm. As the base film, a silicon nitride film may be stacked, or only a silicon nitride film may be used.

Next, 30 nm is formed on the silicon oxide film 1102.
A thick amorphous silicon film (amorphous silicon film) was formed by a plasma CVD method, and after dehydrogenation treatment, excimer laser annealing was performed to form a polysilicon film (a crystalline silicon film or a polycrystalline silicon film).

In this crystallization step, a known laser crystallization technique or thermal crystallization technique may be used. In this embodiment, the amorphous silicon film is crystallized by processing a pulse oscillation type KrF excimer laser into a linear shape.

In this embodiment, the polysilicon film was obtained by crystallizing the initial film as an amorphous silicon film by laser annealing, but a microcrystalline silicon film may be used as the initial film, or the polysilicon film may be formed directly. It may be a film. Of course, laser annealing may be performed on the formed polysilicon film. Further, furnace annealing may be performed instead of laser annealing.

The crystalline silicon film thus formed is patterned to form an active layer 110 made of an island-like silicon layer.
3, 1104 were formed.

Next, a gate insulating film 1105 made of a silicon oxide film is formed to cover the active layers 1103 and 1104.
Gate wirings (including gate electrodes) 1106 and 1107 having a stacked structure of tantalum and tantalum nitride were formed thereon (FIG. 11A).

The thickness of the gate insulating film 1105 was 100 nm. Needless to say, a stacked structure of a silicon oxide film and a silicon nitride film or a silicon oxynitride film may be used instead of the silicon oxide film. Further, other metals can be used for the gate wirings 1106 and 1107, but a material having a high etching selectivity with silicon in a later step is preferable.

When the state shown in FIG. 11A was obtained, a first phosphorus doping step (a step of adding phosphorus) was performed. Here, the acceleration voltage is set to be as high as 80 KeV because of the addition through the gate insulating film 1105. The first impurity regions 1108 and 1109 thus formed have a length (width) of 0.5 μm and a phosphorus concentration of 1 × 10 ¹⁷ atoms / cm ^3.
The dose was adjusted so that The phosphorus concentration at this time is represented by (n-). Note that arsenic could be used instead of phosphorus.

The first impurity regions 1108 and 1109
Were formed in a self-aligned manner using the gate wirings 1106 and 1107 as a mask. At this time, the gate wirings 1106 and 11
07, an intrinsic crystalline silicon layer remains, and channel formation regions 1110 and 1111 were formed. However,
Actually, there is a portion that is added around the inside of the gate wiring, so that the gate wirings 1106 and 1107 overlap with the first impurity regions 1108 and 1109 (FIG. 11B). ).

Next, 0.1-1 μm (typically 0.2-0.
An amorphous silicon layer having a thickness of 3 μm) is formed, and anisotropic etching is performed to thereby form sidewalls 1112 and 111.
113 was formed. Side walls 1112, 1113
(Thickness as viewed from the side wall of the gate wiring) was 0.2 μm (FIG. 11C).

In this embodiment, since an amorphous silicon layer to which no impurity is added is used, a sidewall made of an intrinsic silicon layer is formed.

When the state shown in FIG. 11C was obtained, a second phosphorus doping step was performed. Also in this case, the acceleration voltage was set to 80 KeV as in the first time. Also, the second formed this time
Phosphorous is 1 × 10 ¹⁸ at in impurity regions 1114 and 1115.
The dose was adjusted to be contained at a concentration of oms / cm ³ .
The phosphorus concentration at this time is represented by (n).

Note that in the phosphorus doping step shown in FIG. 11D, the first impurity regions 1108 and 1109 remain only under the sidewalls 1112 and 1113. These first impurity regions 1108 and 1109 function as 1st LDD regions.

In the step of FIG. 11D, phosphorus was also added to the side walls 1112 and 1113. Actually, phosphorus was distributed in such a state that the tail of the phosphorus concentration profile extended to the inside of the sidewall due to the high acceleration voltage. Although the resistance component of the sidewall can be adjusted by this phosphorus, if the concentration distribution of phosphorus varies extremely, the gate voltage applied to the second impurity region 1114 may be a factor that varies for each element. Requires precise control.

Next, a resist mask 1116 covering a part of the NTFT and a resist mask 11 covering the entire PTFT are used.
17 was formed. Then, in this state, the gate insulating film 11 is formed.
Gate insulating film 1 processed by dry etching 05
118 was formed (FIG. 11E).

At this time, the length of the portion where the gate insulating film 1118 protrudes outside the sidewall 1112 (the length of the portion where the gate insulating film 1118 is in contact with the second impurity region 1114) is the second impurity. The length (width) of the region 1114 was determined. Therefore, the resist mask 1116
It was necessary to perform mask alignment with high accuracy.

When the state shown in FIG. 11E was obtained, a third phosphorus doping step was performed. In this case, since the phosphorus is added to the exposed active layer, the acceleration voltage is set to be as low as 10 KeV. The dose was adjusted so that the third impurity region 1119 thus formed contained phosphorus at a concentration of 5 × 10 ²⁰ atoms / cm ³ . The phosphorus concentration at this time is represented by (n +) (FIG. 12A).

In this step, since phosphorus is not added to the portion shielded by resist masks 1116 and 1117, second impurity regions 1114 and 1115 remain in that portion. Therefore, the second impurity region 11
14 are defined. At the same time, the third impurity region 1119
Is defined.

The second impurity region 1114 has the 2nd LDD
The third impurity region 1119 functions as a region, and functions as a source region or a drain region.

Next, resist masks 1116 and 1117 are formed.
Is removed, and a new resist mask 1 covering the entire NTFT is formed.
121 was formed. Then, the side wall 1113 of the PTFT was removed, and the gate insulating film 1105 was dry-etched to form a gate insulating film 1122 having the same shape as the gate wiring 1107 (FIG. 12B).

When the state shown in FIG. 12B was obtained, a boron doping step (boron adding step) was performed. Here, the acceleration voltage is set to 10 KeV, and the formed fourth impurity region 11 is formed.
The dose was adjusted so that 23 contained boron at a concentration of 3 × 10 ²⁰ atoms / cm ³ . The boron concentration at this time is (p
++) (FIG. 12C).

At this time, since boron is also added around the inside of the gate wiring 1107, it is added.
Reference numeral 11 is formed inside the gate wiring 1107. Also,
In this step, the first impurity region 1109 and the second impurity region 1115 formed on the PTFT side are inverted with boron to be P-type. Therefore, actually the first
Although the resistance value changes between the portion that was the impurity region and the portion that was the second impurity region, there is no problem because boron is added at a sufficiently high concentration.

Thus, the fourth impurity region 1123 is defined. The fourth impurity region 1123 is a gate wiring 110
7 is formed in a completely self-aligned manner by using as a mask, and functions as a source region or a drain region. In this embodiment, P
Neither the LDD region nor the offset region is formed for the TFT, but there is no problem since the PTFT is originally high in reliability. On the contrary, it is more convenient to provide no LDD region because the ON current can be gained. is there.

Thus, finally, as shown in FIG. 12C, a channel formation region, a first impurity region, a second impurity region, and a third impurity region are formed in the active layer of the NTFT, and the active layer of the PTFT is formed. Only the channel formation region and the fourth impurity region are formed.

When the state shown in FIG. 12C was obtained in this manner, a first interlayer insulating film 1124 was formed to a thickness of 1 μm. As the first interlayer insulating film 1124, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, an acrylic resin film is employed.

After forming the first interlayer insulating film 1124, source wirings 1125, 1126 and drain wiring 1127 made of a metal material were formed. In this embodiment, a three-layer wiring having a structure in which an aluminum film containing titanium is sandwiched between titanium is used.

Further, as the first interlayer insulating film 1124, BC
When a resin film called B (benzocyclobutene) is used, flatness is improved and copper can be used as a wiring material. Copper is very effective as a wiring material because of its low wiring resistance.

After forming the source wiring and the drain wiring in this way, a 50 nm-thick silicon nitride film 1128 was formed as a passivation film. Further thereon, a second interlayer insulating film 1129 was formed as a protective film. As the second interlayer insulating film 1129, the first interlayer insulating film 1124 is used.
It is possible to use the same material as described above. In this embodiment, a structure in which an acrylic resin film is laminated on a silicon oxide film having a thickness of 50 nm is employed.

Through the above steps, a CMOS circuit having a structure as shown in FIG. 12D is completed. In the CMOS circuit formed according to the present embodiment, NTFT has excellent reliability, and thus the reliability of the entire circuit is greatly improved. In addition, when the structure is as in this embodiment, NTFT
And the PTFT and the PTFT have an excellent characteristic balance (balance of electrical characteristics).

[0105] Similarly, the pixel TFT can be constituted by NTFT.

When the state shown in FIG. 12D is obtained, a contact hole is opened and a pixel electrode connected to the drain electrode of the pixel TFT is formed. Then, a third interlayer film is formed, and an alignment film is formed. In this example, polyimide was used for the alignment film. Further, a black matrix may be formed as needed.

Next, a counter substrate is prepared. The counter substrate is
It is composed of a glass substrate, a counter electrode made of a transparent conductive film, and an alignment film. The counter electrode is processed into the shape described in the first and second embodiments.

In this example, a polyimide film was used as the alignment film. After the formation of the alignment film, a rubbing treatment was performed. In this example, polyimide having a relatively large pre-tilt angle was used for the alignment film.

Next, the active matrix substrate and the counter substrate having undergone the above-described steps are assembled by a known cell assembling step.
Laminate via a sealing material or spacer. Thereafter, a liquid crystal is injected between the two substrates and completely sealed with a sealant. In this embodiment, a nematic liquid crystal is used as the liquid crystal.

Thus, a transmission type active matrix liquid crystal display device is completed.

(Example 4)

This embodiment shows an example in which the crystalline semiconductor film to be an active layer in Embodiment 3 is formed by a thermal crystallization method using a catalytic element. When a catalyst element is used, Japanese Patent Application Laid-Open Nos. 7-130652 and 8-7
It is preferable to use the technique described in US Pat.

FIG. 13 shows an example in which the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 is applied to the present invention. First, a silicon oxide film 1302 is provided on a silicon substrate 1301 by a thermal oxidation method, and an amorphous silicon film 1
303 was formed. Further, a nickel acetate solution containing 10 ppm by weight of nickel was applied to form a nickel-containing layer 1304 (FIG. 13A).

Next, after the hydrogenation step at 500 ° C. for 1 hour, the temperature is set at 500 to 650 ° C. for 4 to 12 hours.
A heat treatment (50 ° C. for 8 hours) is performed to form a polysilicon film 130.
5 was formed. The polysilicon film 130 thus obtained
No. 5 had very excellent crystallinity (FIG. 13 (B)).

After that, the polysilicon film 1305 is patterned to form an active layer.
T was produced.

The technique described in Japanese Patent Application Laid-Open No. H8-78329 enables selective crystallization of an amorphous semiconductor film by selectively adding a catalyst element. FIG. 1 shows a case where the same technology is applied to the present invention.
4 will be described.

First, a silicon oxide film 1402 was provided on a glass substrate 1401, and an amorphous silicon film 1403 and a silicon oxide film 1404 were continuously formed thereon. At this time, the thickness of the silicon oxide film 1404 is 150 nm.
And

Next, an opening 1405 was selectively formed by patterning the silicon oxide film 1404, and then a nickel acetate salt solution containing 100 ppm by weight of nickel was applied. Thus, a nickel-containing layer 1406 was formed, and the nickel-containing layer 1406 was brought into contact with the amorphous silicon film 1402 only at the bottom of the opening 1405 (FIG. 14A).

Next, a heat treatment was performed at 500 to 650 ° C. for 4 to 24 hours (in this embodiment, 570 ° C. for 14 hours) to crystallize the amorphous silicon film. In this crystallization process, the portion in contact with nickel is first crystallized, and crystal growth proceeds in a direction substantially parallel to the substrate. It has been confirmed crystallographically that it proceeds in the <111> axis direction.

The thus formed polysilicon film 140
Reference numeral 7 is an aggregation of rod-shaped or needle-shaped crystals. Each rod-shaped crystal macroscopically grows in a specific direction, and thus has an advantage of uniform crystallinity.

In the above two technologies, in addition to nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (C
o), elements such as platinum (Pt), copper (Cu), and gold (Au) may be used.

A crystalline semiconductor film (including a crystalline silicon film and a crystalline silicon germanium film) may be formed by using the above-described techniques, and may be patterned to form an active layer. Subsequent steps may follow the third embodiment.

When a TFT is manufactured using a crystalline semiconductor film crystallized using the technique of this embodiment, high field-effect mobility (mobility) can be obtained, but high reliability has been required. However, the TFT of this embodiment
By adopting the structure, it is possible to manufacture a TFT that makes the most of the technology of this embodiment.

(Example 5)

In this embodiment, as shown in Embodiment 4, after forming a polysilicon film using a catalytic element (for example, nickel), a step of removing nickel remaining in the film is performed. Is shown. In this embodiment, as a technique for removing nickel, a technique described in JP-A-10-270363 or JP-A-10-247735 is used.

The technique described in Japanese Patent Application Laid-Open No. H10-270363 is to remove nickel used for crystallization of a semiconductor by using a gettering effect of an element belonging to Group 15 (typically, phosphorus) after crystallization. Technology. By using the same technology, the nickel concentration in the active layer is reduced to 1 × 10 ¹⁷ atoms / cm
It can be reduced to ³ or less (preferably 1 × 10 ¹⁶ atoms / cm ³ or less).

FIG. 15 shows a case where the same technique is applied to the present invention. First, a polysilicon film 1505 was formed according to the steps of the fourth embodiment. Next, a mask insulating film 1501 having an opening was provided, and phosphorus was added in that state. At this time, a region 1502 to which phosphorus was added at a high concentration was formed in the polysilicon film exposed at the opening. The present applicant calls this area a gettering area (FIG. 15A).

The gettering area 1502 has 1 × 10 ¹⁹
~ 1 × 10 ²¹ atoms / cm ³ (typically 1 × 10 ²⁰ atoms / c
Phosphorus is added at a concentration of m ³ ).

Next, a heat treatment was performed at 550 to 650 ° C. for 4 to 15 hours (in this embodiment, 12 hours at 600 ° C.).
The catalyst element (nickel in this embodiment) remaining in the polysilicon film 1505 by this heat treatment moved in the direction of the arrow and was captured (gettered) in the gettering region 1502. The region 1502 is called a gettering region for such a reason. The concentration of nickel contained in the polysilicon film 1503 thus formed was reduced to 1 × 10 ¹⁷ atoms / cm ³ or less.

The technique described in Japanese Patent Application Laid-Open No. Hei 10-247735 is intended to selectively add a catalytic element after crystallization using the technique described in Japanese Patent Application Laid-Open No. Hei 7-135318. This is a technique characterized by using the used mask as it is as a mask for adding phosphorus. This technique is very effective for improving the throughput.

A crystalline semiconductor film (including a polysilicon film and a polysilicon germanium film) may be formed using the present embodiment having the above-described technique, and may be patterned to form an active layer. Subsequent steps may follow the third embodiment.

(Embodiment 6)

In the present embodiment, as shown in Embodiment 4, after forming a polysilicon film using a catalytic element (for example, nickel), a step of removing the nickel is performed. In this embodiment, as a technique for removing nickel,
JP-A-10-135468 or JP-A-10-1
The technique described in Japanese Patent No. 35469 was used.

The technique described in this publication is a technique of removing nickel used for crystallization of a semiconductor by using gettering action of a halogen element (typically chlorine) after crystallization. By using this technique, the nickel concentration in the active layer is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less (preferably 1 × 10 ¹⁶ ato
ms / cm ³ or less).

The structure of this embodiment will be described with reference to FIG. First, a quartz substrate 1601 having high heat resistance is used as a substrate.
Was used. Of course, a silicon substrate or a ceramic substrate may be used. When a quartz substrate is used, there is no contamination from the substrate side even if a silicon oxide film is not provided as a base film.

Next, a polysilicon film (not shown) is formed by using the means of the fourth embodiment, and is patterned to form an active layer 16.
02 and 1603 were formed. Further, a gate insulating film 1604 made of a silicon oxide film was formed to cover those active layers (FIG. 16A).

After forming the gate insulating film 1604, heat treatment was performed in an atmosphere containing a halogen element. In this embodiment, the atmosphere is an oxidizing atmosphere in which oxygen and hydrogen chloride are mixed, the processing temperature is 950 ° C., and the processing time is 30 minutes. Note that the processing temperature may be selected from 700 to 1100 ° C., and the processing time may be selected from 10 minutes to 8 hours (FIG. 16B).

At this time, nickel becomes volatile nickel chloride and is released into the processing atmosphere, and the nickel concentration in the polysilicon film is reduced. Therefore, the concentration of nickel contained in the active layers 1605 and 1606 shown in FIG. 16B was reduced to 1 × 10 ¹⁷ atoms / cm ³ or less.

An active layer is formed by using the present embodiment having the above-described technique, and the subsequent steps may be in accordance with the third embodiment.

(Embodiment 7)

In this embodiment, an example of a manufacturing method of the active matrix type liquid crystal display device described in the above-described Embodiments 1 and 2 will be described, which is different from Embodiment 3.

Referring to FIG. 17 and FIG. First, as the substrate 1701, an alkali-free glass substrate represented by, for example, a 1737 glass substrate manufactured by Corning Incorporated was used. Then, a base film 1702 made of silicon oxide was formed to a thickness of 200 nm on the surface of the substrate 1701 where the TFT was formed. As the base film 1702, a silicon nitride film may be further stacked, or only a silicon nitride film may be used.

Next, a 50 nm film is
An amorphous silicon film was formed by the plasma CVD method so as to have a thickness. Although it depends on the amount of hydrogen contained in the amorphous silicon film, it is preferable to carry out dehydrogenation treatment by heating to 400 to 500 ° C. to reduce the amount of hydrogen contained in the amorphous silicon film to 5 atm% or less and to carry out the crystallization step. This was performed to obtain a crystalline silicon film.

In the crystallization step, a known laser crystallization technique or thermal crystallization technique may be used. In this embodiment, a pulse oscillation type KrF excimer laser beam is condensed linearly and applied to an amorphous silicon film to form a crystalline silicon film. Note that the crystallization step may use the method described in the fifth and sixth embodiments.

In this embodiment, the initial film is used as an amorphous silicon film. However, a microcrystalline silicon film may be used as the initial film, or a crystalline silicon film may be directly formed.

The crystalline silicon film thus formed is patterned to form island-like semiconductor layers 1703, 1704, 17
05 was formed.

Next, the semiconductor layers 1703, 1704, 17
05, a gate insulating film 1706 containing silicon oxide or silicon nitride as a main component was formed. Here, plasma C
A silicon nitride oxide film was formed to a thickness of 100 nm by a VD method. Although not described in FIG. 17, the gate insulating film 1
Tantalum (Ta) is formed as a first conductive film on the surface of the first gate electrode 706 at 10 to 200 nm, for example, 50 nm, and aluminum (A) is formed as a second conductive film.
1) was formed with a thickness of 100 to 1000 nm, for example, 200 nm by a sputtering method. Then, first conductive films 1707, 1708, 1709, and 1710 constituting the first gate electrode and 1712, 1713, 1714, and 1715 of the second conductive film were formed by a known patterning technique.

When aluminum is used as the second conductive film constituting the first gate electrode, pure aluminum may be used, or an element selected from titanium, silicon and scandium may be 0.1 to 5 atm. % Added aluminum alloy may be used. In the case of using copper, although not shown, a silicon nitride film is preferably provided on the surface of the gate insulating film 1706.

FIG. 17 shows a structure in which an additional capacitance section is provided on the drain side of the n-channel TFT forming the pixel matrix circuit. At this time, the wiring electrodes 1711 and 1716 of the additional capacitance portion are made of the same material as the first gate electrode.
Is formed.

After the structure shown in FIG. 17A is formed, a first step of adding an n-type impurity is performed.
As an impurity element that imparts n-type to the crystalline semiconductor material, phosphorus (P), arsenic (As), antimony (S
b) and the like are known, but here, the ion doping method using phosphorous and phosphine (PH ₃ ) was used. In this step, the accelerating voltage is set to 80 because phosphorus is added through the gate insulating film 1706 to the semiconductor layer thereunder.
KeV was set higher. Further, the impurity regions thus formed form first impurity regions 1734 and 1742 of an n-channel TFT described later, and function as LDD regions. Therefore, the concentration of phosphorus in this region is preferably set in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atms / cm ³ , and here, it is set to 1 × 10 ¹⁸ atms / cm ³ .

The impurity element added to the semiconductor layer had to be activated by laser annealing or heat treatment. This step may be performed after the step of adding impurities for forming the source / drain regions, but activation at this stage by the laser annealing method was effective.

In this step, the first conductive films 1707, 1708, 1709, 1710 constituting the first gate electrode are formed.
And second conductive films 1712, 1713, 1714, 171
5 served as a mask for the addition of phosphorus. As a result, no or almost no phosphorus was added to the region immediately below the first gate electrode of the semiconductor layer existing via the gate insulating film. Then, as shown in FIG. 17B, the low-concentration impurity regions 1717,
718, 1719, 1720, 1721, 1722, 1
723 was formed.

Next, using the photoresist film as a mask, n
A region for forming a channel type TFT is formed by a resist mask 17.
The step of adding an impurity for imparting a p-type was performed only on the region where the p-channel TFT was formed, which was covered with 24 and 1725. As an impurity element imparting p-type, boron (B), aluminum (Al), and gallium (Ga) are known. Here, boron is used as the impurity element, and diborane (B ₂ H) is ion-doped. ₆ ). Here, the acceleration voltage is set to 80 keV and 2 × 10
Boron was added to a concentration of ²⁰ atms / cm ³ . And FIG.
As shown in (C), region 1 in which boron is added at a high concentration
726, 1727 were formed. This region will later be the source / drain region of the p-channel TFT.

Then, the resist masks 1724, 172
After removing No. 5, a step of forming a second gate electrode was performed. Here, tantalum (Ta) is used as the material of the second gate electrode, and the thickness is 100 to 1000 nm, for example, 200 nm.
It was formed to a thickness of nm. Then, patterning is performed by a known technique, and second gate electrodes 1728 and 172 are formed.
9, 1730, 1731 were formed. At this time, patterning was performed so that the length of the second gate electrode was 5 μm. As a result, in the second gate electrode, regions were formed on both sides of the first gate electrode, each having a length of 1.5 μm and in contact with the gate insulating film.

Further, an additional capacitance portion is provided on the drain side of the n-channel TFT constituting the pixel matrix circuit, and the electrode 1728 of this additional capacitance portion is formed simultaneously with the second gate electrode.

Then, the second gate electrodes 1728, 17
29, 1730, 1731 as a mask, the second n
A step of adding an impurity element for imparting a mold was performed. Here, similarly, the ion doping method using phosphine (PH ₃ ) was performed. Also in this step, the gate insulating film 1706 is used.
The accelerating voltage was set as high as 80 keV in order to add phosphorus to the semiconductor layer therebelow. Here, the region to which phosphorus is added is an n-channel TFT, which is a source region 1735, 1743, a drain region 1736,
In order to function as 1747, the concentration of phosphorus in this region is preferably 1 × 10 ¹⁹ to 1 × 10 ²¹ atms / cm ^3, and in this case, 1 × 10 ²⁰ atms / cm ³ .

Although not shown here, the source regions 1735, 1743 and the drain regions 1736, 17
The gate insulating film covering 47 may be removed to expose the semiconductor layer in that region, and phosphorus may be directly added. By adding this step, the acceleration voltage of the ion doping method could be reduced to 10 keV, and phosphorus could be added efficiently.

The source region 1 of the p-channel TFT is
739 and the drain region 1740 are also doped with phosphorus at the same concentration, but since boron is added at twice the concentration in the previous step, the conductivity type is not inverted, and the p-channel TF
There was no problem in the operation of T.

The n-type or p-type added at each concentration
Since the impurity element imparting the mold does not activate as it is and does not work effectively, it is necessary to perform an activation step. This step includes a thermal annealing method using an electric heating furnace,
The laser annealing using an excimer laser and the rapid thermal annealing (RTA) using a halogen lamp can be performed.

In the thermal annealing method, activation was performed by heating at 550 ° C. for 2 hours in a nitrogen atmosphere. In the present embodiment, aluminum is used for the second conductive film constituting the first gate electrode.
Since the conductive film and the second gate electrode were formed so as to cover the aluminum, the tantalum functioned as a blocking layer to prevent aluminum atoms from diffusing into other regions. In the laser annealing method, activation was performed by condensing and irradiating a pulsed KrF excimer laser beam in a linear manner. Further, when the thermal annealing method was performed after the laser annealing method, even better results were obtained. This step also has the effect of annealing the region where the crystallinity has been destroyed by the ion doping, and has improved the crystallinity of the region.

In the above steps, the gate electrode is provided with the first gate electrode and the second gate electrode is provided so as to cover the first gate electrode. In the case of the n-channel type TFT, both sides of the second gate electrode are provided. Then, a source region and a drain region were formed. Further, a structure in which a first impurity region provided in a semiconductor layer with a gate insulating film interposed therebetween and a region where a second gate electrode is in contact with the gate insulating film is formed in a self-aligned manner is provided. Was done. On the other hand, in a p-channel TFT,
Although the source region and the drain region partially overlap with the second gate electrode, there was no problem in practical use.

When the state shown in FIG. 17D was obtained, a first interlayer insulating film 1749 was formed to a thickness of 1000 nm.
As the first interlayer insulating film 1749, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used. In this embodiment, although not shown, a two-layer structure in which a silicon nitride film is first formed to a thickness of 50 nm and a silicon oxide film is further formed to a thickness of 950 nm.

After that, the first interlayer insulating film 1749 was patterned to form contact holes in the source region and the drain region of each TFT. Then, the source electrodes 1750, 1752, 1753 and the drain electrode 17
51, 1754 were formed. Although not shown, in the present embodiment, this electrode is formed by patterning a three-layer structure film in which a titanium film is continuously formed by a sputtering method with a titanium film of 100 nm, a titanium-containing aluminum film of 300 nm, and a titanium film of 150 nm. .

As shown in FIG. 17E, a CMOS circuit and an active matrix circuit were formed on the substrate 1701. Further, n of the active matrix circuit
On the drain side of the channel type TFT, a storage capacitor portion was simultaneously formed. As described above, an active matrix substrate was manufactured.

Next, a process for manufacturing an active matrix type liquid crystal display device based on the CMOS circuit manufactured on the same substrate and the active matrix circuit by the above process will be described with reference to FIG. First, FIG.
The source electrode 1750, 1
752, 1753 and drain electrodes 1751, 1754
Then, a passivation film 1755 was formed to cover the first interlayer insulating film 1749. Passivation film 1755
Was formed with a thickness of 50 nm using a silicon nitride film. further,
The second interlayer insulating film 1756 made of an organic resin is
It was formed to a thickness of 0 nm. As the organic resin film, polyimide, acrylic, polyimide amide, or the like can be used. The advantages of using an organic resin film include that the film forming method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film other than those described above can also be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used.

Next, a light shielding layer 1557 was formed in a part of the pixel region of the second interlayer insulating film 1756. Light shielding layer 175
7 may be formed of a metal film or an organic resin film containing a pigment. Here, titanium was formed by a sputtering method.

After forming the light-shielding film 1775, a third interlayer insulating film 1758 is formed. This third interlayer insulating film 17
58 is preferably formed using an organic resin film, similarly to the second interlayer insulating film 1756. Then, a contact hole reaching the drain electrode 1754 was formed in the second interlayer insulating film 1756 and the third interlayer insulating film 1758, and a pixel electrode 1759 was formed. The pixel electrode 1759 may be formed using a transparent conductive film in the case of a transmissive liquid crystal display device, or a metal film in the case of a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method, and a pixel electrode 1759 was formed.

After the state shown in FIG. 18A is formed, an alignment film 1760 is formed. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. Opposite substrate 1
On 771, a counter electrode 1772 and an alignment film 1773 were formed. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were parallel-aligned with a certain pretilt angle. The counter electrode was processed as described in Example 1 or Example 2.

Through the above-mentioned steps, the substrate on which the active matrix circuit, the CMOS circuit is formed, and the counter substrate are bonded to each other via a sealing material or a spacer (both not shown) by a known cell assembling step. afterwards,
A liquid crystal material 1774 was injected between both substrates, and completely sealed with a sealant (not shown). Thus, the active matrix liquid crystal display device shown in FIG.

(Embodiment 8) In the above-described embodiments 3 to 7, an active matrix type liquid crystal display device is manufactured using a top gate type TFT. However, a bottom gate type TFT such as an inverted stagger may be used. good.

(Embodiment 9) In the active matrix type liquid crystal display devices of Embodiments 1 to 8 described above, a TN mode using a nematic liquid crystal as a display medium is used as a display mode. Can also be used.

Further, an active matrix type liquid crystal display device may be constructed by using a thresholdless antiferroelectric liquid crystal or a ferroelectric liquid crystal having a high response speed as a display medium.

For example, in 1998, SID, "Characteristics an
d Driving Scheme of Polymer-Stabilized Monostable
FLCD Exhibiting Fast Response Time and High Contra
st Ratio with Gray-Scale Capability "by H. Furue e
t al., 1997, SID DIGEST, 841, "A Full-Color Thres
holdless Antiferroelectric LCD Exhibiting Wide Vie
wing Angle with Fast Response Time "by T. Yoshida
et al., 1996, J. Mater. Chem. 6 (4), 671-673, "Th
resholdless antiferroelectricity in liquidcrystals
and its application to displays "by S. Inui et a
and the liquid crystal disclosed in U.S. Pat. No. 5,594,569 can be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V (cell thickness is about 1 μm to 2 μm).
m) have also been found.

Here, FIG. 21 shows an example showing characteristics of light transmittance with respect to applied voltage of a thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optical response. The vertical axis of the graph shown in FIG. 21 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. Note that the transmission axis of the polarizing plate on the incident side of the active matrix type liquid crystal display device is substantially the same as the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal which substantially matches the rubbing direction of the active matrix type liquid crystal display device. It is set in parallel. The transmission axis of the exit-side polarizing plate is set to be substantially perpendicular (crossed Nicols) to the transmission axis of the incidence-side polarizing plate.

As shown in FIG. 21, it can be seen that when such a thresholdless antiferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible.

When such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in an active matrix type liquid crystal display device having an analog driver, the power supply voltage of the image signal sampling circuit is, for example, 5V. It can be suppressed to about 8 V. Therefore, the operating power supply voltage of the driver can be reduced, and low power consumption and high reliability of the active matrix liquid crystal display device can be realized.

Also, when such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in an active matrix liquid crystal display device having a digital driver, the D / D
Since the output voltage of the A conversion circuit can be reduced, D /
The operating power supply voltage of the A conversion circuit can be reduced, and the operating power supply voltage of the driver can be reduced. Therefore, low power consumption and high reliability of the active matrix liquid crystal display device can be realized.

Therefore, the use of such a low-voltage-driven thresholdless antiferroelectric mixed liquid crystal makes it possible to use a TFT (for example, a TFT having a relatively small LDD region (low-concentration impurity region)).
(0 nm to 500 nm or 0 nm to 200 nm) is also effective.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used in an active matrix type liquid crystal display device, a relatively large storage capacitor is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. In addition, by making the driving method of the active matrix type liquid crystal display device line-sequential driving, the writing period (pixel feed period) of the gray scale voltage to the pixel is lengthened, and even if the storage capacity is small, it is compensated. You may.

Since low-voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal, low power consumption of an active matrix type liquid crystal display device is realized.

Any liquid crystal having electro-optical characteristics as shown in FIG. 21 can be used as the display medium of the active matrix type liquid crystal display device of the present invention.

In the active matrix semiconductor display device of the present invention, any other display medium whose optical characteristics can be modulated in response to an applied voltage may be used. For example, an electroluminescent element may be used.

As an active element used in an active matrix circuit of an active matrix type liquid crystal display device, an MIM element or the like other than a TFT may be used.

In the above embodiment, an active matrix type liquid crystal display device in which an active matrix circuit and a driving circuit are integrally formed on the same substrate has been described. However, the active matrix type semiconductor display device of the present invention is described. The active matrix circuit and the drive circuit may be formed separately. In this case, an amorphous silicon TFT can be used as a pixel TFT constituting an active matrix circuit, and a driving circuit is an IC.
Can be configured by

(Embodiment 10) In this embodiment, an example of an electronic apparatus in which the active matrix semiconductor display devices of the above-described Embodiments 1 to 9 are incorporated as components will be described. Note that the active matrix semiconductor display device of the present invention can be applied to all kinds of electronic devices other than the following electronic devices.

Examples of such electronic devices include a video camera, a digital camera, a projector, a projection TV, a head mounted display (goggle type display), a car navigation system, a personal computer, and a portable information terminal (mobile computer, mobile phone, electronic book, etc.). ). One example of them is shown in FIG.

FIG. 19A shows a portable telephone, and
01, an audio output unit 1902, an audio input unit 1903, an active matrix semiconductor display device 1904, operation switches 1905, and an antenna 1906.

FIG. 19B shows a video camera, which includes a main body 2001 and an active matrix type semiconductor display device 20.
02, an audio input unit 2003, an operation switch 2004, a battery 2005, and an image receiving unit 2006.

FIG. 19C shows a mobile computer (mobile computer), which includes a main body 2101, a camera section 2102, an image receiving section 2103, operation switches 2104, and an active matrix display device 2105.

FIG. 19D shows a goggle type display, which comprises a main body 2201, an active matrix type semiconductor display device 2202, and an arm portion 2203.

FIG. 19E shows a rear type projector, which includes a main body 2301, a light source 2302, an active matrix type semiconductor display device 2303, and a polarizing beam splitter 2.
304, reflectors 2305 and 2306, and a screen 2307.

FIG. 19F shows a portable book (electronic book), which includes a main body 2401, active matrix semiconductor display devices 2402 and 2403, a storage medium 2404, operation switches 2405, and an antenna 2406.

As described above, the applicable range of the active matrix type semiconductor display device of the present invention is extremely wide, and it can be applied to electronic devices in various fields.

(Embodiment 11) The active matrix type liquid crystal display device of this embodiment is different from the embodiment 2 in the shape of the counter electrode. However, other configurations are the same as in the second embodiment.

Referring to FIG. FIG. 22 is a schematic configuration diagram of the active matrix type liquid crystal display device of the present embodiment. Note that the active matrix circuit portion is schematically shown. In FIG. 22, reference numeral 801 denotes a source signal line driving circuit, 802 denotes a gate signal line driving circuit,
Reference numeral 804 denotes a pixel TFT, and 805 denotes a pixel electrode.

In the present embodiment, the counter electrode 1 and the counter electrode 2 correspond to every two source signal lines, respectively.
It has a shape that fills the gap between each other.

That is, the counter electrode 1 is connected to the source signal line (S
1, S2, S5, S6,..., S4n-3, S4n-2) connected to the pixel TFTs (1, 1) to (m, 1), (1, 2) to
(M, 2), (1, 5)-(m, 5), (1, 6)-
(M, 6), ..., (1, 4n-3) to (m, 4n-
3) and (1, 4n-2) to (m, 4n-2). However, for example, pixel TFTs (1, 1) to (m, 1) and (1,
The second embodiment differs from the second embodiment in that the counter electrodes arranged corresponding to the pixels having 2) to (m, 2) have no gap.

The opposite electrode 2 is connected to the source signal line (S
, S4, S7, S8,..., S4n−1, S4n) connected to the pixel TFTs (1, 3) to (m, 3), (1, 4).
~ (M, 4), (1, 7) ~ (m, 7), (1, 8) ~
(M, 8), ..., (1, 4n-1) to (m, 4n-
1) and (1, 4n) to (m, 4n). However, for example, the pixel T
FT (1,3) to (m, 3) and (1,4) to (m,
The counter electrode arranged corresponding to the pixel having 4) is different from the second embodiment in that there is no gap.

(Embodiment 12) This embodiment is different from the other embodiments in the structure of the counter electrode. However, other configurations are the same as those of the first embodiment.

Referring to FIG. FIG. 23 schematically shows an active matrix circuit portion in the schematic configuration diagram of the active matrix liquid crystal display device of the present embodiment. In FIG. 23, reference numeral 901 denotes a source signal line driving circuit, 902 denotes a gate signal line driving circuit, 904 denotes a pixel TFT, and 905 denotes a pixel electrode.

In this embodiment, the counter electrode 1 includes a counter electrode 1-1 made of a light-transmitting conductive material and a counter electrode 1-2 made of a low-resistance metal material. The counter electrode 1-2 is formed above the pixel TFT 904 and functions as a light shielding film. As a material of the counter electrode 1-2, for example, Ti or the like can be used.

The counter electrode 2 has the same structure as that of the counter electrode 1, and includes the counter electrode 2-1 made of a transparent conductive material.
And a counter electrode 2-2 made of a metal material having a low resistance.

By adopting the configuration as in this embodiment, the resistance of the counter electrode 1 and the counter electrode 2 can be reduced.

(Embodiment 13) In this embodiment, the configuration of the counter electrode is different from that of the twelfth embodiment. However, other configurations are the same as those of the twelfth embodiment.

Referring to FIG. FIG. 24 schematically shows a portion of an active matrix circuit in a schematic configuration diagram of the active matrix type liquid crystal display device of the present embodiment. 24, reference numeral 1001 denotes a source signal line driving circuit, 1002 denotes a gate signal line driving circuit,
04 is a pixel TFT, and 1005 is a pixel electrode.

The counter electrode 1 and the counter electrode 2 of this embodiment
Is different from the counter electrode and the counter electrode 2 of Example 12 in that the shapes of the counter electrode 1-2 and the counter electrode 2-2 functioning as a light shielding film are different. The counter electrode 1 has a configuration in which a counter electrode 1-1 made of a transparent conductive material is sandwiched between a counter electrode 1-2 made of a low-resistance metal material above a pixel. As a material of the counter electrode 1-2, for example, Ti or the like can be used.

The counter electrode 2 has the same structure as the counter electrode 1.

By employing the configuration as in the present embodiment, the resistance of the counter electrode 1 and the counter electrode 2 can be further reduced as compared with the twelfth embodiment.

Embodiment 14 In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described.

FIG. 25A is a top view of an EL display device using the present invention. In FIG. 25A, 4010
Denotes a substrate, 4011 denotes a pixel portion, 4012 denotes a source side driver circuit, and 4013 denotes a gate side driver circuit. Each of the driver circuits is connected to an FPC 4017 through wirings 4014 to 4016.
And connected to the external device.

At this time, the cover member 600 is formed so as to surround at least the pixel portion, preferably, the driving circuit and the pixel portion.
0, sealing material (also referred to as housing material) 7000,
A sealing material (a second sealing material) 7001 is provided.

FIG. 25B shows a cross-sectional structure of the EL display device of this embodiment.
A driving circuit TFT 4022 (here, a CMOS circuit combining an n-channel TFT and a p-channel TFT is illustrated) 4022 and a pixel portion TFT 40
23 (however, here, TF for controlling the current to the EL element)
Only T is shown. ) Is formed. These T
The FT may use a known structure (top gate structure or bottom gate structure). When the driving circuit TFT 4022 and the pixel portion TFT 4023 are completed by using the present invention, a transparent conductive film electrically connected to the drain of the pixel portion TFT 4023 is formed on an interlayer insulating film (planarization film) 4026 made of a resin material. The pixel electrode 4027 is formed. As the transparent conductive film, a compound of indium oxide and tin oxide (called ITO) or a compound of indium oxide and zinc oxide can be used.

[0214] Next, an EL layer 4029 is formed. The EL layer 4029 is formed of a known EL material (a hole injection layer, a hole transport layer,
A light-emitting layer, an electron transport layer, or an electron injection layer) may be freely combined to form a stacked structure or a single-layer structure. A known technique may be used to determine the structure. Also, E
The L material includes a low molecular material and a high molecular (polymer) material. When a low molecular material is used, an evaporation method is used, but when a high molecular material is used, a spin coating method,
A simple method such as a printing method or an inkjet method can be used.

[0215] In this embodiment, an EL layer is formed by an evaporation method using a shadow mask. By forming a light-emitting layer (a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer) capable of emitting light having different wavelengths for each pixel using a shadow mask, color display becomes possible. In addition, the color conversion layer (CC
M) and a color filter are combined, and a white light-emitting layer and a color filter are combined. Either method may be used. Needless to say, a monochromatic EL display device can be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable to remove as much as possible moisture and oxygen existing at the interface. Therefore, the EL layer 4029 and the cathode 40 in vacuum
It is necessary to devise a method of continuously forming the film 30 or forming the EL layer 4029 in an inert atmosphere and forming the cathode 4030 without opening to the atmosphere. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

In this embodiment, the cathode 4030 is
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by a vapor deposition method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in a region indicated by 4031. A wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 via the conductive paste material 4032.
7 is connected.

In the region indicated by 4031, the cathode 40
In order to electrically connect the wiring 30 and the wiring 3016, it is necessary to form contact holes in the interlayer insulating film 4026 and the insulating film 4028. These are at the time of etching the interlayer insulating film 4026 (at the time of forming the contact hole for the pixel electrode).
Or when the insulating film 4028 is etched (when an opening is formed before the EL layer is formed). Also, the insulating film 40
When etching 28, etching may be performed all at once up to the interlayer insulating film 4026. In this case, the interlayer insulating film 40
If the same resin material is used for the insulating film 26 and the insulating film 4028, the shape of the contact hole can be made good.

[0219] The passivation film 6003 and the filler 600 cover the surface of the EL element thus formed.
4. The cover material 6000 is formed. Further, the cover member 6000 and the substrate 4010 are arranged so as to surround the EL element portion.
A sealing material (second sealing material) 70 is provided outside the sealing material 7000.
01 is formed.

At this time, the filler 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0221] The filler 6004 may contain a spacer. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have translucency.

The wiring 4016 is made of a sealing material 700.
0 and through the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Although the wiring 4016 has been described here, the other wiring 401
4, 4015 are similarly electrically connected to the FPC 4017 under the sealant 7000 and the sealant 7001. [Embodiment 15] In this embodiment, an example of manufacturing an EL display device having a mode different from that of Embodiment 14 using the present invention will be described with reference to FIGS. FIG.
Elements having the same numbers as 5 (A) and 25 (B) indicate the same parts, and thus description thereof will be omitted.

FIG. 26A is a top view of the EL display device of this embodiment, and FIG. 26B is a cross-sectional view taken along line AA ′ of FIG.

According to Embodiment 14, a passivation film 6003 is formed to cover the surface of the EL element.

[0228] Further, a filler 6004 is provided so as to cover the EL element. This filler 6004 is used as the cover material 6
000 also functions as an adhesive for bonding. As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because a moisture absorbing effect can be maintained.

[0229] A spacer may be contained in the filler 6004. At this time, the spacer may be a granular substance made of BaO or the like, and the spacer itself may have hygroscopicity.

In the case where a spacer is provided, the passivation film 6003 can reduce the spacer pressure.
Further, a resin film or the like for relaxing the spacer pressure may be provided separately from the passivation film.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless steel plate, FRP (Five)
rglass-Reinforced Plastic
s) plate, PVF (polyvinyl fluoride) film,
Mylar film, polyester film or acrylic film can be used. The filling material 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which aluminum foil of several tens of μm is sandwiched between PVF films or Mylar films.

However, depending on the direction of light emission (the direction of light emission) from the EL element, the cover material 6000 needs to have a light transmitting property.

Next, using the filler 6004, the cover material 6
After bonding 000, the side surface of filler 6004 (exposed surface)
Frame material 6001 is attached so as to cover. The frame material 6001 is a sealing material (functions as an adhesive)
Glued by 6002. At this time, a photocurable resin is preferably used as the sealing material 6002, but a thermosetting resin may be used as long as the heat resistance of the EL layer is allowed. Note that the sealing material 6002 is preferably a material that does not transmit moisture or oxygen as much as possible. Further, a desiccant may be added to the inside of the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 has been described here, the other wirings 4014 and 4015 are also electrically connected to the FPC 4017 under the sealing material 6002 in the same manner. [Embodiment 16] The present invention can be applied to an EL display panel having the structure as in Embodiments 14 and 15. Here, a more detailed sectional structure of the pixel portion is shown in FIG.
FIG. 28A shows a top view structure, and FIG. 28B shows a circuit diagram.
Shown in 27, 28 (A) and 28 (B) use the same reference numerals, so they may be referred to each other.

Referring to FIG. 27, a switching TFT 3502 provided on a substrate 3501 is an NTF of the present invention.
It is formed using T. This embodiment has a double gate structure. However, the double gate structure has a structure in which two TFTs are substantially connected in series, and has an advantage that an off-current value can be reduced. Although the double gate structure is used in this embodiment, a single gate structure, a triple gate structure, or a multi-gate structure having more gates may be used. In addition, it may be formed using a PTFT.

The current control TFT 3503 is formed by using the NTFT of the present invention. At this time, the drain wiring 35 of the switching TFT 3502 is electrically connected to the gate electrode 37 of the current controlling TFT by the wiring 36. The wiring indicated by 38 is a gate wiring for electrically connecting the gate electrodes 39a and 39b of the switching TFT 3502.

At this time, it is very important that the current control TFT 3503 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows and the element has a high risk of deterioration due to heat or hot carriers. Therefore, the structure of the present invention in which the LDD region is provided on the drain side of the current controlling TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In this embodiment, the current controlling TFT 35 is used.
03 is shown with a single gate structure.
A multi-gate structure in which FTs are connected in series may be used.
Further, a structure in which a plurality of TFTs are connected in parallel to substantially divide the channel formation region into a plurality of regions so that heat can be radiated with high efficiency may be employed. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 28A, the wiring to be the gate electrode 37 of the current controlling TFT 3503 has 35 wirings.
In a region indicated by 04, the region overlaps with the drain wiring 40 of the current control TFT 3503 via an insulating film. At this time, 3
In the region indicated by 504, a capacitor is formed. This capacitor 3504 functions as a capacitor for holding a voltage applied to the gate of the current control TFT 3503. The drain wiring 40 is connected to a current supply line (power supply line) 3506, and a constant voltage is constantly applied.

The first passivation film 4 is formed on the switching TFT 3502 and the current control TFT 3503.
And a planarizing film 42 made of a resin insulating film thereon.
Is formed. It is very important to flatten the step due to the TFT using the flattening film 42. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 43 denotes a pixel electrode (cathode of an EL element) made of a conductive film having high reflectivity.
503 is electrically connected to the drain. Pixel electrode 43
It is preferable to use a low-resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a stacked film thereof. Of course, a stacked structure with another conductive film may be employed.

A light emitting layer 45 is formed in a groove (corresponding to a pixel) formed by banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
Light emitting layers corresponding to each color of B (blue) may be separately formed.
As the organic EL material for the light emitting layer, a π-conjugated polymer material is used. Typical polymer-based materials include polyparaphenylenevinylene (PPV), polyvinylcarbazole (PVK), and polyfluorene.

Note that there are various types of PPV-based organic EL materials, for example, “H. Shenk, H. Becker, O. Ge.
lsen, E. Kluge, W. Kreuder, and H. Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and JP-A-10-92576.

As specific light emitting layers, cyanopolyphenylenevinylene is used for a red light emitting layer, polyphenylenevinylene is used for a green light emitting layer, and polyphenylenevinylene or polyalkylphenylene is used for a blue light emitting layer. Good. The film thickness is 30-150n
m (preferably 40 to 100 nm).

However, the above example is an example of the organic EL material that can be used as the light emitting layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer.

For example, in this embodiment, an example in which a polymer material is used for the light emitting layer has been described, but a low molecular organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

In this embodiment, PEDOT is formed on the light emitting layer 45.
This is an EL layer having a laminated structure provided with a hole injection layer 46 made of (polythiophene) or PAni (polyaniline). An anode 47 made of a transparent conductive film is provided on the hole injection layer 46. In the case of this embodiment, since the light generated in the light emitting layer 45 is emitted toward the upper surface side (toward the upper side of the TFT), the anode must be translucent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used; however, it is possible to form after forming a light-emitting layer or a hole-injecting layer with low heat resistance. A material that can form a film at a temperature as low as possible is preferable.

When the anode 47 is formed, the EL element 3
505 is completed. Note that the EL element 3505 mentioned here
Are the pixel electrode (cathode) 43, the light emitting layer 45, the hole injection layer 4
6 and the anode 47. FIG.
As shown in (A), the pixel electrode 43 substantially matches the area of the pixel, so that the entire pixel functions as an EL element. Therefore, the efficiency of light emission is extremely high, and a bright image can be displayed.

In the present embodiment, a second passivation film 48 is further provided on the anode 47. Second
As the passivation film 48, a silicon nitride film or a silicon nitride oxide film is preferable. The purpose of this is to shut off the EL element from the outside, and has both the meaning of preventing the organic EL material from being deteriorated due to oxidation and the effect of suppressing outgassing from the organic EL material. Thereby, the reliability of the EL display device is improved.

As described above, the EL display panel of the present invention has a pixel portion composed of pixels having a structure as shown in FIG. 27, a switching TFT having a sufficiently low off-state current value, and a current controlling portion having a strong resistance to hot carrier injection. And a TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The structure of this embodiment is similar to those of the first to thirteenth embodiments.
It can be implemented in any combination with the configuration.
Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the tenth embodiment.

(Embodiment 17) In this embodiment, Embodiment 16 will be described.
A structure in which the structure of the EL element 3505 is inverted in the pixel portion shown in FIG. FIG. 29 is used for the description. Note that the only difference from the structure of FIG. 27 is the EL element portion and the current control TFT, so that the other description will be omitted.

In FIG. 29, the current control TFT 350
3 is formed using PTFT.

In this embodiment, a transparent conductive film is used as the pixel electrode (anode) 50. Specifically, a conductive film formed using a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

The banks 51a and 51b made of insulating films
Is formed, a light emitting layer 52 made of polyvinyl carbazole is formed by applying a solution. An electron injection layer 53 made of potassium acetylacetonate (denoted as acacK) and a cathode 54 made of an aluminum alloy are formed thereon. In this case, the cathode 54 also functions as a passivation film. Thus, an EL element 3701 is formed.

In the case of this embodiment, the light generated in the light emitting layer 52 is radiated toward the substrate on which the TFT is formed as shown by the arrow.

The structure of this embodiment is similar to that of the first to thirteenth embodiments.
Can be freely combined with the above configuration. Further, it is effective to use the EL display panel of this embodiment as the display unit of the electronic device of the tenth embodiment.

(Embodiment 18) In this embodiment, FIG.
FIGS. 30A to 30C show examples in which a pixel having a structure different from that of the circuit diagram shown in FIG. In this embodiment, reference numeral 3801 denotes a switching TFT 380.
2 is a source wiring, and 3803 is a switching TFT 38.
02, a gate wiring 3804, a current controlling TFT 38,
05 is a capacitor, 3806 and 3808 are current supply lines,
Reference numeral 3807 denotes an EL element.

FIG. 30A shows an example in which a current supply line 3806 is shared between two pixels. That is, the feature is that two pixels are formed to be line-symmetric with respect to the current supply line 3806. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 30 (B) shows the current supply line 380
8 is provided in parallel with the gate wiring 3803. Note that in FIG. 30B, the current supply line 3808 and the gate wiring 3803 are provided so as not to overlap with each other.
They can be provided so as to overlap with each other via an insulating film. In this case, since the power supply line 3808 and the gate wiring 3803 can share an occupied area, the pixel portion can have higher definition.

In FIG. 30C, a current supply line 3808 is provided in parallel with the gate wiring 3803 in the same manner as in the structure of FIG. 30B, and two pixels are connected to the current supply line 3808.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 3808 so as to overlap with one of the gate wirings 3803. In this case, the number of power supply lines can be reduced, so that the pixel portion can have higher definition.

The structure of the present embodiment is similar to that of the first to first embodiments.
The present invention can be implemented in any combination with the configuration of 3, 14, or 15. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 10. (Embodiment 19) FIGS. 28A and 28 shown in Embodiment 16
In (B), the capacitor 3504 is provided to hold the voltage applied to the gate of the current controlling TFT 3503; however, the capacitor 3504 can be omitted. In the case of Embodiment 16, the current control TFT 350
3, the NTFT of the present invention is used.
It has a DD area. A parasitic capacitance generally called a gate capacitance is formed in the overlapped region. The present embodiment is characterized in that this parasitic capacitance is actively used instead of the capacitor 3504.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the LDD region overlap, it is determined by the length of the LDD region included in the overlapping region.

Further, FIG. 30 (A),
Similarly, in the structures (B) and (C), the capacitor 3
It is possible to omit 805.

The structure of this embodiment is similar to that of Embodiments 1 to 18
Can be freely combined with the above configuration. In addition, it is effective to use an EL display panel having the pixel structure of this embodiment as a display portion of the electronic device of Embodiment 10.

[0266]

According to the active matrix type semiconductor display device of the present invention, the opposing electrodes are divided into two, different potentials are applied to the two opposing electrodes, and the two opposing electrodes are driven to be inverted. Thus, the potential of the image signal can be reduced, so that the voltage required for operating the driver circuit can be reduced.

As a result, it is possible to improve the reliability of the elements such as the TFTs constituting the driving circuit and the active matrix circuit and to reduce the power consumption.

In addition, since the voltage of the timing pulse supplied by the driving circuit can be reduced, the boosting circuit can be omitted, and the area of the driving circuit can be reduced.

In the active matrix type semiconductor display device of the present invention, addressing modes such as gate line (row) inversion drive, source line (column) inversion drive, and dot (point) inversion drive can be effectively adopted. Deterioration of the display screen can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of an active matrix semiconductor display device of the present invention.

FIG. 2 is a schematic configuration diagram of one embodiment of an active matrix semiconductor display device of the present invention.

FIG. 3 is an enlarged view of an active matrix circuit of one embodiment of the active matrix type semiconductor display device of the present invention.

FIG. 4 is an operation timing chart of an embodiment of the active matrix type semiconductor display device of the present invention.

FIG. 5 is an operation timing chart of an embodiment of the active matrix type semiconductor display device of the present invention.

FIG. 6 is a simulation result of a potential distribution characteristic of a pixel of the active matrix semiconductor display device of the present invention.

FIG. 7 is a schematic configuration diagram of an embodiment of an active matrix semiconductor display device of the present invention.

FIG. 8 is a schematic configuration diagram of one embodiment of an active matrix semiconductor display device of the present invention.

FIG. 9 is an operation timing chart of an embodiment of the active matrix type semiconductor display device of the present invention.

FIG. 10 is an operation timing chart of an embodiment of the active matrix semiconductor display device of the present invention.

FIG. 11 is an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 12 is an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 13 illustrates an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 14 is an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 15 is an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 16 is an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 17 illustrates an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 18 illustrates an example of a manufacturing process of an active matrix semiconductor display device of the present invention.

FIG. 19 is an example of an electronic device equipped with the active matrix semiconductor display device of the present invention.

FIG. 20 is a schematic configuration diagram of a conventional active matrix liquid crystal display device.

FIG. 21 is a graph showing an applied voltage-transmittance characteristic of a thresholdless antiferroelectric mixed liquid crystal.

FIG. 22 is a schematic configuration diagram of an embodiment of an active matrix type semiconductor display device of the present invention.

FIG. 23 is a schematic configuration diagram of an embodiment of an active matrix type semiconductor display device of the present invention.

FIG. 24 is a schematic configuration diagram of an embodiment of an active matrix semiconductor display device of the present invention.

FIG. 25 is a top view and a cross-sectional view of an embodiment of the active matrix semiconductor display device of the present invention.

26A and 26B are a top view and a cross-sectional view of an embodiment of an active matrix semiconductor display device of the present invention.

FIG. 27 is a sectional view of an embodiment of the active matrix semiconductor display device of the present invention.

FIG. 28 is a configuration diagram and a circuit diagram of a pixel portion of an embodiment of an active matrix semiconductor display device of the present invention.

FIG. 29 is a sectional view of an embodiment of an active matrix semiconductor display device of the present invention.

FIG. 30 is a circuit diagram of an embodiment of the active matrix type semiconductor display device of the present invention.

[Explanation of symbols]

 101 Source signal line drive circuit 102 Gate signal line drive circuit 103 Active matrix circuit 104 Pixel TFT 105 Pixel electrode 106 Liquid crystal 107 Storage capacitance

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/30 G02F 1/136 500 3/36 1/137 510 H01L 29/786 H01L 29/78 612C

Claims (5)

[Claims] 1. A source signal line driving circuit for supplying an image signal to a plurality of source signal lines, a gate signal line driving circuit for supplying a selection signal to a plurality of gate signal lines, a pixel TFT and a drain electrode of the pixel TFT A pixel having a pixel electrode connected to the pixel TFT is arranged in a matrix, the source signal line is connected to the source electrode of the pixel TFT, and the gate signal line is connected to the gate electrode of the pixel TFT. A matrix circuit; two counter electrodes; a display medium sandwiched between the pixel electrode and the counter electrode;
An active matrix type semiconductor display device having: wherein the two counter electrodes are respectively arranged corresponding to pixels corresponding to each source signal line among the plurality of source signal lines; An active matrix semiconductor display device in which two opposite electrodes are respectively supplied with potentials opposite to the potential of an image signal supplied to a corresponding source signal line. 2. A source signal line driving circuit for supplying an image signal to a plurality of source signal lines, a gate signal line driving circuit for supplying a selection signal to a plurality of gate signal lines, a pixel TFT and a drain electrode of the pixel TFT. A pixel having a pixel electrode connected to the pixel TFT is arranged in a matrix, the source signal line is connected to the source electrode of the pixel TFT, and the gate signal line is connected to the gate electrode of the pixel TFT. A matrix circuit; two counter electrodes; a display medium sandwiched between the pixel electrode and the counter electrode;
An active matrix type semiconductor display device having: wherein the two counter electrodes are respectively arranged corresponding to pixels corresponding to every two source signal lines of the plurality of source signal lines; An active matrix semiconductor display device in which two opposite electrodes are respectively supplied with potentials opposite to the potential of an image signal supplied to a corresponding source signal line. 3. A source signal line driving circuit for supplying an image signal to a plurality of source signal lines, a gate signal line driving circuit for supplying a selection signal to a plurality of gate signal lines, a pixel TFT and a drain electrode of the pixel TFT. A pixel having a pixel electrode connected to the pixel TFT is arranged in a matrix, the source signal line is connected to the source electrode of the pixel TFT, and the gate signal line is connected to the gate electrode of the pixel TFT. A matrix circuit; two counter electrodes; a display medium sandwiched between the pixel electrode and the counter electrode;
An active matrix type semiconductor display device having: wherein the two counter electrodes are respectively arranged corresponding to pixels corresponding to z source signal lines of the plurality of source signal lines; An active matrix semiconductor display device in which two opposite electrodes are respectively supplied with potentials opposite to the potential of an image signal supplied to a corresponding source signal line. 4. The display medium according to claim 1, wherein said display medium is a liquid crystal.
4. The active matrix type semiconductor display device according to item 3. 5. The active matrix type semiconductor display device according to claim 1, wherein said display medium is an antiferroelectric mixed liquid crystal having a V-shaped electro-optical characteristic.