JP2000341555A - System and method for adjusting delay quantity of sampling clock of video signal and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay quantity adjustment system and a delay quantity adjusting method for sampling clock of a video signal, which can maintain the number of steps of the phase adjustment of the sampling lock at a fixed level whatever the frequency the sampling clock may be. SOLUTION: This system can change the delay quantity of a sampling signal 14a of an A/D converter 18 by the oscillation frequency of a PLL 16, and whatever the frequency of the clock 14a may be, the system does not depend on the resolution (the number of display dots) of a screen and also adjusts the delay quantity within the adjustment range of the optimum number of steps, so as not to cause large changes in number of steps.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for adjusting a delay amount of a sampling clock used when sampling is performed by an A / D (analog / digital) converter to convert an analog video signal into a digital signal. TECHNICAL FIELD The present invention relates to a system for adjusting a delay amount of a sampling clock of a video signal, a delay amount adjusting method, and a recording medium which can keep the number of steps of phase adjustment of a sampling clock constant at any frequency.

[0002]

2. Description of the Related Art In current digital video equipment, A / D (analog / digital) is used to convert an analog video signal into a digital signal.
Sampling with a digital) converter. In this case, the sampling clock supplied to the A / D converter converts the horizontal synchronization signal of the video signal into a PLL (Phase) signal.
The reference clock is generated by dividing the frequency by a locked loop, and a predetermined amount of delay is added to the reference clock. At this time, if the delay amount added to the reference clock is not set to an appropriate value, noise will be added to the video data sampled by the A / D converter. There must be.

Conventionally, in order to obtain an appropriate delay amount, a delay of 1 ns (nano (nano is one billionth) second) per step and a delay amount is adjusted in 64 steps. This is done by repeating the fixed delay amount a set number of times (first conventional technique).

Another conventional technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-161614 (second conventional technique). That is, the second prior art aims to provide a signal delay technique suitable for adjusting the phase of a sampling clock with a simple configuration, and uses a display device to output an analog image signal output from a computer. An image display device for displaying, comprising: an A / D conversion circuit that converts an analog image signal into a digital image signal based on a sampling clock; and a PLL circuit that generates a dot clock synchronized with a horizontal synchronization signal output from a computer. And a sampling clock adjustment circuit that generates a sampling clock by delaying the dot clock, adjusts the phase relationship between the sampling clock and the analog image signal by adjusting the amount of delay, and an A / D conversion circuit. Display the image using a display device according to the digital image signal. The sampling clock adjustment circuit includes a delay circuit, and a delay amount adjustment circuit that controls the delay amount of the delay circuit, and the delay circuit has different delay amounts connected in parallel. N stages (N is an integer of 2 or more) of cascade-connected delay blocks each having a plurality of delay paths and a selection circuit for selecting one of the plurality of delay paths, and delay amount adjustment A selection signal generation circuit for generating N selection signals to be applied to each selection circuit of the N-stage delay block in accordance with a signal supplied from the circuit. 0 delay paths and (M + 1) delay paths each having a delay amount of 1 to M times a predetermined delay unit (M is an integer of 1 or more that can be set to a different value for each delay block), N-stage delay Each predetermined delay unit block has a different value, in the delay block of the N stages, i-th (i
Is an integer from 1 to (N-1)), the predetermined delay unit in the i-th delay block having a delay unit of size
It has a delay unit of the (i + 1) th or later size (i +
1) The delay amount is set to a value larger than the total value of the delay amounts at the time of selection in each selection circuit so that the total value of the delay amounts through the delay blocks after the first is the largest. In the i-th (i is 1 to (N-1)
The predetermined delay unit in the i-th delay block having a delay unit having a size of (integer) is the number of delay paths in the (i + 1) -th delay block having a (i + 1) -th delay unit. The image display device is set to be equal to a value obtained by multiplying a value of a predetermined delay unit in an (i + 1) -th delay block.

[0005]

However, in the first prior art, in the VGA standard or the like having a long time of one clock, there is an adjustment range of several tens steps per clock.
In the UXGA standard or the like in which the time of one clock is short, there is a problem that there is only an adjustment width of several steps in one clock.

On the other hand, the second prior art has the following problems. First, the first problem is that it is difficult to adjust the delay amount within an optimum adjustment range of the number of steps so as not to greatly change the number of steps. The reason is that the second prior art is a sampling clock delay circuit in which delay circuits each having a delay amount of an integral multiple of each other are further configured in multiple stages. And the second
The problem is that the scale of the actual circuit cannot be reduced. The reason is that the second prior art describes a method of expressing a delay line compactly on a circuit diagram, and a delay circuit having a large delay has an appropriate scale.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide an image capable of keeping the number of steps of the phase adjustment of the sampling clock constant regardless of the frequency of the sampling clock. An object of the present invention is to provide a signal sampling clock delay amount adjustment system, a delay amount adjustment method, and a recording medium.

[0008]

The gist of the present invention is that a delay of a sampling clock of a video signal can be kept constant regardless of the frequency of the sampling clock. A video signal, comprising: means for changing a delay amount of one step in accordance with a dot clock of an input video signal; and means for performing phase adjustment with a fixed total number of steps. In the sampling clock delay amount adjusting system. The gist of the invention described in claim 2 is to round up a numerical value obtained as a result of an operation of dividing the product of the time of one dot and the predetermined number of steps by the product of the total number of steps and the delay time of the delay element. ,
2. The system according to claim 1, further comprising means for determining a delay amount according to the designated number of steps. Further, the gist of the present invention is to provide a PLL for generating and outputting a reference clock by dividing a horizontal synchronizing signal of a video signal, and a delay for generating and outputting a delay amount designating signal for designating a predetermined delay amount. An amount determining means, a delay amount adjusting means for generating and outputting a sampling clock by adding a predetermined amount of delay to the reference clock from the PLL based on the delay amount specifying signal from the delay amount determining means; 3. The system according to claim 1, further comprising an A / D converter for converting a video signal into a digital signal based on a clock.
The gist of the present invention is that the delay amount adjusting means selectively combines the plurality of delay elements and the plurality of delay elements based on the delay amount designating signal from the delay amount determining means. 4. A delay selector for generating a predetermined delay amount to generate and output the sampling clock obtained by adding the predetermined delay amount to the reference clock from the PLL.
The video signal sampling clock delay amount adjusting system described in (1). The gist of the invention according to claim 5 is that the delay amount adjusting means defines a total number of steps and a delay time of the delay element, and the number of steps between 0 and the total number of steps. Means for defining the number of phase adjustment steps, and means for calculating the sampling time of one dot from the horizontal synchronization frequency and the frequency division ratio and substituting the calculated sampling time for the time of the one dot. A fourth aspect of the present invention is a video signal sampling clock delay amount adjusting system. The gist of the invention described in claim 6 is that the delay amount adjusting means has means for outputting a numerical value obtained by calculating a predetermined arithmetic expression to the delay selector as the delay amount designating signal. In the system for adjusting a delay amount of a sampling clock of a video signal according to the fourth or fifth aspect of the present invention. The gist of the invention described in claim 7 is that the delay amount adjusting means calculates a predetermined arithmetic expression as (time of one dot * number of phase adjustment steps) /
5. The apparatus according to claim 4, further comprising means for outputting a numerical value obtained by calculating an arithmetic expression described by (total number of steps * delay time of the delay element) to the delay selector as the delay amount designation signal. 5. A system for adjusting a delay amount of a sampling clock of a video signal according to item 5. The gist of the invention described in claim 8 is a method of adjusting a delay amount of a sampling clock of a video signal, wherein the number of steps of adjusting the phase of the sampling clock can be kept constant regardless of the frequency of the sampling clock. 1 according to the dot clock of the video signal
A method for adjusting a delay amount of a sampling clock of a video signal includes a step of changing a delay amount of a step and a step of performing phase adjustment with a fixed total number of steps. The gist of the invention described in claim 9 is:
The value obtained by dividing the product of the time of one dot and the predetermined number of steps by the product of the total number of steps and the delay time of the delay element is rounded up, and the delay amount according to the specified number of steps is rounded up. The method according to claim 8, further comprising the step of determining the delay amount of the sampling clock of the video signal. The gist of the present invention is to provide a reference clock generating step of generating and outputting a reference clock by dividing a horizontal synchronizing signal of a video signal, and generating and outputting a delay amount specifying signal for specifying a predetermined delay amount. A delay amount determining step for outputting, and a delay amount for generating and outputting a sampling clock by adding a predetermined delay amount to the reference clock from the reference clock generating step based on the delay amount designating signal from the delay amount determining step The method according to claim 8 or 9, further comprising an adjusting step and an A / D conversion step of converting the video signal into a digital signal based on the sampling clock. The gist of the present invention is that the delay amount adjusting step generates a predetermined delay amount by selectively combining a plurality of delay elements based on the delay amount designation signal from the delay amount determining step. 11. The video signal sampling clock according to claim 10, further comprising a delay selection step of generating and outputting the sampling clock obtained by adding the predetermined delay amount to the reference clock from the reference clock generation step. In the method of adjusting the amount of delay. The gist of the invention according to claim 12 is that, in the delay amount adjusting step, a total number of steps is defined;
Defining the delay time of the delay element, defining the number of phase adjustment steps by the number of steps from 0 to the total number of steps, and calculating the sampling time of one dot from the horizontal synchronization frequency and the division ratio. 12. The method according to claim 11, further comprising a step of substituting the calculated sampling time into the time of the one dot. The gist of the invention described in claim 13 is that the delay amount adjusting step includes a step of outputting a numerical value obtained by calculating a predetermined arithmetic expression to the delay selecting step as the delay amount designating signal. A method for adjusting a delay amount of a sampling clock of a video signal according to claim 11 or 12. The gist of the invention described in claim 14 is that, in the delay amount adjusting step, a predetermined arithmetic expression is used.
A numerical value obtained by calculating an arithmetic expression described by (time of one dot * number of phase adjustment steps) / (total number of steps * delay time of delay element) is output to the delay select step as the delay amount designation signal. 13. The method according to claim 11, further comprising the step of adjusting a delay amount of a sampling clock of a video signal. A gist of the invention according to claim 15 is a recording medium on which a program for adjusting a delay amount of a sampling clock of a video signal capable of keeping the number of steps of adjusting the phase of the sampling clock constant regardless of the frequency of the sampling clock. And a program code for changing a delay amount of one step according to a dot clock of an input video signal, and a program code for executing phase adjustment with a fixed total number of steps. It is present on a recording medium on which a sampling clock delay amount adjustment program is recorded. The gist of the invention described in claim 16 is to round up a numerical value obtained as a result of an operation of dividing the product of the time of one dot and the predetermined number of steps by the product of the total number of steps and the delay time of the delay element. And a program code for determining a delay amount in accordance with the specified number of steps. The recording medium according to claim 15, wherein the delay amount adjustment program for a video signal sampling clock is recorded. The gist of the invention described in claim 17 is to generate a reference clock generating program code for generating and outputting a reference clock by dividing the horizontal synchronizing signal of a video signal and a delay amount specifying signal for specifying a predetermined delay amount. A sampling clock is generated by adding a predetermined delay amount to the reference clock from the reference clock generation program code based on the delay amount determination program code to be output and the delay amount designation signal from the delay amount determination program code. 17. The delay of a video signal sampling clock according to claim 15, further comprising: a delay amount adjustment program code to be output; and an A / D conversion program code for converting a video signal into a digital signal based on the sampling clock. Be on the recording medium that has recorded the quantity adjustment program The gist of the invention described in claim 18 is that the delay amount adjustment program code is configured to selectively combine a plurality of delay elements based on the delay amount designating signal from the delay amount determination program code and to provide a predetermined delay amount. 18. The video according to claim 17, further comprising a delay select program code for generating and outputting the sampling clock obtained by adding the predetermined delay amount to the reference clock from the reference clock generation program code. The present invention resides in a recording medium on which a delay adjustment program for a signal sampling clock is recorded. The gist of the invention described in claim 19 is that the delay amount adjustment program code includes a program code defining a total number of steps;
A sampling time of one dot is calculated from a program code that defines a delay time of the delay element and a phase adjustment step number by a step number between 0 and the total step number, and a horizontal synchronization frequency and a frequency division ratio. 19. The recording medium according to claim 18, further comprising a program code for substituting the calculated sampling time into the one-dot time. The gist of the invention according to claim 20 is that the delay amount adjustment program code is a program code for outputting a numerical value obtained by calculating a predetermined arithmetic expression to the delay select program code as the delay amount designation signal. 20. A recording medium according to claim 18 or 19, wherein the program for adjusting a delay amount of a sampling clock of a video signal is recorded. According to a twenty-first aspect of the present invention, the delay amount adjustment program code is obtained by calculating a predetermined arithmetic expression by (time of one dot * number of phase adjustment steps) / (total number of steps * delay time of delay element). 20. The video signal sampling clock according to claim 18, further comprising: a program code for outputting a numerical value obtained by calculating an arithmetic expression to be described to the delay select program code as the delay amount designating signal. In the recording medium on which the delay amount adjustment program is recorded.

[0009]

FIG. 1 is a system configuration diagram for explaining a system 100 for adjusting a delay amount of a sampling clock 14a of a video signal according to an embodiment of the present invention. In FIG. 1, reference numeral 12 denotes delay amount determining means,
2a is a delay amount designation signal, 14 is delay amount adjusting means, 142 is a delay element, 146 is a delay selector,
4a is a sampling clock, 16 is a PLL, 16a is a reference clock, 18 is an A / D converter, and 100 is a delay amount adjustment system. Referring to FIG.
Sampling clock 14a of video signal of the present embodiment
The delay amount adjustment system 100 of FIG. 1 divides the horizontal synchronizing signal of the video signal (analog video signal) and
PLL 16 (Phase Loc) that generates and outputs 6a
(Ked Loop), a delay amount determining means 12 for generating and outputting a signal (delay amount specifying signal 12a) for specifying a predetermined delay amount, and a delay amount specifying signal 12a from the delay amount determining means 12 to output a signal from the PLL 16. A delay amount adjusting means 14 for generating and outputting a sampling clock 14a by adding a predetermined delay amount to a reference clock 16a, and an A / D (analog / analog) for converting a video signal (analog video signal) into a digital signal based on the sampling clock 14a. Digital) converter 18. The delay amount adjusting means 14 includes a plurality of delay elements 142,.
42, and a plurality of delay elements 142,..., 142 are selectively combined based on the delay amount designating signal 12a from the delay amount determination means 12 to generate a predetermined amount of delay.
The delay selector 146 generates and outputs a sampling clock 14a obtained by adding the predetermined delay amount to the reference clock 16a from L16.

The delay amount adjusting means 14 defines a total step number STEP and a delay amount delay (= delay time of the delay element 142) for one delay element 142, The user sets the phase adjustment step number st by the number of steps (natural number) during STEP.
means for defining ep, and 1 based on the horizontal synchronization frequency and the frequency division ratio.
The sampling time of the display pixel (one dot) is calculated, and the calculated sampling time is set as the one dot time dot_
There are provided means for substituting into time and means for outputting a numerical value obtained by calculating the following arithmetic expression 1 to the delay selector 146 as a delay amount designation signal 12a.

(Dot_time * step) / (STEP * delay) (Equation 1) where dot_time is the time of one dot, and dela
y is the delay time of the delay element 142, STEP is the total number of steps, and step is the number of phase adjustment steps.
Means the value of P.

Next, the operation of the system 100 for adjusting the delay amount of the sampling clock 14a of the video signal (a method of adjusting the delay amount of the sampling clock 14a of the video signal) according to the present embodiment will be described. FIG. 2 shows a sampling clock 14a of a video signal according to an embodiment of the present invention.
FIG. 3 is a delay amount adjustment characteristic diagram for explaining a conventional delay amount adjustment method for explaining a delay amount adjustment method for a sampling clock 14a of a video signal. First, a conventional method for adjusting the delay amount of the sampling clock 14a of a video signal will be described. Assuming that a delay of 1 ns can be obtained per step, the dot clock of the input signal is 25 MHz.
In the case of z, the time for one dot is 40 ns, so the required number of phase adjustment steps is 40 steps. However, when the input signal is 125 MHz, the time for one dot is 8 ns, so the number of necessary phase adjustment steps is eight steps. There is no problem for 8 steps, but 40 steps
In the case of steps, it is inconvenient for the user to make adjustments.

On the other hand, in the method of adjusting the delay amount of the sampling clock 14a of the video signal according to the present embodiment,
The delay amount by one step can be changed to three stages by using the delay amount adjusting means 14, and the maximum number of steps is set to ten steps. That is, one is 1 ns per step
Corresponds to a dot clock of 100 MHz or more. One is 2 ns per step, 100MHz to 50MHZ
This corresponds to the dot clock of z. One corresponds to dot lock of 50 MHz or less at 4 ns per step.
When the dot clock of the input signal is 25 MHz, 4 ns is selected per step by the delay amount adjusting means 14, so that the phase can be adjusted in 10 steps. When the dot clock of the input signal is 125 MHz, the phase can be adjusted if there is an adjustment width of 8 ns or more, and 1 ns is selected per step by the delay amount adjusting means 14, so that the phase can be adjusted in 10 steps. Become. Thus, for an input signal having various dot clocks, 10
As a result of the phase adjustment being made possible by the delay amount adjusting means 14 in steps, the user can easily adjust the phase. In the above description, the delay amount in one step can be changed to three stages by using the delay amount adjusting means 14. However, the present invention is not particularly limited to this, and the delay amount can be further divided into multiple stages by calculation. For example, by rounding up the numerical value obtained by the above arithmetic expression 1, dot_time and s
It is possible to calculate how many times the delay element requires the delay amount from the value of the step.

Finally, technical differences and effects of the present embodiment will be described in comparison with the prior art described above. First, in the present embodiment, the delay amount of the sampling clock 14a of the A / D
Irrespective of the frequency of the sampling clock 14a, regardless of the resolution of the screen (the number of display dots) and within an optimum adjustment range of the number of steps that does not greatly change the number of steps. The feature is that the amount of delay can be adjusted.

On the other hand, the second prior art described in Japanese Patent Application Laid-Open No. 10-161614 only discloses a sampling clock delay circuit in which delay circuits each having an integer multiple of delay amount are further configured in multiple stages.
Further, the characteristic configuration of the present embodiment in which the delay amount can be changed by the oscillation frequency of the PLL 16 is not disclosed. Therefore, the second prior art described in Japanese Patent Application Laid-Open No. H10-161614 cannot obtain the effect of adjusting the delay amount within the optimum adjustment range of the number of steps without largely changing the number of steps. This is another invention that is clearly different from the embodiment described above.

The second prior art described in Japanese Patent Application Laid-Open No. 10-161614 discloses a method of compactly expressing a delay line on a circuit diagram. A delay circuit having a large delay is not suitable. Because of the scale, the scale of the actual circuit is not reduced, and there is only an advantage that the circuit diagram is easy to see.

On the other hand, the present embodiment aims at keeping the number of steps of the phase adjustment of the sampling clock 14a constant regardless of the frequency of the sampling clock 14a. For example, when one clock is 8 ns, 1 ns * 8 steps, 3 ns * for 24 ns
It can be set as 8 steps. Therefore, Japanese Patent Application Laid-Open
This is fundamentally different from the second related art described in Japanese Patent No. 161614.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment,
The number, position, shape, and the like suitable for carrying out the present invention can be obtained. In each drawing, the same components are denoted by the same reference numerals.

[0019]

Since the present invention is configured as described above, the following effects can be obtained. The first effect is A
The delay amount of the sampling clock of the / D converter can be changed by the oscillation frequency of the PLL, so that the sampling clock frequency does not depend on the screen resolution (the number of display dots) and does not greatly change the number of steps regardless of the sampling clock frequency. That is, the amount of delay can be adjusted within the optimal adjustment range of the number of steps. The second effect is
That is, the amount of delay can be changed depending on the oscillation frequency of the PLL. The third effect is that the number of steps of phase adjustment of the sampling clock can be kept constant regardless of the frequency of the sampling clock.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram illustrating a system for adjusting a delay amount of a sampling clock of a video signal according to an embodiment of the present invention;

FIG. 2 is a delay amount adjustment characteristic diagram for explaining a method of adjusting a delay amount of a sampling clock of a video signal according to one embodiment of the present invention;

FIG. 3 is a delay amount adjustment characteristic diagram for describing a conventional method of adjusting a delay amount of a sampling clock of a video signal.

[Explanation of symbols]

 12 delay amount determining means 12a delay amount designating signal 14 delay amount adjusting means 142 delay element 146 delay selector 14a sampling clock 16 PLL 16a reference clock 18 A / D converter 100 delay amount adjusting system delay ... Delay time of delay element dot_time ... Time of 1 dot step ... Number of phase adjustment steps STEP ... Total number of steps

Claims (21)

[Claims] An image signal sampling clock delay amount adjusting system capable of keeping the number of steps of adjusting the phase of the sampling clock constant regardless of the frequency of the sampling clock. A delay amount adjustment system for a sampling clock of a video signal, comprising: means for changing a delay amount of one step in accordance with the delay time, and means for performing phase adjustment with a fixed total number of steps. 2. A numerical value obtained as a result of an operation of dividing a product of a time of one dot and a predetermined number of steps by a product of a total number of steps and a delay time of a delay element is rounded up to a specified number of steps. 2. The system according to claim 1, further comprising means for determining a delay amount according to the delay amount of the sampling clock of the video signal. 3. A PLL for generating and outputting a reference clock by dividing a horizontal synchronizing signal of a video signal, a delay amount determining means for generating and outputting a delay amount designating signal for designating a predetermined delay amount, Delay amount adjusting means for generating and outputting a sampling clock by adding a predetermined delay amount to the reference clock from the PLL based on the delay amount designating signal from the amount determining means; and outputting a video signal based on the sampling clock. 3. The system according to claim 1, further comprising an A / D converter for converting a digital signal into a digital signal. 4. The delay amount adjusting means generates a predetermined delay amount by selectively combining the plurality of delay elements based on a plurality of delay elements and the delay amount designation signal from the delay amount determining means. 4. The video signal sampling clock delay amount adjustment according to claim 3, further comprising a delay selector configured to generate and output the sampling clock obtained by adding the predetermined delay amount to the reference clock from the PLL. system. 5. The delay amount adjusting means defines a total number of steps, defines a delay time of the delay element, and defines a phase adjustment step number by a step number between 0 and the total number of steps. 5. The video according to claim 4, further comprising: means for calculating a one-dot sampling time from the horizontal synchronization frequency and the frequency division ratio, and substituting the calculated sampling time for the one-dot time. Signal sampling clock delay adjustment system. 6. The delay amount adjusting means includes means for outputting a numerical value obtained by calculating a predetermined arithmetic expression to the delay selector as the delay amount designating signal. 4. The system for adjusting a delay amount of a sampling clock of a video signal according to claim 1. 7. The delay amount adjustment means calculates a predetermined arithmetic expression as (time of one dot * number of phase adjustment steps) /
5. The apparatus according to claim 4, further comprising means for outputting a numerical value obtained by calculating an arithmetic expression described by (total number of steps * delay time of the delay element) to the delay selector as the delay amount designation signal. 6. The system for adjusting a delay amount of a sampling clock of a video signal according to 5. 8. A method for adjusting a delay amount of a sampling clock of a video signal, wherein the number of steps for adjusting the phase of the sampling clock can be kept constant regardless of the frequency of the sampling clock. A method of adjusting a delay amount of a sampling clock of a video signal, comprising: a step of changing a delay amount of one step in accordance with the step (a), and a step of performing phase adjustment with a fixed total number of steps. 9. A numerical value obtained as a result of an operation of dividing a product of a time of one dot and a predetermined number of steps by a product of a total number of steps and a delay time of a delay element is rounded up to a specified number of steps. 9. The method according to claim 8, further comprising the step of determining a corresponding delay amount. 10. A reference clock generating step of generating and outputting a reference clock by dividing a horizontal synchronizing signal of a video signal, and a delay amount determining step of generating and outputting a delay amount designating signal for designating a predetermined delay amount. A delay amount adjustment step of adding a predetermined delay amount to the reference clock from the reference clock generation step based on the delay amount designation signal from the delay amount determination step to generate and output a sampling clock; 10. The method according to claim 8, further comprising an A / D conversion step of converting a video signal into a digital signal based on the A / D conversion. 11. The reference clock generating step, wherein the delay amount adjusting step selectively generates a predetermined delay amount by selectively combining a plurality of delay elements based on the delay amount designating signal from the delay amount determining step. 11. The method according to claim 10, further comprising a delay selection step of generating and outputting the sampling clock obtained by adding the predetermined delay amount to the reference clock from the video signal. 12. The delay amount adjusting step includes defining a total number of steps, defining a delay time of the delay element, and defining a number of phase adjustment steps by a number of steps between 0 and the total number of steps. 12. The image according to claim 11, further comprising: calculating a one-dot sampling time from the horizontal synchronization frequency and the frequency division ratio, and substituting the calculated sampling time for the one-dot time. A method for adjusting the delay amount of the signal sampling clock. 13. The delay amount adjusting step includes a step of outputting a numerical value obtained by calculating a predetermined arithmetic expression to the delay selecting step as the delay amount designating signal. 13. The method for adjusting a delay amount of a sampling clock of a video signal according to item 12. 14. The delay amount adjusting step may be performed as follows: (1 dot time * phase adjusting step number)
A step of outputting a numerical value obtained by calculating an arithmetic expression described by // (total number of steps * delay time of delay element) to the delay select step as the delay amount designation signal. 13. The method for adjusting a delay amount of a sampling clock of a video signal according to 11 or 12. 15. A recording medium recording a sampling clock delay amount adjustment program for a video signal capable of keeping the number of steps of adjusting the phase of the sampling clock constant regardless of the frequency of the sampling clock. A program for adjusting a delay amount of a sampling clock of a video signal, comprising: a program code capable of changing a delay amount of one step according to a dot clock of the video signal; and a program code for performing phase adjustment with a fixed total number of steps. Recording medium on which is recorded. 16. A numerical value obtained as a result of an operation of dividing the product of the time of one dot and the predetermined number of steps by the product of the total number of steps and the delay time of the delay element is rounded up to the specified number of steps. The recording medium according to claim 15, further comprising a program code for determining a delay amount according to the program, wherein the delay amount adjustment program for a sampling clock of a video signal is recorded. 17. A reference clock generating program code for generating and outputting a reference clock by dividing a horizontal synchronizing signal of a video signal, and a delay amount determining program for generating and outputting a delay amount designating signal for designating a predetermined delay amount A delay amount adjustment program code for generating and outputting a sampling clock by adding a predetermined delay amount to the reference clock from the reference clock generation program code based on the delay amount designation signal from the delay amount determination program code 17. The recording method according to claim 15, further comprising an A / D conversion program code for converting a video signal into a digital signal based on the sampling clock. Medium. 18. The delay amount adjusting program code according to claim 1, wherein a predetermined delay amount is generated by selectively combining a plurality of delay elements based on the delay amount designating signal from the delay amount determining program code, and The sampling clock is generated by adding the predetermined delay amount to the reference clock from the generation program code.
18. The recording medium according to claim 17, further comprising a delay select program code to be output. 19. The delay amount adjusting program code includes a program code defining a total number of steps, a delay time of the delay element, and a phase adjusting step number between 0 and the total number of steps. And a program code for calculating a one-dot sampling time from the horizontal synchronization frequency and the frequency division ratio and substituting the calculated sampling time for the one-dot time. A recording medium on which the program for adjusting a delay amount of a sampling clock of a video signal described in 1 above is recorded. 20. The program according to claim 20, wherein the delay amount adjustment program code includes a program code for outputting a numerical value obtained by calculating a predetermined arithmetic expression to the delay select program code as the delay amount designation signal. Item 20. A recording medium on which the program for adjusting a delay amount of a sampling clock of a video signal according to Item 18 or 19 is recorded. 21. The delay amount adjustment program code is obtained by calculating a predetermined arithmetic expression as (time of one dot * number of phase adjustment steps) / (total number of steps * delay time of delay element).
20. The video signal sampling method according to claim 18, further comprising a program code for outputting a numerical value obtained by calculating an arithmetic expression described in the following as the delay amount designating signal to the delay select program code. A recording medium on which a clock delay adjustment program is recorded.