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JP2000340710A - Wiring board, semiconductor mounting device and electronic equipment - Google Patents

Wiring board, semiconductor mounting device and electronic equipment

Info

Publication number
JP2000340710A
JP2000340710A JP11151752A JP15175299A JP2000340710A JP 2000340710 A JP2000340710 A JP 2000340710A JP 11151752 A JP11151752 A JP 11151752A JP 15175299 A JP15175299 A JP 15175299A JP 2000340710 A JP2000340710 A JP 2000340710A
Authority
JP
Japan
Prior art keywords
semiconductor device
wiring
insulating substrate
substrate
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11151752A
Other languages
Japanese (ja)
Other versions
JP3379477B2 (en
Inventor
Takashi Tanaka
敬 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15175299A priority Critical patent/JP3379477B2/en
Publication of JP2000340710A publication Critical patent/JP2000340710A/en
Application granted granted Critical
Publication of JP3379477B2 publication Critical patent/JP3379477B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board, which is highly reliable to mechanical stresses and can be mounted at a high density. SOLUTION: A plurality of connection pads 4 are provided on the surface, which is mounted with a rectangular semiconductor unit 2, of a glass epoxy substrate in a dotted type in the state corresponding to external terminals 3 under the unit 2. Substrate wirings 6 for electrically connecting with other electronic component through the pads 4 are led out in the opposite directions to the directions of the one pair of the sides 2A and 2C opposing each other of a mounting region 2E and are formed. The number of the lead-out sides of the region 2E can be reduced, there is no need to ensure the laying space for the substrate wirings 6, components adjacent to the substrate wirings 6 can be arranged at the positions, where the wirings 6 are not led out, and a high-density mounting can be performed on a wiring board.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の外部
端子が接続される接続パッドから基板配線を引き出し形
成した配線基板、この配線基板に半導体装置を実装した
半導体実装装置、および、これら配線基板あるいは半導
体実装装置が配設された電子機器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board formed by drawing substrate wiring from connection pads to which external terminals of a semiconductor device are connected, a semiconductor mounting device having the semiconductor device mounted on the wiring board, and these wiring boards. Alternatively, the present invention relates to an electronic device provided with a semiconductor mounting device.

【0002】[0002]

【従来の技術】従来、配線基板および配線基板上へ半導
体装置を実装したものとして、例えば図10に示すよう
な特開平10−284846号公報に記載の構成が知ら
れている。
2. Description of the Related Art Conventionally, as a wiring board and a semiconductor device mounted on the wiring board, for example, a configuration disclosed in Japanese Patent Application Laid-Open No. 10-284846 as shown in FIG. 10 is known.

【0003】この図10に示すような特開平10−28
4846号公報に記載のものは、配線基板22上にドッ
ト状に複数形成された接続パッド33,34から引き出
される他の電子部品への基板配線29が、矩形の半導体
装置21の実装エリア23の4辺全部の方向に引き出さ
れている。
[0003] As shown in FIG.
No. 4,846, the board wiring 29 to another electronic component drawn out from a plurality of connection pads 33 and 34 formed in a dot shape on the wiring board 22 is formed in the mounting area 23 of the rectangular semiconductor device 21. It is pulled out in all four sides.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記図
10に示すような特開平10−284846号公報に記
載のものでは、半導体装置21の実装エリア23からさ
らに引き出された基板配線29のスペースにより、この
基板配線29の部分には隣接部品を配置することができ
ない。このため、実装密度を上げることができない。
However, in the device described in Japanese Patent Application Laid-Open No. H10-284846 as shown in FIG. 10, the space of the substrate wiring 29 further drawn out from the mounting area 23 of the semiconductor device 21 is reduced. Adjacent components cannot be arranged in the portion of the board wiring 29. For this reason, the mounting density cannot be increased.

【0005】また、4方向に基板配線29が引き出され
ているため、例えば携帯電子機器に採用した場合、携帯
電子機器本体に曲げなどの機械的ストレスが繰り返し加
わった際に、曲げ応力の発生する方向と基板配線29の
引き出し方向が一致すると、この一致した部分の基板配
線29に接続されている接続パッド33,34の接続部
分の付け根部分で断線しやすくなる。このため、半導体
装置21を実装した構造において、曲げなどの機械的ス
トレスに対する装置信頼性のさらなる向上が図りにくい
問題がある。
Further, since the board wiring 29 is drawn out in four directions, for example, when employed in portable electronic equipment, bending stress is generated when mechanical stress such as bending is repeatedly applied to the portable electronic equipment body. If the direction and the drawing direction of the board wiring 29 match, it is easy to break at the base of the connection portion of the connection pads 33 and 34 connected to the board wiring 29 in the matched portion. For this reason, in the structure in which the semiconductor device 21 is mounted, there is a problem that it is difficult to further improve the device reliability against mechanical stress such as bending.

【0006】本発明は、このような点に鑑みなされたも
ので、機械的ストレスに対して高い信頼性が得られ高密
度な実装が可能な配線基板、半導体実装装置および電子
機器を提供することを目的とする。
The present invention has been made in view of the above circumstances, and provides a wiring board, a semiconductor mounting apparatus, and an electronic apparatus which can obtain high reliability against mechanical stress and can be mounted at a high density. With the goal.

【0007】[0007]

【課題を解決するための手段】請求項1記載の配線基板
は、外部端子を有した略矩形の半導体装置が実装される
絶縁基板と、この絶縁基板の少なくとも前記半導体装置
が実装される面に設けられ前記半導体装置の外部端子が
電気的かつ機械的に接続される接続パッドと、この接続
パッドに接続され前記半導体装置が実装される実装エリ
アの多くとも3つの辺から引き出し形成される基板配線
とを具備したものである。請求項2記載の配線基板は、
外部端子を有した略矩形の半導体装置が実装されこの半
導体装置が実装される面から反対側の面に亘って貫通す
るスルーホールを有した絶縁基板と、この絶縁基板の前
記半導体装置が実装される面から前記スルーホールの内
周面を介して前記絶縁基板の反対側の面に亘って設けら
れ前記半導体装置の外部端子が電気的かつ機械的に接続
される接続パッドと、前記絶縁基板の反対側の面に位置
して前記スルーホールの内周面を介して前記接続パッド
に接続されて前記半導体装置が実装される実装エリアか
ら引き出し形成された基板配線とを具備したものであ
る。請求項3記載の配線基板は、外部端子を有した略矩
形の半導体装置が実装されこの半導体装置が実装される
面に開口する凹状のビアホールを有した絶縁基板と、こ
の絶縁基板の前記半導体装置が実装される面から前記ビ
アホールの内周面に亘って設けられ前記半導体装置の外
部端子が電気的かつ機械的に接続される接続パッドと、
前記絶縁基板の中間層に位置して前記ビアホールの内周
面を介して前記接続パッドに接続されて前記絶縁基板の
平面方向に沿って前記半導体装置が実装される実装エリ
アから引き出し形成された基板配線とを具備したもので
ある。請求項4記載の配線基板は、外部端子を有した略
矩形の半導体装置が実装され、この半導体装置が実装さ
れる面から反対側の面に亘って貫通するスルーホールお
よび前記半導体装置が実装される面に開口する凹状のビ
アホールを有した絶縁基板と、この絶縁基板の前記半導
体装置が実装される面から前記スルーホールの内周面を
介して前記絶縁基板の反対側の面に亘って設けられると
ともに、絶縁基板の前記半導体装置が実装される面から
前記ビアホールの内周面に亘って設けられ、前記前記半
導体装置の外部端子が電気的かつ機械的に接続される接
続パッドと、前記絶縁基板の反対側の面および前記絶縁
基板の中間層の少なくともいずれか一方に位置して前記
スルーホールおよび前記ビアホールの内周面の少なくと
もいずれか一方を介して前記接続パッドに接続され、前
記半導体装置が実装される実装エリアから前記絶縁基板
の平面方向に沿って引き出し形成された基板配線とを具
備したものである。請求項5記載の配線基板は、請求項
2ないし4のいずれか一に記載の配線基板において、基
板配線は、実装エリアの多くとも3つの辺から引き出し
形成されたものである。請求項6記載の配線基板は、請
求項1ないし5のいずれか一に記載の配線基板におい
て、基板配線は、実装エリアの対向する一対の辺から引
き出し形成されたものである。請求項7記載の配線基板
は、請求項1ないし6のいずれか一に記載の配線基板に
おいて、接続パッドおよび基板配線は、それぞ複数設け
られ、前記基板配線の全数に対する少なくとも80%の
数が、実装エリアの所定の辺から引き出し形成されたも
のである。請求項8記載の配線基板は、請求項1ないし
7のいずれか一に記載の配線基板において、絶縁基板
は、長手状に形成され、基板配線は、前記絶縁基板の長
手方向に対して交差する方向に引き出し形成されたもの
である。請求項9記載の半導体実装装置は、請求項1な
いし8のいずれか一に記載の配線基板と、この配線基板
に実装された半導体装置とを具備したものである。請求
項10記載の半導体実装装置は、請求項9記載の半導体
実装装置において、半導体装置と配線基板との間には、
樹脂材料が充填されたものである。請求項11記載の電
子機器は、本体ケースと、この本体ケース内に配設され
た請求項1ないし8のいずれか一に記載の配線基板およ
び請求項9または10記載の半導体実装装置の少なくと
もいずれか一方とを具備したものである。請求項12記
載の電子機器は、請求項11記載の電子機器において、
本体ケースは、長手状に形成され、この本体ケースに請
求項8記載の配線基板が長手方向を前記本体ケースの長
手方向に沿って配設されたものである。
According to a first aspect of the present invention, there is provided a wiring board including an insulating substrate on which a substantially rectangular semiconductor device having external terminals is mounted, and at least a surface of the insulating substrate on which the semiconductor device is mounted. A connection pad provided to electrically and mechanically connect external terminals of the semiconductor device, and a substrate wiring connected to the connection pad and drawn out from at most three sides of a mounting area where the semiconductor device is mounted Is provided. The wiring board according to claim 2,
A substantially rectangular semiconductor device having external terminals is mounted, and an insulating substrate having a through hole extending from a surface on which the semiconductor device is mounted to an opposite surface, and the semiconductor device of the insulating substrate is mounted. A connection pad which is provided from the surface of the insulating substrate through the inner peripheral surface of the through hole to the surface on the opposite side of the insulating substrate, and to which external terminals of the semiconductor device are electrically and mechanically connected; And a substrate wiring which is located on the opposite surface, is connected to the connection pad via an inner peripheral surface of the through hole, and is drawn out from a mounting area where the semiconductor device is mounted. 4. The wiring board according to claim 3, wherein the insulating substrate has a substantially rectangular semiconductor device having external terminals mounted thereon, the insulating substrate having a concave via hole opened on a surface on which the semiconductor device is mounted, and the semiconductor device having the insulating substrate. A connection pad that is provided from the surface on which the via hole is mounted to the inner peripheral surface of the via hole, and external terminals of the semiconductor device are electrically and mechanically connected;
A substrate which is connected to the connection pad via an inner peripheral surface of the via hole and is drawn out of a mounting area where the semiconductor device is mounted along a plane direction of the insulating substrate, which is located in an intermediate layer of the insulating substrate; And wiring. The wiring board according to claim 4, wherein a substantially rectangular semiconductor device having external terminals is mounted, a through hole penetrating from a surface on which the semiconductor device is mounted to a surface on the opposite side, and the semiconductor device is mounted. An insulating substrate having a concave via hole opening in a surface of the insulating substrate, and an insulating substrate provided from the surface of the insulating substrate on which the semiconductor device is mounted to the surface on the opposite side of the insulating substrate via the inner peripheral surface of the through hole. A connection pad that is provided from a surface of the insulating substrate on which the semiconductor device is mounted to an inner peripheral surface of the via hole, and that electrically and mechanically connects external terminals of the semiconductor device; Through at least one of the inner peripheral surface of the through hole and the via hole located on at least one of the opposite surface of the substrate and the intermediate layer of the insulating substrate Serial connected to the connection pad, is obtained by including a said semiconductor device substrate wiring is drawn out formed along a plane direction of the insulating substrate from the mounting area to be mounted. According to a fifth aspect of the present invention, there is provided the wiring board according to any one of the second to fourth aspects, wherein the board wiring is formed by drawing out from at most three sides of the mounting area. A wiring board according to a sixth aspect is the wiring board according to any one of the first to fifth aspects, wherein the board wiring is formed by being drawn out from a pair of opposite sides of the mounting area. According to a seventh aspect of the present invention, in the wiring board according to any one of the first to sixth aspects, a plurality of connection pads and a plurality of substrate wirings are provided, and at least 80% of the total number of the substrate wirings is provided. , Which are drawn out from predetermined sides of the mounting area. According to a eighth aspect of the present invention, in the wiring board according to any one of the first to seventh aspects, the insulating substrate is formed in a longitudinal shape, and the substrate wiring crosses the longitudinal direction of the insulating substrate. It is drawn out in the direction. According to a ninth aspect of the present invention, there is provided a semiconductor mounting device including the wiring substrate according to any one of the first to eighth aspects, and a semiconductor device mounted on the wiring substrate. The semiconductor mounting device according to claim 10 is the semiconductor mounting device according to claim 9, wherein a distance between the semiconductor device and the wiring board is
It is filled with a resin material. An electronic device according to claim 11 is a main body case, at least one of a wiring board according to any one of claims 1 to 8 and a semiconductor mounting device according to claim 9 or 10 provided in the main body case. Or one of them. The electronic device according to claim 12 is the electronic device according to claim 11,
The main body case is formed in a longitudinal shape, and the wiring board according to claim 8 is disposed on the main body case along a longitudinal direction of the main body case.

【0008】[0008]

【発明の実施の形態】次に、本発明の一実施の形態を示
す半導体実装装置の構成を図面に基づいて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a configuration of a semiconductor mounting device according to an embodiment of the present invention will be described with reference to the drawings.

【0009】図1は、本発明の一実施の形態に係る配線
基板を示す平面図である。図2は、同上の半導体実装装
置を示す断面図である。
FIG. 1 is a plan view showing a wiring board according to an embodiment of the present invention. FIG. 2 is a sectional view showing the semiconductor mounting device according to the first embodiment.

【0010】図1において、配線基板1上の半導体装置
2が実装される実装エリア2Eには、半導体装置2の外
部端子3の配列に対応して同配列で配設された接続パッ
ド4が複数ドット状に形成されいる。この配線基板1
は、例えば絶縁基板としてのガラスエポキシ基板が用い
られる。そして、このガラスエポキシ基板上に、実装さ
れる半導体装置2の複数の外部端子3に対応する位置
に、例えば銅にてドット状に接続パッド4が複数設けら
れている。なお、半導体装置2が1.27mmピッチの
BGA(Ball Glid Array)の場合は、
接続パッド4は直径が約630μm前後の大きさで形成
される。
In FIG. 1, a plurality of connection pads 4 arranged in the same arrangement corresponding to the arrangement of the external terminals 3 of the semiconductor device 2 are provided in a mounting area 2E where the semiconductor device 2 on the wiring board 1 is mounted. It is formed in a dot shape. This wiring board 1
For example, a glass epoxy substrate as an insulating substrate is used. On the glass epoxy substrate, a plurality of dot-like connection pads 4 are provided, for example, with copper at positions corresponding to the plurality of external terminals 3 of the semiconductor device 2 to be mounted. When the semiconductor device 2 is a 1.27 mm pitch BGA (Ball Grid Array),
The connection pad 4 has a diameter of about 630 μm.

【0011】また、これら接続パッド4には、図示しな
い他の電子部品と電気的に接続するための基板配線6が
それぞれ引き出し形成されている。これら基板配線6
は、接続パッド4と同様に銅にて形成され、実装される
矩形の半導体装置2の辺に対応した対向する辺2A,2
Cの方向へ反対方向に引き出され、他の電子部品5と電
気的に接続される。なお、基板配線6は、配線基板1の
厚さ方向には引き出し形成されていない。
Further, board wirings 6 for electrically connecting to other electronic components (not shown) are drawn out from these connection pads 4 respectively. These board wiring 6
Are opposite sides 2A, 2A formed of copper similarly to the connection pads 4 and corresponding to the sides of the rectangular semiconductor device 2 to be mounted.
It is pulled out in the direction opposite to the direction C and is electrically connected to another electronic component 5. The board wiring 6 is not drawn out in the thickness direction of the wiring board 1.

【0012】そして、半導体装置2の実装面側に形成さ
れた外部端子3と、配線基板1に形成された接続パッド
4がはんだボール7により接続され、配線基板1と半導
体装置2とが電気的かつ機械的に接続され、図2に示す
ように半導体実装装置が構成される。
Then, the external terminals 3 formed on the mounting surface side of the semiconductor device 2 and the connection pads 4 formed on the wiring board 1 are connected by solder balls 7, and the wiring board 1 and the semiconductor device 2 are electrically connected. In addition, they are mechanically connected to form a semiconductor mounting device as shown in FIG.

【0013】次に、上記実施の形態の動作を説明する。Next, the operation of the above embodiment will be described.

【0014】実装される半導体装置2の外部端子3に対
応して配線基板1に設けた接続パッド4に、他の電子部
品5と電気的に接続する基板配線6を、半導体装置2の
辺に対応した対向する辺2A,2Cの方向へ反対方向に
引き出し形成する。
On the connection pads 4 provided on the wiring board 1 corresponding to the external terminals 3 of the semiconductor device 2 to be mounted, board wirings 6 electrically connected to other electronic components 5 are provided on the sides of the semiconductor device 2. It is formed so as to be drawn in the opposite direction to the corresponding opposite sides 2A and 2C.

【0015】このように、半導体装置2の実装エリア2
Eから外部に基板配線6が引き出される辺の数を少なく
することにより、基板配線6の引き出されていない辺2
B,2Dに対応する位置には基板配線6の引き回しスペ
ースを確保する必要がなく、この基板配線6の引き出さ
れていない辺2B,2Dに対応する位置に隣接部品を配
置することが可能となり、高密度な実装ができる。
As described above, the mounting area 2 of the semiconductor device 2
By reducing the number of sides from which the board wiring 6 is drawn out from E to the outside, the side 2 from which the board wiring 6 is not drawn out is reduced.
There is no need to secure a space for leading the board wiring 6 at the positions corresponding to B and 2D, and it is possible to arrange adjacent components at positions corresponding to the sides 2B and 2D where the board wiring 6 is not drawn out. High-density mounting is possible.

【0016】また、上記配線基板1を例えば携帯電子機
器などに採用した場合において、携帯電子機器に曲げな
どの外部からの機械的なストレスが繰り返し加わるなど
して、生じる曲げ応力の発生する方向が基板配線6の引
き出し方向と直交する場合には、機械的ストレスにより
基板配線6の接続パッド4との付け根部分である引き出
し部分に断線が生じることを抑制できる。このことか
ら、上記配線基板1の基板配線6の引き出される辺の数
を少なく設計することにより、曲げ応力の発生する方向
と基板配線6の引き出される方向とが略平行となりにく
くなり断線が生じる確率が低減でき、採用した携帯電子
機器の品質の信頼性も向上できる。
When the wiring board 1 is used in, for example, a portable electronic device, the direction in which the bending stress is generated due to repeated mechanical stress such as bending applied to the portable electronic device. When the direction is perpendicular to the direction in which the board wiring 6 is drawn out, it is possible to suppress the occurrence of disconnection in the drawn-out part of the board wiring 6 which is the base part with the connection pad 4 due to mechanical stress. Therefore, by designing the number of sides from which the board wiring 6 is drawn out of the wiring board 1 to a small number, the direction in which the bending stress is generated and the direction in which the board wiring 6 is drawn out are unlikely to be substantially parallel, and the probability of occurrence of disconnection is increased. And the reliability of the quality of the adopted portable electronic device can be improved.

【0017】なお、携帯電子機器の形状により、曲げ応
力の発生しやすい方向がほぼ決定されるので、あらかじ
め曲げ応力の発生する方向と基板配線6の引き出される
方向とが直交するように配線基板1を携帯電子機器に配
設することは容易である。
Since the direction in which bending stress is likely to be generated is substantially determined by the shape of the portable electronic device, the wiring board 1 is set so that the direction in which bending stress is generated and the direction in which the board wiring 6 is drawn out are orthogonal to each other. It is easy to arrange in a portable electronic device.

【0018】すなわち、例えば電子機器が、携帯電話な
どの携帯型の通信機などのように、図3に示すように縦
横長さの比が大きい長方形状で、内部に組み込まれる配
線基板1も同様に縦横長さの比が大きい形状、例えば長
手方向とこの長手方向に直交する方向との長さの比が
1.5:1 〜4:1(携帯電話の場合は通常3:1〜
4:1、折り込み可能な携帯電話の場合は通常1.5:
1〜2:1)である場合、図4に示すように電子機器に
長手方向穂の曲げストレスなどの機械的ストレスが繰り
返し加わる場合がある。これに伴って、配線基板1にも
同様の曲げストレスなどの機械的ストレスが加わる。
That is, for example, as shown in FIG. 3, the electronic device has a rectangular shape having a large vertical and horizontal length, such as a portable communication device such as a mobile phone, and the wiring board 1 incorporated therein is also similar. In the case of a shape having a large length-width ratio, for example, the length ratio between the longitudinal direction and the direction orthogonal to the longitudinal direction is 1.5: 1 to 4: 1 (in the case of a mobile phone, usually 3: 1 to 4: 1)
4: 1, typically 1.5: for foldable mobile phones
In the case of (1: 1 to 2: 1), mechanical stress such as bending stress in the longitudinal direction ear may be repeatedly applied to the electronic device as shown in FIG. Along with this, similar mechanical stress such as bending stress is applied to the wiring board 1.

【0019】このような縦横長さ比が比較的大きく曲げ
ストレスなどがほとんど図4の矢印方向にのみ加わる場
合、基板配線6はこの曲げストレスが加わる方向に沿っ
た配線基板1の長手方向に沿って引き出し形成すること
なく、図3に示すように曲げストレスの加わる方向と交
差する方向、例えば直交する方向へのみ引き出し形成す
ることにより、図4に示すように曲げストレスが加わっ
ても、基板配線6の接続パッド4との接続部分である付
け根部分に断線が生じることを抑制できる。
When such an aspect ratio is relatively large and bending stress or the like is applied almost only in the direction of the arrow in FIG. 4, the substrate wiring 6 extends along the longitudinal direction of the wiring board 1 along the direction in which the bending stress is applied. By drawing out only in a direction intersecting the direction in which the bending stress is applied as shown in FIG. 3, for example, in a direction perpendicular to the direction in which the bending stress is applied as shown in FIG. 3, even if the bending stress is applied as shown in FIG. It is possible to suppress the occurrence of disconnection at the base portion, which is the connection portion with the connection pad 4 of FIG.

【0020】すなわち、機械的ストレスの加わりが小さ
い方向に基板配線6を引き出し形成するとよい。
That is, it is preferable to draw out the substrate wiring 6 in a direction in which the application of mechanical stress is small.

【0021】なお、上記図1および図2に示す実施の形
態において、実装エリア2Eの対向する一対の辺2A,
2Cの位置から基板配線6を反対方向に引き出し形成し
て説明したが、例えば辺2A,2Bなどの隣接する辺か
ら引き出したり、1つの辺以外の3つの辺から引き出し
たり、1つの辺のみから引き出し形成するなどしても、
高密度な実装が得られる点で同様の効果を奏する。
In the embodiment shown in FIGS. 1 and 2, a pair of opposing sides 2A, 2A,
In the description, the substrate wiring 6 is drawn out from the position 2C in the opposite direction, but it is drawn out from adjacent sides such as sides 2A and 2B, drawn out from three sides other than one side, or drawn out from only one side. Even if drawers are formed,
A similar effect is obtained in that high-density mounting can be obtained.

【0022】また、1つの辺の位置のみから引き出し形
成する構成では、同様に、外部からの機械的ストレスに
より生じる曲げ応力の方向と、引き出し方向とが略平行
となりにくくなり、基板配線6の接続パッド4との付け
根部分である引き出し部分に断線が生じることを抑制で
き、配線基板1を配設した電子機器の品質の信頼性を向
上できるという効果も奏する。
Further, in the configuration in which the wiring is drawn out only from the position of one side, the direction of the bending stress generated by the mechanical stress from the outside is unlikely to be substantially parallel to the drawing out direction. It is possible to suppress the occurrence of disconnection in the lead-out portion that is the base portion with the pad 4, and it is possible to improve the reliability of the quality of the electronic device provided with the wiring board 1.

【0023】次に、本発明の他の実施の形態を図面に基
づいて説明する。
Next, another embodiment of the present invention will be described with reference to the drawings.

【0024】図5は、本発明の他の実施の形態に係る配
線基板を示す平面図である。図6は、同上の半導体実装
装置を示す断面図である。
FIG. 5 is a plan view showing a wiring board according to another embodiment of the present invention. FIG. 6 is a sectional view showing the semiconductor mounting device according to the first embodiment.

【0025】図5において、配線基板1は、図1および
図2に示す実施の形態の配線基板1と同様に、例えばガ
ラスエポキシ基板にて形成され、半導体装置2が実装さ
れる実装面である表面、裏面および表面と裏面との間の
中間層を備えた積層状に構成されている。そして、この
配線基板1には、表面から裏面に亘って貫通するスルー
ホール8および表面から中間層に有底状に開口するビア
ホール9が、実装される半導体装置2の複数の外部端子
3に対応する位置に複数設けられている。
In FIG. 5, the wiring board 1 is formed of, for example, a glass epoxy board and is a mounting surface on which the semiconductor device 2 is mounted, similarly to the wiring board 1 of the embodiment shown in FIGS. It is configured in a laminate with a front surface, a back surface, and an intermediate layer between the front and back surfaces. In the wiring board 1, a through hole 8 penetrating from the front surface to the back surface and a via hole 9 opening from the front surface to the intermediate layer with a bottom correspond to the plurality of external terminals 3 of the semiconductor device 2 to be mounted. Are provided at different positions.

【0026】また、配線基板1には、表面に位置してド
ット状でスルーホール8およびビアホール9の内周面に
亘って連続する接続パッド4がそれぞれ設けられ、表面
配線層が形成されている。
The wiring substrate 1 is provided with connection pads 4 which are located on the surface and are continuous in dot form over the inner peripheral surfaces of the through hole 8 and the via hole 9, respectively, and a surface wiring layer is formed. .

【0027】さらに、配線基板1の裏面には、スルーホ
ール8の内周面に設けられた各接続パッド4にそれぞれ
接続されて図示しない他の電子部品5と電気的に接続す
るための基板配線6が複数引き出し形成されて裏面配線
層が形成されている。
Further, on the rear surface of the wiring board 1, there are provided substrate wirings respectively connected to the respective connection pads 4 provided on the inner peripheral surface of the through hole 8 and electrically connected to other electronic components 5 not shown. 6 are drawn out to form a backside wiring layer.

【0028】また、配線基板1の中間層には、ビアホー
ル9の内周面に設けられた各接続パッド4にそれぞれ接
続されて図示しない他の電子部品5と電気的に接続する
ための配線基板1の平面方向に沿って基板配線6が複数
引き出し形成され、表面配線層および裏面配線層と略平
行な中間配線層が形成されて配線基板1が積層状に形成
されている。
In the intermediate layer of the wiring board 1, a wiring board connected to each connection pad 4 provided on the inner peripheral surface of the via hole 9 and electrically connected to another electronic component 5 (not shown) A plurality of substrate wirings 6 are drawn out along the direction of the plane 1, an intermediate wiring layer substantially parallel to the front surface wiring layer and the back surface wiring layer is formed, and the wiring substrate 1 is formed in a laminated shape.

【0029】なお、表面配線層には基板配線6が設けら
れておらず、裏面配線層および中間配線層に設けられた
基板配線6は、半導体装置2が実装される実装エリア2
Eの4つの辺2A,2B,2C,2D全ての方向から外
部に引き出し形成されている。
Note that the substrate wiring 6 is not provided on the front wiring layer, and the substrate wiring 6 provided on the back wiring layer and the intermediate wiring layer is provided in the mounting area 2 on which the semiconductor device 2 is mounted.
E is drawn out from all four sides 2A, 2B, 2C and 2D to the outside.

【0030】そして、半導体装置2の実装面側に形成さ
れた外部端子3が、配線基板1に形成された接続パッド
4の表面配線層側にはんだボール7により接続されて配
線基板1と半導体装置2とが電気的かつ機械的に接続さ
れ、図6に示すように半導体実装装置が構成される。
Then, the external terminals 3 formed on the mounting surface side of the semiconductor device 2 are connected to the surface wiring layer side of the connection pads 4 formed on the wiring substrate 1 by solder balls 7 so that the wiring substrate 1 and the semiconductor device 2 are electrically and mechanically connected to each other to form a semiconductor mounting device as shown in FIG.

【0031】この図5および図6に示す実施の形態で
は、半導体装置2が実装される表面配線層に実装エリア
2Eから外部へ引き出される基板配線6が設けられてい
ないので、実装面となる表面配線層に基板配線6の引き
回しのスペースを確保する必要がなく、この基板配線6
の引き出されていない4つの全ての辺2A,2B,2
C,2Dに対応する位置に隣接部品を配置することが可
能となり、さらに高密度な実装ができる。
In the embodiment shown in FIGS. 5 and 6, the surface wiring layer on which the semiconductor device 2 is mounted is not provided with the substrate wiring 6 which is drawn out from the mounting area 2E to the outside. There is no need to secure a space for routing the substrate wiring 6 in the wiring layer.
All four sides 2A, 2B, 2 of
Adjacent components can be arranged at positions corresponding to C and 2D, and higher-density mounting can be achieved.

【0032】また、基板配線6を積層状に位置して設け
るため、図1および図2に示す実施の形態の1つの層の
みに基板配線6を設ける構成に比して、基板配線6の配
線間隔を広く設計でき、基板配線6どうしの短絡などを
防止できる一方、より端子ピッチの狭い半導体装置2や
外部端子3の多い半導体装置2でも適用できる。
Further, since the substrate wiring 6 is provided in a laminated state, the wiring of the substrate wiring 6 is different from the configuration in which the substrate wiring 6 is provided only in one layer in the embodiment shown in FIGS. While the spacing can be designed to be wide and short circuit between the substrate wirings 6 can be prevented, the present invention can be applied to the semiconductor device 2 having a narrower terminal pitch or the semiconductor device 2 having many external terminals 3.

【0033】そして、基板配線6が設けられていない表
面配線層側が曲げストレスの掛かりやすい面であるよう
に電子機器内に配線基板1が配設されざるを得ない場合
において、基板配線6が設けられる中間配線層および裏
面配線層は生じる曲げストレスが比較的小さくなり、よ
り断線を抑制できる。
In a case where the wiring board 1 must be provided in the electronic device so that the surface wiring layer side on which the board wiring 6 is not provided is a surface on which bending stress is easily applied, the board wiring 6 is provided. In the intermediate wiring layer and the rear wiring layer to be formed, the bending stress generated is relatively small, and the disconnection can be further suppressed.

【0034】なお、上記図5および図6に示す実施の形
態において、実装エリア2Eの4つの全ての辺2A,2
B,2C,2Dの位置から基板配線6を引き出し形成し
て説明したが、例えば図7に示すように、図1および図
2に示す実施の形態と同様に対向する一対の辺2A,2
Cの位置から引き出し形成したり、1つの辺のみから引
き出し形成したり、3つの辺から引き出し形成したり、
隣接する辺の位置から引き出し形成しても、高密度な実
装が得られる点で同様の効果を奏する。
In the embodiment shown in FIGS. 5 and 6, all four sides 2A, 2A of mounting area 2E are set.
In the description, the substrate wiring 6 is drawn out from the positions of B, 2C, and 2D. However, as shown in FIG. 7, for example, a pair of opposing sides 2A, 2A are similar to the embodiment shown in FIGS.
It can be drawn out from the position C, drawn out from only one side, drawn out from three sides,
A similar effect can be obtained in that a high-density mounting can be obtained even when drawing out from the position of the adjacent side.

【0035】さらに、対向する一対の辺の位置から引き
出し形成する構成、あるいは、1つの辺の位置から引き
出し形成する構成によれば、外部からの機械的ストレス
により生じる曲げ応力の方向と、引き出し方向とが略平
行となりにくくなり、基板配線6の接続パッド4との付
け根部分である引き出し部分に断線が生じることを抑制
でき、配線基板1を配設した電子機器の品質の信頼性を
向上できるという効果も奏する。
Further, according to the configuration of drawing out from the position of a pair of opposing sides or the configuration of drawing out from the position of one side, the direction of bending stress generated by external mechanical stress and the direction of drawing out Are not substantially parallel to each other, and it is possible to suppress the occurrence of disconnection in the lead-out portion, which is the root portion of the board wiring 6 with the connection pad 4, and to improve the reliability of the quality of the electronic device provided with the wiring board 1. It also has an effect.

【0036】また、スルーホール8およびビアホール9
の双方を設け、中間配線層および裏面配線層の双方に基
板配線6を設けて説明したが、素ルール8のみを設けて
裏面配線層のみ基板配線6を設けたり、ビアホール9の
みを設けて中間配線層のみに基板配線6を設けてもよ
い。
The through hole 8 and the via hole 9
In the description, the substrate wiring 6 is provided on both the intermediate wiring layer and the rear wiring layer. However, only the elementary rule 8 is provided and the substrate wiring 6 is provided only on the rear wiring layer, or only the via hole 9 is provided. The substrate wiring 6 may be provided only on the wiring layer.

【0037】この図5および図6の実施の形態で示すよ
うに、基板配線設計上の制約が有り、図1および図2に
示す実施の形態のように、基板配線6を全く引き出し形
成しない方向を設けることができない場合、制約がある
方向へは、全基板配線6の数の20%以下とするとよ
い。例えば、外部端子3の数が100ピンの半導体装置
2の場合、図1および図2に示す実施の形態のように引
き出す方向へはそれぞれ50本ずつとするが、上記図5
および図6の実施の形態のように基板配線設計上の制約
がある場合には、引き出しを多くする辺では合わせて8
0本以上とし、引き出しを少なくする辺では合わせて2
0本以下とすると、基板配線6の付け根部分の断線を比
較的抑制できる。
As shown in the embodiments of FIGS. 5 and 6, there is a restriction on the substrate wiring design, and the direction in which the substrate wiring 6 is not drawn out at all as in the embodiment shown in FIGS. When it is not possible to provide the wiring, it is preferable to set the number to 20% or less of the number of all the board wirings 6 in the direction in which there is a restriction. For example, when the number of the external terminals 3 is 100 pins, the semiconductor device 2 has 50 pins in each of the drawing directions as in the embodiment shown in FIGS.
In addition, when there are restrictions on the board wiring design as in the embodiment of FIG.
0 or more, 2 on the side where drawers are reduced
When the number is zero or less, disconnection at the base of the board wiring 6 can be relatively suppressed.

【0038】また、基板配線設計上の制約が大きく、こ
のように引き出す割合を異ならせることができない場合
には、コーナ近傍の基板配線6をこのように考慮する
と、比較的に基板配線6の付け根部分での断線を抑制で
きる。
In addition, when there is a great restriction on the design of the substrate wiring and it is not possible to make the ratio of drawing out different in this way, considering the substrate wiring 6 near the corner in this way, the base of the substrate wiring 6 is relatively large. Disconnection at a part can be suppressed.

【0039】次に、本発明のさらに他の実施の形態を図
面に基づいて説明する。
Next, still another embodiment of the present invention will be described with reference to the drawings.

【0040】図8は、本発明のさらに他の実施の形態に
係る配線基板を示す平面図である。図9は、同上の半導
体実装装置を示す断面図である。
FIG. 8 is a plan view showing a wiring board according to still another embodiment of the present invention. FIG. 9 is a cross-sectional view showing the semiconductor mounting device of the above.

【0041】この図8および図9に示す実施の形態は、
上記図5および図6に示す実施の形態における表面配線
層にも接続パッド4に接続する基板配線6を設けたもの
である。
The embodiment shown in FIG. 8 and FIG.
The substrate wiring 6 connected to the connection pad 4 is also provided on the surface wiring layer in the embodiment shown in FIGS.

【0042】なお、表面配線層、中間配線層および裏面
配線層にそれぞれ設けられた基板配線6は、図1および
図2に示す実施の形態、および図7に示す実施の形態と
同様に、実装エリア2Eの対向する一対の辺2A,2C
の位置からそれぞれ反対方向に引き出し形成されてい
る。
The substrate wirings 6 provided on the front wiring layer, the intermediate wiring layer and the rear wiring layer, respectively, are mounted similarly to the embodiment shown in FIGS. 1 and 2 and the embodiment shown in FIG. A pair of opposite sides 2A and 2C of the area 2E
Are drawn out in the opposite directions from the respective positions.

【0043】この図8および図9に示す実施の形態で
は、図1および図2に示す実施の形態と同様に、外部か
らの機械的ストレスにより生じる曲げ応力の方向と、引
き出し方向とが略平行となりにくくなり、基板配線6の
接続パッド4との付け根部分である引き出し部分に断線
が生じることを抑制でき、配線基板1を配設した電子機
器の品質の信頼性を向上できる。
In the embodiment shown in FIGS. 8 and 9, similarly to the embodiment shown in FIGS. 1 and 2, the direction of the bending stress generated by external mechanical stress is substantially parallel to the drawing direction. It is possible to suppress the occurrence of disconnection in the lead-out portion, which is the base portion of the board wiring 6 with the connection pad 4, and to improve the reliability of the quality of the electronic device provided with the wiring board 1.

【0044】また、図5および図6に示す実施の形態と
同様に、複数の層に基板配線6を設けたため、基板配線
6の配線間隔を広く設計でき、基板配線6どうしの短絡
などを防止できる一方、より端子ピッチの狭い半導体装
置2や外部端子3の多い半導体装置2でも適用できる。
Also, as in the embodiment shown in FIGS. 5 and 6, the substrate wirings 6 are provided in a plurality of layers, so that the wiring intervals between the substrate wirings 6 can be designed to be wide, and a short circuit between the substrate wirings 6 can be prevented. On the other hand, the present invention can be applied to a semiconductor device 2 having a narrower terminal pitch or a semiconductor device 2 having many external terminals 3.

【0045】なお、この図8および図9に示す実施の形
態において、実装エリア2Eの対向する一対の辺2A,
2Cの位置から基板配線6を反対方向に引き出し形成し
て説明したが、例えば辺2A,2Bなどの隣接する辺か
ら引き出したり、1つの辺以外の3つの辺から引き出し
たり、1つの辺のみから引き出し形成するなどしても、
高密度な実装が得られる点で同様の効果を奏する。
In the embodiment shown in FIGS. 8 and 9, a pair of opposing sides 2A, 2A,
In the description, the substrate wiring 6 is drawn out from the position 2C in the opposite direction, but it is drawn out from adjacent sides such as sides 2A and 2B, drawn out from three sides other than one side, or drawn out from only one side. Even if drawers are formed,
A similar effect is obtained in that high-density mounting can be obtained.

【0046】また、上記図1および図2に示す実施の形
態、図3および図4に示す実施の形態、図5および図6
に示す実施の形態、図7に示す実施の形態、および、図
8および図9に示す実施の形態において、接続パッド4
は、複数列の千鳥配設、フルマトリクスで設けても同様
の効果を奏する。
Further, the embodiment shown in FIGS. 1 and 2, the embodiment shown in FIGS. 3 and 4, FIGS.
In the embodiment shown in FIG. 7, the embodiment shown in FIG. 7, and the embodiment shown in FIG. 8 and FIG.
The same effect can be obtained even if a plurality of rows are provided in a staggered arrangement or in a full matrix.

【0047】さらに、半導体装置2が1.27mmピッ
チのBGA(Ball GlidArray)である場
合に接続パッド4を630μm前後の大きさで形成して
説明したが、これに限られない。
Further, in the case where the semiconductor device 2 is a BGA (Ball Grid Array) having a pitch of 1.27 mm, the connection pad 4 is formed to have a size of about 630 μm, but the present invention is not limited to this.

【0048】そして、必要に応じて、Ni/Au合金な
どの表面処理を施してもよい。
If necessary, a surface treatment such as a Ni / Au alloy may be applied.

【0049】また、端子ピッチを1.27mmピッチと
して説明したが、例えば1.0mmピッチ、0.8mm
ピッチ、0.65mmピッチ、0.5mmピッチ、さら
により細かいピッチなどでもできる。
Also, the terminal pitch has been described as 1.27 mm pitch.
Pitch, 0.65 mm pitch, 0.5 mm pitch, and even finer pitch can be used.

【0050】さらに、配線基板1は、ガラスエポキシ基
板に限らず、例えばエポキシ樹脂にガラス以外の繊維な
どと組み合わせた有機基板や、ポリイミド系基板、アル
ミナ系絶縁基板などの無機質基板、エポキシ樹脂に無機
フィラを混入させて硬化後の熱膨張係数を小さくしたも
のなど、基材の材質やその構造、製造方法は、いずれの
ものでもできる。なお、熱膨張係数を小さく形成したも
のであれば、熱膨張収縮による応力が作用して断線する
などをさらに抑制できる。
Further, the wiring substrate 1 is not limited to a glass epoxy substrate, but may be an organic substrate in which an epoxy resin is combined with fibers other than glass, an inorganic substrate such as a polyimide substrate or an alumina insulating substrate, or an inorganic substrate such as an epoxy resin. Any material can be used for the material of the base material, its structure, and manufacturing method, such as a material having a reduced thermal expansion coefficient after curing by mixing a filler. In addition, if it is formed with a small thermal expansion coefficient, it is possible to further suppress disconnection due to the stress due to thermal expansion and contraction.

【0051】一方、半導体装置2と配線基板1との間隙
に樹脂材料を充填して、はんだボール7や基板配線6の
接続パッド4へ接続する付け根の部分を補強してもよ
い。この場合、ばんだボールなどの部分は補強されその
部分の寿命は向上するが、樹脂材料の充填部分の端部あ
るいは実装エリア2Eからはみ出した部分の樹脂そのも
のにストレスが集中し、この樹脂材料の端部の直下部分
の基板配線6にクラックによる断線が発生する場合や、
樹脂材料そのものにクラックが発生し、そのクラックが
進展して基板配線6を断線させるおそれがあるため注意
を要する。この場合にも、クラックの発生しやすい辺の
基板配線6の引き出しを少なくする、引き出しを行わな
い、または表層での配線を行わないことにより、断線の
可能性も低くなる。
On the other hand, the gap between the semiconductor device 2 and the wiring board 1 may be filled with a resin material to reinforce the solder ball 7 and the base of the board wiring 6 connected to the connection pad 4. In this case, the portion of the ball or the like that has been reinforced is reinforced and the life of the portion is improved, but stress concentrates on the resin itself at the end of the portion filled with the resin material or the portion protruding from the mounting area 2E, and this resin material is used. In the case where a break occurs due to a crack in the substrate wiring 6 immediately below the end,
Care must be taken because cracks may occur in the resin material itself, and the cracks may develop and break the substrate wiring 6. Also in this case, the possibility of disconnection is reduced by reducing the number of pull-outs of the substrate wiring 6 on the side where cracks are likely to occur, by not pulling out the wiring, or by not performing wiring on the surface layer.

【0052】[0052]

【発明の効果】本発明によれば、半導体装置の実装エリ
アから外部に基板配線が引き出される辺の数を多くとも
3つ以下に少なくすることにより、基板配線の引き出さ
れていない辺に対応する位置には基板配線の引き回しス
ペースを確保する必要がなく、この基板配線の引き出さ
れていない辺に対応する位置に隣接部品を配置すること
が可能となり、高密度な実装ができる。
According to the present invention, the number of sides from which the board wiring is drawn out from the mounting area of the semiconductor device to the outside is reduced to at most three or less, thereby coping with the side where the board wiring is not drawn out. There is no need to secure a space for routing the board wiring at the position, and it is possible to arrange adjacent components at a position corresponding to the side from which the board wiring is not drawn out, so that high-density mounting can be performed.

【0053】また、引き出される数を少なくすることに
より、機械的ストレスにより生じる応力の発生方向と基
板配線の引き出し方向とが一致しにくくなり、断線の生
じる確率を低減でき、安定した特性が得られる。
Further, by reducing the number of wires to be drawn out, the direction in which the stress generated by the mechanical stress is generated and the direction in which the board wiring is drawn out become difficult to match, the probability of occurrence of disconnection can be reduced, and stable characteristics can be obtained. .

【0054】そして、基板配線の引き出し方向を曲げ応
力が発生しやすい長手状の絶縁基板の長手方向に対して
交差する方向に形成することにより、簡単な構成で容易
に断線を抑制でき、安定した特性が得られる。
Further, by forming the wiring direction of the substrate wiring in a direction intersecting the longitudinal direction of the longitudinal insulating substrate in which bending stress is likely to be generated, disconnection can be easily suppressed with a simple structure and stable. Characteristics are obtained.

【0055】また、実装エリアの対向する一対の辺から
反対方向に引き出し形成することにより、機械的ストレ
スにより生じる応力の発生方向と基板配線の引き出し方
向とが一致しにくくなり、簡単な構成で容易に断線の生
じる確率を低減でき、安定した特性が得られる。
Further, by forming the mounting area in the opposite direction from a pair of opposite sides of the mounting area, the direction in which the stress generated by the mechanical stress is generated and the direction in which the board wiring is drawn out hardly coincide with each other. The probability of occurrence of disconnection can be reduced, and stable characteristics can be obtained.

【0056】さらに、電子機器の長手状の本体ケース内
に、長手方向に対して交差する方向に基板配線を引き出
し形成した長手状の配線基板を本体ケースの長手方向に
沿って配設するため、簡単な構成で容易に断線を抑制で
き、電子機器の安定した特性が容易に得られる。
Further, in order to dispose a long wiring board in which the board wiring is drawn out in a direction intersecting with the longitudinal direction in the longitudinal main body case of the electronic device along the longitudinal direction of the main body case, Disconnection can be easily suppressed with a simple configuration, and stable characteristics of the electronic device can be easily obtained.

【0057】そして、絶縁基板にスルーホールやビアホ
ールを設けて、基板配線を実装面と異なる裏面や中間層
に設けることにより、より高密度の実装が得られる。
By providing through holes and via holes in the insulating substrate and providing the substrate wiring on the back surface or intermediate layer different from the mounting surface, higher-density mounting can be obtained.

【0058】また、中間層や裏面などの複数の層に基板
配線を設けることにより、基板配線の配線間隔を広く設
計でき、基板配線どうしの短絡などを防止できる一方、
より端子ピッチの狭い半導体装置や外部端子の多い半導
体装置でも適用できる。
Further, by providing the substrate wiring in a plurality of layers such as the intermediate layer and the back surface, the wiring interval between the substrate wirings can be designed to be wide, and a short circuit between the substrate wirings can be prevented.
The present invention can be applied to a semiconductor device having a narrower terminal pitch or a semiconductor device having many external terminals.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態を示す配線基板の平面図
である。
FIG. 1 is a plan view of a wiring board according to an embodiment of the present invention.

【図2】同上半導体実装装置を示す断面図である。FIG. 2 is a cross-sectional view showing the same semiconductor mounting device.

【図3】本発明の他の実施の形態を示す配線基板の平面
図である。
FIG. 3 is a plan view of a wiring board showing another embodiment of the present invention.

【図4】同上電子機器内に配設した配線基板に曲げスト
レスが加わる状況を説明する説明図である。
FIG. 4 is an explanatory diagram illustrating a situation in which bending stress is applied to a wiring board provided in the electronic device.

【図5】本発明のさらに他の実施の形態を示す配線基板
の平面図である。
FIG. 5 is a plan view of a wiring board showing still another embodiment of the present invention.

【図6】同上半導体実装装置を示す断面図である。FIG. 6 is a cross-sectional view showing the semiconductor mounting device according to the first embodiment;

【図7】本発明のさらに他の実施の形態を示す配線基板
の平面図である。
FIG. 7 is a plan view of a wiring board showing still another embodiment of the present invention.

【図8】本発明のさらに他の実施の形態を示す配線基板
の平面図である。
FIG. 8 is a plan view of a wiring board showing still another embodiment of the present invention.

【図9】同上半導体実装装置を示す断面図である。FIG. 9 is a sectional view showing the semiconductor mounting device according to the second embodiment;

【図10】従来例の配線基板を示す平面図である。FIG. 10 is a plan view showing a conventional wiring board.

【符号の説明】[Explanation of symbols]

1,22 配線基板 2,21 半導体装置 2A,2B,2C,2D 辺 2E,23 実装エリア 3 外部端子 4,33,34 接続パッド 6,29 基板配線 7 はんだボール 8 スルーホール 9 ビアホール 1, 22 Wiring board 2, 21 Semiconductor device 2A, 2B, 2C, 2D side 2E, 23 Mounting area 3 External terminal 4, 33, 34 Connection pad 6, 29 Board wiring 7 Solder ball 8 Through hole 9 Via hole

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】 外部端子を有した略矩形の半導体装置が
実装される絶縁基板と、 この絶縁基板の少なくとも前記半導体装置が実装される
面に設けられ前記半導体装置の外部端子が電気的かつ機
械的に接続される接続パッドと、 この接続パッドに接続され前記半導体装置が実装される
実装エリアの多くとも3つの辺から引き出し形成される
基板配線とを具備したことを特徴とした配線基板。
1. An insulating substrate on which a substantially rectangular semiconductor device having external terminals is mounted, and an external terminal provided on at least a surface of the insulating substrate on which the semiconductor device is mounted, wherein the external terminals of the semiconductor device are electrically and mechanically mounted. A wiring board, comprising: a connection pad connected to the connection pad; and a board wiring drawn from at most three sides of a mounting area connected to the connection pad and mounting the semiconductor device.
【請求項2】 外部端子を有した略矩形の半導体装置が
実装されこの半導体装置が実装される面から反対側の面
に亘って貫通するスルーホールを有した絶縁基板と、 この絶縁基板の前記半導体装置が実装される面から前記
スルーホールの内周面を介して前記絶縁基板の反対側の
面に亘って設けられ前記半導体装置の外部端子が電気的
かつ機械的に接続される接続パッドと、 前記絶縁基板の反対側の面に位置して前記スルーホール
の内周面を介して前記接続パッドに接続されて前記半導
体装置が実装される実装エリアから引き出し形成された
絶縁基板とを具備したことを特徴とする配線基板。
2. An insulating substrate having a substantially rectangular semiconductor device having external terminals mounted thereon and having a through hole extending from a surface on which the semiconductor device is mounted to an opposite surface, and A connection pad provided from the surface on which the semiconductor device is mounted to the surface on the opposite side of the insulating substrate via the inner peripheral surface of the through hole, and external terminals of the semiconductor device being electrically and mechanically connected; An insulating substrate that is connected to the connection pad via an inner peripheral surface of the through hole and is drawn out from a mounting area where the semiconductor device is mounted, the insulating substrate being positioned on a surface on the opposite side of the insulating substrate. A wiring board characterized by the above-mentioned.
【請求項3】 外部端子を有した略矩形の半導体装置が
実装されこの半導体装置が実装される面に開口する凹状
のビアホールを有した絶縁基板と、 この絶縁基板の前記半導体装置が実装される面から前記
ビアホールの内周面に亘って設けられ前記半導体装置の
外部端子が電気的かつ機械的に接続される接続パッド
と、 前記絶縁基板の中間層に位置して前記ビアホールの内周
面を介して前記接続パッドに接続されて前記絶縁基板の
平面方向に沿って前記半導体装置が実装される実装エリ
アから引き出し形成された基板配線とを具備したことを
特徴とする配線基板。
3. An insulating substrate having a substantially rectangular semiconductor device having external terminals mounted thereon and having a concave via hole opened on a surface on which the semiconductor device is mounted, and wherein the semiconductor device of the insulating substrate is mounted. A connection pad provided from the surface to an inner peripheral surface of the via hole, to which external terminals of the semiconductor device are electrically and mechanically connected; and an inner peripheral surface of the via hole located in an intermediate layer of the insulating substrate. And a substrate wiring connected to the connection pad via a mounting area where the semiconductor device is mounted along a plane direction of the insulating substrate.
【請求項4】 外部端子を有した略矩形の半導体装置が
実装され、この半導体装置が実装される面から反対側の
面に亘って貫通するスルーホールおよび前記半導体装置
が実装される面に開口する凹状のビアホールを有した絶
縁基板と、 この絶縁基板の前記半導体装置が実装される面から前記
スルーホールの内周面を介して前記絶縁基板の反対側の
面に亘って設けられるとともに、絶縁基板の前記半導体
装置が実装される面から前記ビアホールの内周面に亘っ
て設けられ、前記半導体装置の外部端子が電気的かつ機
械的に接続される接続パッドと、 前記絶縁基板の反対側の面および前記絶縁基板の中間層
の少なくともいずれか一方に位置して前記スルーホール
および前記ビアホールの内周面の少なくともいずれか一
方を介して前記接続パッドに接続され、前記半導体装置
が実装される実装エリアから前記絶縁基板の平面方向に
沿って引き出し形成された基板配線とを具備したことを
特徴とする配線基板。
4. A substantially rectangular semiconductor device having external terminals is mounted, a through hole penetrating from a surface on which the semiconductor device is mounted to an opposite surface, and an opening in a surface on which the semiconductor device is mounted. An insulating substrate having a concave via hole to be formed, and an insulating substrate provided from a surface of the insulating substrate on which the semiconductor device is mounted to a surface on the opposite side of the insulating substrate via an inner peripheral surface of the through hole. A connection pad provided from a surface of the substrate on which the semiconductor device is mounted to an inner peripheral surface of the via hole, and externally connected to the external terminal of the semiconductor device electrically and mechanically; Surface and at least one of the intermediate layer of the insulating substrate and the connection pad through at least one of the inner peripheral surface of the through hole and the via hole. Is continued, the wiring board, characterized by comprising the above semiconductor device substrate wiring is drawn out formed along a plane direction of the insulating substrate from the mounting area to be mounted.
【請求項5】 基板配線は、実装エリアの多くとも3つ
の辺から引き出し形成されたことを特徴とした請求項2
ないし4のいずれか一に記載の配線基板。
5. The circuit board according to claim 2, wherein the substrate wiring is drawn out from at most three sides of the mounting area.
5. The wiring board according to any one of items 4 to 4.
【請求項6】 基板配線は、実装エリアの対向する一対
の辺から引き出し形成されたことを特徴とした請求項1
ないし5のいずれか一に記載の配線基板。
6. The wiring according to claim 1, wherein the substrate wiring is drawn out from a pair of opposite sides of the mounting area.
6. The wiring board according to any one of items 5 to 5.
【請求項7】 接続パッドおよび基板配線は、それぞ複
数設けられ、 前記基板配線の全数に対する少なくとも80%の数が、
実装エリアの所定の辺から引き出し形成されたことを特
徴とする請求項1ないし6のいずれか一に記載の配線基
板。
7. A plurality of connection pads and substrate wirings are provided, respectively, and at least 80% of the total number of the substrate wirings is:
7. The wiring board according to claim 1, wherein the wiring board is drawn out from a predetermined side of the mounting area.
【請求項8】 絶縁基板は、長手状に形成され、 基板配線は、前記絶縁基板の長手方向に対して交差する
方向に引き出し形成されたことを特徴とした請求項1な
いし7のいずれか一に記載の配線基板。
8. The insulating substrate according to claim 1, wherein the insulating substrate is formed in a longitudinal shape, and the substrate wiring is drawn out in a direction crossing the longitudinal direction of the insulating substrate. The wiring board according to claim 1.
【請求項9】 請求項1ないし8のいずれか一に記載の
配線基板と、 この配線基板に実装された半導体装置とを具備したこと
を特徴とする半導体実装装置。
9. A semiconductor mounting device, comprising: the wiring board according to claim 1; and a semiconductor device mounted on the wiring board.
【請求項10】 半導体装置と配線基板との間には、樹
脂材料が充填されたことを特徴とした請求項9記載の半
導体実装装置。
10. The semiconductor mounting device according to claim 9, wherein a resin material is filled between the semiconductor device and the wiring board.
【請求項11】 本体ケースと、 この本体ケース内に配設された請求項1ないし8のいず
れか一に記載の配線基板および請求項9または10記載
の半導体実装装置の少なくともいずれか一方とを具備し
たことを特徴とする電子機器。
11. A main body case, and at least one of the wiring board according to any one of claims 1 to 8 and the semiconductor mounting device according to claim 9 or 10 provided in the main body case. An electronic device, comprising:
【請求項12】 本体ケースは、長手状に形成され、 この本体ケースに請求項8記載の配線基板が長手方向を
前記本体ケースの長手方向に沿って配設されたことを特
徴とする請求項11記載の電子機器。
12. The main body case is formed in a longitudinal shape, and the wiring board according to claim 8 is disposed on the main body case along a longitudinal direction of the main body case. 12. The electronic device according to item 11.
JP15175299A 1999-05-31 1999-05-31 Wiring board, semiconductor mounting device and electronic equipment Expired - Fee Related JP3379477B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15175299A JP3379477B2 (en) 1999-05-31 1999-05-31 Wiring board, semiconductor mounting device and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15175299A JP3379477B2 (en) 1999-05-31 1999-05-31 Wiring board, semiconductor mounting device and electronic equipment

Publications (2)

Publication Number Publication Date
JP2000340710A true JP2000340710A (en) 2000-12-08
JP3379477B2 JP3379477B2 (en) 2003-02-24

Family

ID=15525527

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246507A (en) * 2000-12-15 2002-08-30 Ibiden Co Ltd Multilayer printed wiring board
JP2004134649A (en) * 2002-10-11 2004-04-30 Seiko Epson Corp Circuit board, mounting structure of semiconductor device with bumps, electro-optical device, and electronic apparatus
CN113133181A (en) * 2019-12-31 2021-07-16 颀邦科技股份有限公司 Circuit board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246507A (en) * 2000-12-15 2002-08-30 Ibiden Co Ltd Multilayer printed wiring board
JP2004134649A (en) * 2002-10-11 2004-04-30 Seiko Epson Corp Circuit board, mounting structure of semiconductor device with bumps, electro-optical device, and electronic apparatus
CN113133181A (en) * 2019-12-31 2021-07-16 颀邦科技股份有限公司 Circuit board
CN113133181B (en) * 2019-12-31 2022-02-11 颀邦科技股份有限公司 Circuit board

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