JP2000216377A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, capable of preventing or suppressing deterioration of hot-carrier resistance of N-channel MOS transistor and increased the shift in threshold voltage of P-channel MOS transistors. SOLUTION: After a nitride silicon film 9 covering an NMOS transistor 50A and a PMOS transistor 50B on a silicon wafer 1 is formed, argon ions are implanted to the nitride silicon film 9 to relax its internal stress. This lowers the effects caused by the high internal stress in the nitride silicon film 9 to lower an internal stress in gate oxide films 4A and 4B of the transistors 50A and 50B. The nitride silicon film 9 functions as an etching stopper during the etching process of a BPSG film 11 formed on it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a field effect transistor formed on a semiconductor substrate, an interlayer insulating film covering the field effect transistor, and The present invention relates to a method of manufacturing a semiconductor device including a wiring layer formed and connected to the field-effect transistor via a through hole formed in the interlayer insulating film.

[0002]

2. Description of the Related Art In recent years, semiconductor elements have been increasingly miniaturized due to higher integration of semiconductor devices.
The distance between an element isolation region formed on the surface of a semiconductor substrate and a contact hole is becoming smaller. For this reason,
The overlap margin (margin) of the contact hole forming mask with respect to the element isolation region is further reduced, and as a result,
Metal-Oxide-Semiconductor,
The problem of “junction leakage current” of a MOS (Field Effect Transistor) type transistor (hereinafter referred to as MOS transistor) is very likely to occur.

That is, generally, an element isolation region is formed on a surface of a semiconductor substrate using a silicon oxide (SiO ₂ ) film, and a large number of active regions are defined by the element isolation region. Then, various semiconductor elements such as MOS transistors are formed in these active regions. These M
Since an OS transistor needs to be electrically connected to a wiring layer formed thereon via an interlayer insulating film made of silicon oxide, the interlayer insulating film has a large number of contacts penetrating the interlayer insulating film. Holes and contact grooves (hereinafter, abbreviated as “contact holes” including both of them) are formed by an etching method. The wiring layer is electrically connected to the MOS transistor by a conductor (contact plug) extending through the contact hole or the contact groove. Alternatively, the conductor forming the wiring layer is directly electrically connected to the MOS transistor.

When the overlap margin of the contact hole forming mask with respect to the element isolation region is reduced, the position of the contact hole pattern is not desired by the MOS transistor due to the overlay error of the mask itself and the displacement of the pattern on the mask. And the risk of overlapping with a part of the element isolation region increases. When the contact hole pattern overlaps part of the element isolation region,
In an etching step of forming a contact hole in an interlayer insulating film made of silicon oxide, a part of the silicon oxide film forming an element isolation region is removed by over-etching, and the semiconductor substrate is placed in the contact hole near the element isolation region. It becomes easy to be exposed.

Since the source / drain region of a MOS transistor is usually formed in contact with an element isolation region, in this state, a contact plug and a source / drain region to be filled in a contact hole in a later step are formed. A desired distance cannot be secured between the semiconductor substrate and a pn junction formed between the semiconductor substrate and the semiconductor substrate. As a result, a leak current flowing through the pn junction, that is, a “junction leak current” is likely to occur.

When the etching amount of the silicon oxide film in the element isolation region increases, the contact plug becomes
It may come into contact with the joint. In this case, "junction leakage current" always flows.

The "junction leakage current" not only increases the current consumption of the semiconductor device, but also causes a malfunction of a circuit formed in the semiconductor device and leads to a reduction in reliability. It is desired. Therefore, conventionally, a silicon nitride (Si ₃ N ₄ ) film is provided between a MOS transistor and a wiring layer, and an interlayer insulating film is formed on the silicon nitride film to form a contact hole in the interlayer insulating film. A method has been proposed for use as an etching stopper when forming. An example is shown in FIG.
And FIG.

First, as shown in FIG. 8A, silicon oxide is buried in a shallow groove (trench) provided in a surface region of a semiconductor substrate 101 to form an element isolation region 103. This element isolation region 103 allows the semiconductor substrate 1
A number of active areas are defined in the 01 surface area. However, here, only two adjacent active regions will be described to simplify the description.

Next, a p-type impurity is selectively ion-implanted into one of the active regions to form a p-well 102A. Similarly, an n impurity is selectively implanted into the other active region to form an n well 102B. FIG.
As shown in (a), p-well 102A and n-well 10A
2B are adjacent to each other with the element isolation region 103 interposed therebetween.

Then, the p-well 102A and the n-well 10
2B, the n-channel MOs are respectively formed by known methods.
S transistor (hereinafter referred to as NMOS transistor)
150A and a p-channel MOS transistor (hereinafter referred to as PM
An OS transistor (referred to as OS transistor) 150B is formed.

As shown in FIG. 8A, an NMOS transistor 150A has a gate oxide film 104A formed on the surface of a p-well 102A, a gate electrode 105A formed on the gate oxide film 104A, and a gate oxide film. 104
A, a pair of insulating side walls 106A disposed on the surface of the p-well 102A on both sides, and a pair of n-type source / drain regions 107A formed in the surface region of the p-well 102A.
It is composed of Similarly, the PMOS transistor 15
0B is a gate oxide film 104B formed on the surface of the n-well 102B, a gate electrode 105B formed on the gate oxide film 104B, and a pair of gate electrodes disposed on the surface of the n-well 102B on both sides of the gate oxide film 104B. It comprises an insulating side wall 106B and a pair of p-type source / drain regions 107B formed in the surface region of the n-well 102B.

Next, a silicon oxide film 108 functioning as an interlayer insulating film is deposited on the entire semiconductor substrate 101,
MOS transistor 150A and PMOS transistor 1
Cover 50B. Subsequently, a silicon nitride film 109 is deposited on the silicon oxide film 108. The state at this time is shown in FIG.
As shown in FIG.

Subsequently, as shown in FIG. 8B, a layer of B which functions as another interlayer insulating film is formed on the silicon nitride film 109.
A PSG (BoroPhosphoSilicate Glass) film 111 is formed. Then, using the photoresist film 112 as a mask, reactive ion etching (Reactive Ion Etching,
Only the BPSG film 111 is selectively etched by the RIE method, and the contact hole 1 penetrating the BPSG film 111 is formed.
13A and 113B are formed. Since the BPSG film 111 is a kind of silicon oxide film, in the etching process of the BPSG film 111, the silicon nitride film 109 is etched.
Functions as a stopper. Therefore, the silicon nitride film 1
The silicon oxide film 108 below the portion 09 is not etched.

Next, as shown in FIG. 8C, using the same photoresist film 112 as a mask, the silicon nitride film 109 is sequentially formed by RIE under different etching conditions.
And the silicon oxide film 108 are etched respectively,
Contact hole 113A penetrating all of PSG film 111, silicon nitride film 109 and silicon oxide film 108
a and 113Ba are formed. The contact holes 113Aa and 113Ba are located immediately below the contact holes 113A and 113B penetrating the BPSG film 111. The bottom of the contact hole 113Aa is an NMOS transistor 150A.
Reaches one source / drain region 107A, and the bottom of the contact hole 113Ba is
B reaches one of the source / drain regions 107B.

The contact hole 113Ba should be correctly arranged on the source / drain region 107B without the bottom of the contact hole 113Ba overlapping the element isolation region 103. However, FIG. 8C illustrates a state in which the photoresist film 112 is shifted leftward toward the paper surface due to an overlay error.

After removing the photoresist film 112, as shown in FIG. 9, a titanium film and a titanium nitride film (both not shown) are covered with BPS so as to cover the entire semiconductor substrate 101.
A barrier metal film 114 is formed by lamination on the G film 111. The barrier metal film 114 has a contact hole 113
Surfaces of p-well 102A and n-well 102B exposed from Aa and 113Ba, and contact holes 113Aa and
It contacts the side wall of 3Ba.

Subsequently, on the barrier metal film 114,
After depositing a tungsten film 115 thick enough to close the internal space between the contact holes 113Aa and 113Ba, the barrier metal film 114 and the tungsten film 115 are removed by chemical mechanical polishing (CMP) until the BPSG film 111 is exposed. Perform polishing. Thereby, the barrier metal film 114 and the tungsten film 11
5 is selectively left only inside the contact holes 113Aa and 113Ba. Thus, the barrier metal film 114 and the tungsten film 115 left inside the contact holes 113Aa and 113Ba form the contact plug 1
41. The bottoms of these contact plugs 141 correspond to the corresponding source / drain regions 107A and 107A.
7B.

Further, a titanium nitride film 116 and an aluminum alloy film 1 such as an AlCu film are formed on the BPSG film 111.
17 and a titanium nitride film 118 are sequentially stacked. Thereafter, the three films 116, 117 and 118 are patterned to form a three-layer wiring layer 119 as shown in FIG.
It is formed on the PSG film 111. The predetermined wiring of the wiring layer 119 is connected to the corresponding source / drain regions 107A and 107B via the contact plug 141, respectively.

Actually, in a subsequent step, the wiring layer 119 is formed.
A low dielectric constant film, a silicon oxide film, or the like is formed as another interlayer insulating film on the BPSG film 111 so as to cover the BPSG film 111, and further another wiring layer, a passivation film, and the like are formed to complete the semiconductor device. However, these steps are irrelevant to the present invention, and a description thereof will be omitted.

In the above-described conventional method of manufacturing a semiconductor device, as shown in FIG.
Is shifted from the correct position and a part thereof overlaps the element isolation region 103, the etching amount of the silicon oxide film forming the element isolation region 103 is almost negligibly small. This is because only the silicon oxide film 108 is etched after the BPSG film 111 and the silicon nitride film 109 are respectively etched, so that the over-etching time of the silicon oxide film forming the element isolation region 103 is greatly reduced. This is because the etching amount also decreases. In other words, the element isolation region 103
This is because the controllability of the etching of the silicon oxide film forming the silicon oxide film is improved.

Thus, the contact hole 113Ba
A contact plug 141 filled in the inside and a source
A sufficient distance is secured between the drain region 107B and the pn junction formed at the junction with the semiconductor substrate 101. Therefore, "junction leak current" is prevented.

In the above-described conventional method for manufacturing a semiconductor device, the "junction leakage current" is prevented by the silicon nitride film 109, so that the contact holes 113Aa and
The ion implantation step performed to suppress the “junction leakage current” after the formation of 3Ba is not required. For this reason,
There is also an advantage that the number of steps is reduced.

The silicon nitride film 109 used in the above-described conventional method of manufacturing a semiconductor device serves as an etching stopper in the etching process of the BPSG film 111 and also serves as an interlayer formed above the silicon nitride film 109. The moisture contained in the insulating film causes the MOS transistor 1
50A and 150B are prevented from reaching the gate insulating films 104A and 104B.
It also has the role of preventing deterioration of the characteristics of A and 150B.

That is, the element isolation region 10 by miniaturization
As the distance between the wiring 3 and the contact holes 113Aa and 113Ba decreases, the distance between the wirings in the wiring layer 119 also decreases, and the parasitic capacitance between the wirings increases accordingly. As a result, not only does the operating speed of the circuit slow down,
The power consumption also increases. Therefore, in order to suppress this, conventionally, various low dielectric constant films have been used as interlayer insulating films instead of the BPSG film 111. For example,
SiOF (Silicon OxyFluoride), HSQ (Hydrogen
SilsesQuioxane), BCB (Benzo Cyclo-Butene), organic SOG (Spin On Glass) material, fluorinated amorphous carbon, and the like.

However, since these low dielectric constant films are porous, they have a property of easily absorbing atmospheric moisture. For this reason, when the temperature becomes high due to the heat applied during the heat treatment during the manufacturing process or the heat generated during the operation of the semiconductor device, the moisture contained in these low dielectric constant films is directed toward the MOS transistors 150A and 150B thereunder. Easy to spread. When the moisture reaches the gate oxide films 104A and 104B,
A trap level is generated at the interface between the semiconductor substrate 101 and the gate oxide films 104A and 104B and in the gate oxide films 104A and 104B. As a result, for example, the hot carrier resistance is reduced and the MOS transistors 150A and 150
The characteristics of 0B are degraded.

However, if the silicon nitride film 109 exists under the interlayer insulating film made of the low dielectric constant film, the diffusion of the moisture contained in the low dielectric constant film will
9 prevents the moisture from reaching the gate insulating films 104A and 104B. Thus, the deterioration of the characteristics of the MOS transistors 150A and 150B is prevented.

[0027]

In the conventional method of manufacturing a semiconductor device shown in FIGS.
By providing 08, “junction leakage current” is prevented for the above-described reason, but on the other hand, a new problem described below occurs.

That is, in the conventional method of manufacturing a semiconductor device shown in FIGS. 8 and 9, a silicon nitride film 109 is formed on a silicon oxide film 108. This silicon nitride film 108 serves as an etching stopper. In order to ensure the function, it usually has a thickness of 20 nm or more. On the other hand,
It is known that the silicon nitride film 109 has a high tensile stress of 10 ⁹ dyne / cm ² or more. The high tensile stress of the silicon nitride film 109 affects the underlying silicon oxide film 108 and increases the internal stress of the silicon oxide film 108. Silicon oxide film 108
The increased internal stress further reduces the gate electrodes 105A, 105B and the gate oxide films 104A,
4B and increase their internal stress.

In this manner, the gate oxide films 104A, 104
When the internal stress of the gate oxide film 104A increases, the internal stress of the gate oxide film 104A increases.
Interface between gate and p-well 102A or gate oxide film 1
An interface state is likely to be formed at the interface between 04B and n-well 102B. Also, the gate oxide films 104A and 104B
The amount of fixed charges inside the semiconductor device also tends to increase.

As a result, in the NMOS transistor 150A of the p-well 102A, there arises a problem that the hot carrier resistance is easily deteriorated. Also, the n-well 102
In the B PMOS transistor 150B, there is a problem that the amount of shift of the threshold voltage tends to increase due to slow trapping. Both of these problems are caused by the NMOS transistor 150A and the PM transistor 150A.
This leads to a decrease in the reliability of the OS transistor 150B.

It is an object of the present invention to provide a method of manufacturing a semiconductor device which can increase the reliability of a built-in field effect transistor.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing or suppressing deterioration of hot carrier resistance of an n-channel field effect transistor and an increase in a shift amount of a threshold voltage of a p-channel field effect transistor. To provide.

[0033]

(1) In a method of manufacturing a semiconductor device according to the present invention, a step of forming a field effect transistor on a semiconductor substrate and a step of forming a silicon nitride film so as to cover the field effect transistor Implanting predetermined ions into the silicon nitride film to reduce internal stress in the silicon nitride film, and forming a first interlayer insulating film on the silicon nitride film into which the ions have been implanted. Selectively etching the first interlayer insulating film using the silicon nitride film as an etching stopper, thereby forming a first connection hole penetrating the first interlayer insulating film; Selectively etching the silicon nitride film to form a second connection hole penetrating the silicon nitride film and communicating with the first connection hole; Forming a wiring layer connected to the source / drain region of the field-effect transistor via the second connection hole on the first interlayer insulating film, wherein the step of ion-implanting the silicon nitride film comprises: The present invention is characterized in that the stress of the gate insulating film of the field effect transistor is reduced by relaxing the internal stress of the silicon nitride film.

(2) In the method of manufacturing a semiconductor device according to the present invention, after forming a silicon nitride film so as to cover a field effect transistor formed on a semiconductor substrate, predetermined ions are implanted into the silicon nitride film. Thus, the internal stress of the silicon nitride film, that is, the mechanical stress is reduced. For this reason, an increase in the internal stress of the gate electrode of the field effect transistor and hence of the gate insulating film due to the large internal stress of the silicon nitride film is prevented or suppressed. As a result, the formation of interface states at the interface between the gate insulating film and the semiconductor substrate is prevented or suppressed, and the increase in the amount of fixed charges inside the gate insulating film is also prevented or suppressed.

Accordingly, it is possible to prevent or suppress the deterioration of the hot carrier resistance of the NMOS transistor, and also to prevent or suppress the increase in the shift amount of the threshold voltage of the PMOS transistor due to the slow trap. That is, the reliability of the built-in field effect transistor can be improved.

(3) Incidentally, Japanese Patent Application Laid-Open No. 61-156837
Japanese Patent Application Laid-Open Publication No. 2002-122,086 discloses a method of manufacturing a semiconductor device in which, when a wiring layer has a barrier layer made of titanium nitride (TiN), the barrier layer is stressed by ion-implanting argon into the barrier layer. I have. However, in the method of manufacturing a semiconductor device described in the publication, the implantation of argon ions prevents the disconnection and displacement of the wiring layer on the barrier layer made of titanium nitride due to the stress of the barrier layer. This is done for the purpose.

Therefore, the present invention is clearly different from the present invention which aims at improving or improving the reliability of the field effect transistor by eliminating or suppressing the adverse effect of the internal stress of the silicon nitride film on the field effect transistor.

(4) In a preferred example of the semiconductor device of the present invention, the implantation conditions in the ion implantation step into the silicon nitride film are such that the concentration distribution of the ions implanted into the silicon nitride film is determined by the thickness of the silicon nitride film. It is set to be maximum at the approximate center of the direction. In this case, the effect of relaxing the internal stress of the silicon nitride film by the ion implantation is maximized.

In another preferred embodiment of the semiconductor device of the present invention, a step of forming a second interlayer insulating film is included between the step of forming the field-effect transistor and the step of forming the silicon nitride film. The silicon nitride film is formed on the second interlayer insulating film, and further selectively etching the second interlayer insulating film through the first connection hole and the second connection hole. Forming a third connection hole penetrating the second interlayer insulating film and communicating with the first connection hole and the second connection hole.

In this case, even if the ions implanted into the silicon nitride film penetrate the silicon nitride film, there is a danger that the ions may enter the semiconductor substrate because the second interlayer insulating film exists below the silicon nitride film. There is an advantage that the property can be eliminated.

In still another preferred embodiment of the semiconductor device of the present invention, the silicon nitride film is formed on the field effect transistor without including a step of forming another film, and the silicon nitride film is formed on the field effect transistor. Contact field effect transistor. In this case, the following advantages are obtained.

That is, when a second interlayer insulating film exists between the field effect transistor and the silicon nitride film,
Moisture contained in the second interlayer insulating film may affect the field effect transistor. However, in this case, since the second interlayer insulating film does not exist, the influence can be eliminated. Therefore, as compared with the case where the second interlayer insulating film exists, the shift amount of the threshold voltage of the field effect transistor is reduced, and the hot carrier resistance is improved.
In other words, there is an advantage that the reliability of the field effect transistor is further improved.

The silicon nitride film has a thickness of 20 nm or more,
It preferably has a thickness of 0 nm or less. This is because a thickness of 20 nm or more is necessary to secure the function as an etching stopper. On the other hand, if the thickness exceeds 60 nm, the internal stress of the silicon nitride film becomes excessive, and it may not be able to be alleviated by ion implantation.

The ions implanted into the silicon nitride film are preferably ions of an inert gas. This is because even if ions implanted in the silicon nitride film enter the semiconductor substrate for some reason, it is difficult for the ions to change the characteristics of the field effect transistor.

Among the ions of the inert gas, argon
Ions or helium ions are more preferred. This is because it can be easily used in the step of implanting ions into the silicon nitride film.

As the ions to be implanted into the silicon nitride film, boron ions may be used. This is because boron ions are frequently used in an ion implantation process in a general semiconductor device manufacturing process and are easy to use.

(5) The composition of the silicon nitride film used in the present invention is not limited, and any silicon nitride film can be used as long as it functions as an etching stopper in the step of etching the first interlayer insulating film. A silicon film can be used.

The conditions for the ion implantation into the silicon nitride film according to the present invention can be set arbitrarily so that the internal stress can be reduced according to the silicon nitride film to be used.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

(First Embodiment) FIGS. 1 to 3 show a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, silicon oxide is buried in a shallow groove (trench) provided in a surface region of a silicon substrate 1 to form an element isolation region 3 by a known method. I do. A large number of active regions are defined in the surface region of the silicon substrate 1 by the element isolation regions 3.
However, here, only two adjacent active regions will be described to simplify the description.

Next, ion implantation is performed using a patterned photoresist film (not shown) as a mask, and p-type impurities are selectively introduced into one of the active regions. Similarly, ion implantation is performed, and an n-type impurity is selectively introduced into the other active region. Thereafter, heat treatment for activating the implanted impurities is performed to form a p-well 2A and an n-well 2B in the two active regions, respectively. As shown in FIG. 1A, the p well 2A and the n well 2B are adjacent to each other with the element isolation region 3 interposed therebetween.

Subsequently, after a silicon oxide film (not shown) is formed on the entire surface of the silicon substrate 1 by the thermal oxidation method, a polysilicon film (not shown) is deposited on the silicon oxide film by the CVD method. I do. By simultaneously patterning the silicon oxide film and the polysilicon film, p
A silicon oxide gate oxide film 4A and a polysilicon gate electrode 5A are formed on the well 2A, and a silicon oxide gate oxide film 4B and a polysilicon gate electrode 5B are formed on the n-well 2B.

Next, after depositing a silicon oxide film (not shown) so as to cover the entire surface of the silicon substrate 1 by the CVD method, the silicon oxide film is etched back by the anisotropic RIE method to form a gate. A pair of side walls 6A and 6B made of silicon oxide are formed on the sides of the electrodes 5A and 5B, respectively.

Subsequently, the gate electrodes 5A and 5B and the side walls 6
Using A and 6B as masks, ions of an n-type impurity are implanted into the p-well 2A, and a pair of n-type source / drain regions 7A are formed in the surface region of the p-well 2A in a self-aligned manner. At this time, the same n-type impurity is also introduced into gate electrode 5A. Similarly, ions of a p-type impurity are implanted into the n-well 2B, and a pair of p-type source / drain regions 7B are formed in the surface region of the n-well 2B in a self-aligned manner. At this time, the same p-type impurity is also introduced into gate electrode 5B.

Thus, an NMOS transistor 50A including the gate oxide film 4A, the gate electrode 5A, the pair of side walls 6A, and the pair of source / drain regions 7A is formed in the p well 2A. In the n-well 2B, a PMOS transistor 50B including a gate oxide film 4B, a gate electrode 5B, a pair of side walls 6B, and a pair of source / drain regions 7B is formed.

Note that a titanium silicide film or a cobalt silicide film may be formed on the source / drain regions 7A and 7B and the gate electrodes 5A and 5B by a known method. In this case, the resistance of the source / drain regions 7A and 7B and the gate electrodes 5A and 5B can be reduced.

Next, a silicon oxide film 8 functioning as a first interlayer insulating film is deposited by normal pressure CVD so as to cover the entire surface of the silicon substrate 1. This silicon oxide film 8
Has a thickness of about 100 nm and is in contact with the NMOS transistor 50A and the PMOS transistor 50B.

Subsequently, a silicon nitride film 9 functioning as an etching stopper is deposited on the silicon oxide film 8. The thickness of this silicon nitride film 8 is 20 nm or more. If the thickness is less than 20 nm, the function as an etching stopper becomes insufficient. The preferred thickness of the silicon nitride film 8 is 20 to 60 nm. If the thickness exceeds 60 nm, the internal stress of the silicon nitride film 8 becomes excessive, and the internal stress cannot be sufficiently reduced in the next ion implantation step.

The formation of the silicon nitride film 8 is performed, for example, by using Si
Cl ₂ H ₂ and NH ₃ are used as source gases of silicon and nitrogen, respectively, and the temperature of the silicon substrate 1 is set to 650 to 8
Set to 00 ° C and gas pressure from 0.1 Torr to 100T
It can be performed by a low pressure CVD method set to orr.

Next, as shown in FIG. 1B, argon ions 10 are ion-implanted into the silicon nitride film 9 in order to reduce the large internal stress of the silicon nitride film 9.
The conditions for this ion implantation are set so that the distribution of the amount of implanted ions has a peak near the center in the thickness direction of the silicon nitride film 9. This is because in this case, the effect of relaxing the internal stress of the silicon nitride film 9 is maximized.

The conditions for implanting argon ions 10 are, for example, an acceleration energy of 10 to 30 keV and a dose of 1 × 1.
0 ^{15 to} 3 × 10 ¹⁵ cm ⁻² . Note that as an ion species to be implanted, an inert gas such as argon or helium is preferable. The reason is that the implanted ions are
This is because there is an advantage that the characteristics of the MOS transistors 50A and 50B are unlikely to change even if they penetrate through the silicon oxide film 8 and enter the inside of the silicon substrate 1.

Further, by the normal pressure CVD method, FIG.
As shown in FIG. 5, a BPSG film 11 (having a thickness of about 1.4 μm) functioning as a second interlayer insulating film is formed on the silicon nitride film 9.
To form Thereafter, the surface of the BPSG film 11 is polished and flattened by the CMP method. At this time, the gate electrode 5
The polishing conditions are set so that the height (thickness) from the tops of A and 5B to the surface of the BPSG film 11 becomes a desired value (for example, about 0.6 μm). The height is set in consideration of the aspect ratio of the contact hole to be formed so as not to cause a problem when processing the contact hole.

Subsequently, a patterned photoresist film 12 is formed on the BPSG film 11. Then RI
Using the photoresist film 12 as a mask,
By selectively etching only the PSG film 11, contact holes 13A and 13B penetrating the BPSG film 11 are formed. In this dry etching step, the etching rate of the BPSG film 11 with respect to the silicon nitride film 9 becomes sufficiently high so that the silicon nitride film 9 functions reliably as an etching stopper (that is, the selectivity is sufficiently large). Etching conditions are set as follows. For example, a mixed gas of C ₄ F ₈ , CO, Ar, and O ₂ is used as an etching gas, and the gas pressure is set to about 30 mTorr.
r, the temperature is 20 ° C., and the supply power is 700 W.

Next, as shown in FIG. 2A, using the same photoresist film 12 as a mask, the silicon nitride film 9 and the silicon oxide film 8 are sequentially dry-etched by RIE under different etching conditions. Then, contact holes 13Aa and 13Ba penetrating the BPSG film 11, the silicon nitride film 9, and the silicon oxide film 8 are formed. The etching conditions for these etching steps are set, for example, as follows.

In the etching of the silicon nitride film 9, CH
A mixed gas of F ₃ and CF ₄ is used as an etching gas, the gas pressure is about 30 mTorr, the temperature is 20 ° C.,
The supply power is 800 W. In the etching of the silicon oxide film 8, a mixed gas of C ₄ F ₈ , CO, Ar and O ₂ is used as an etching gas, and the gas pressure is set to about 30 m.
Torr, temperature 20 ° C., supply power 700 W.

The planar shape of the contact holes 13Aa and 13Ba is, for example, rectangular or circular. Contact hole 1
The bottoms of 3Aa and 13Ba reach the corresponding source / drain regions 7A and 7B, respectively.

Correctly, the contact hole 13Ba should be disposed on the source / drain region 7B without the bottom of the contact hole 13Ba overlapping the element isolation region 3. However, in FIG. 2A, the photoresist film 12
Are shifted to the left as viewed in the drawing due to the superposition error.

Next, after the photoresist film 12 is removed, as shown in FIG.
On the SG film 11, a titanium film (thickness: about 30 nm) and a titanium nitride film (thickness: about 50 nm) (both not shown) are sequentially stacked. The titanium film and the titanium nitride film form the barrier metal film 14. Barrier metal film 1
4 is p exposed from the contact holes 13Aa and 13Ba.
The surface of the well 2A and the n-well 2B and the contact hole 13
It contacts the side walls of Aa and 13Ba.

Subsequently, a tungsten film 15 (thickness: about 0.5 μm) is deposited on the barrier metal film 14 by a low pressure CVD method so as to close the internal space of the contact holes 13Aa and 13Ba. BPSG
Polishing of the barrier metal film 14 and the tungsten film 15 is performed until the film 11 is exposed. Thus, the barrier metal film 14 and the tungsten film 15 are selectively left inside the contact holes 13Aa and 13Ba. Contact hole 13
The barrier metal film 14 and the tungsten film 15 left inside Aa and 13Ba are respectively
1. The bottoms of these contact plugs 41 are in contact with the corresponding source / drain regions 7A and 7B, respectively.

Subsequently, the BPSG film 1 was formed by sputtering.
On top of this, a titanium nitride film 16, an aluminum alloy film 17 made of, for example, AlCu, and a titanium nitride film 18 are sequentially laminated. Each of the titanium nitride film 16, the aluminum alloy film 17, and the titanium nitride film 18 has a thickness of about 50.
nm, about 0.5 μm, and about 50 nm. Thereafter, the titanium nitride film 16, the aluminum alloy film 17, and the titanium nitride film 1 are formed by photolithography and RIE.
8 are simultaneously patterned to form a first wiring layer 19 having a three-layer structure on the BPSG film 11. The predetermined wiring of the first wiring layer 19 is connected to the corresponding source / drain regions 7A and 7B via the contact plug 41, respectively.

The titanium nitride film 18 functions as an anti-reflection film for exposure light in a photolithography process.

Next, as shown in FIG. 3, a high-density plasma CVD
Is formed to cover the wiring layer 19. On the liner oxide film 20, a low dielectric constant film 21 is further formed. The low dielectric constant film 21 functions as a third interlayer insulating film, and is formed of a material such as SiOF, HSQ, BCB, an organic SOG material, or fluorinated amorphous carbon.

Subsequently, a silicon oxide film 22 having a thickness of about 1.4 μm is formed on the low dielectric constant film 21 by a plasma CVD method.
Is formed, the surface of the silicon oxide film 22 is flattened by the CMP method. At this time, the polishing conditions are set so that the height (thickness) from the top of the wiring layer 19 to the surface of the low dielectric constant film 21 is about 0.6 μm. The reason is BPSG
This is the same as described above for the film 11.

Next, via holes 23 penetrating the low dielectric constant film 21 and the silicon oxide film 22 are formed by photolithography and RIE. This via hole 23
Are connected to the corresponding wiring of the first wiring layer 19 below.

Further, a titanium film (thickness: about 30 nm) and a titanium nitride film (thickness: about 50 nm) (both not shown) are sequentially formed on the silicon oxide film 22 by sputtering. These titanium films and titanium nitride films are:
A barrier metal film 24 is formed. Barrier metal film 24
Contacts the surface of the wiring corresponding to the wiring layer 19 exposed from the via hole 23 and the side wall of the via hole 23.

Subsequently, a tungsten film 25 (thickness: about 0.5 μm) thick enough to close the internal space of the via hole 23 is deposited on the barrier metal 24 by a low pressure CVD method. Then, the silicon oxide film 2 is formed by the CMP method.
The barrier metal film 24 and the tungsten film 25 are polished until the layer 2 is exposed, and is selectively left only inside the via hole 23. Thus, the via plug 42 made of the barrier metal 24 and the tungsten film 25 is provided inside the via hole 23.
To form The bottom of the via plug 42 is in contact with the corresponding wiring of the wiring layer 19.

Next, a titanium nitride film 26, an aluminum alloy film 27 such as AlCu, and a titanium nitride film 28 are sequentially formed on the silicon oxide film 22 by sputtering. Titanium nitride film 26, aluminum alloy film 27,
The thickness of the titanium nitride film 28 is about 50 nm, about 0.5 μm, and about 50 nm, respectively. Thereafter, the titanium nitride film 26 is formed by photolithography and RIE.
The aluminum alloy film 27 and the titanium nitride film 28 are patterned to form a second wiring layer 29 on the silicon oxide film 22.
To form

Note that the titanium nitride film 28 functions as an anti-reflection film for exposure light in a photolithography process.

Finally, a silicon oxynitride (Silicon Oxynitrid) having a thickness of about 0.3 μm is formed on the silicon oxide film 22.
e, SiON) film, and a second cover film 30 is formed.
The wiring layer 29 is covered.

Thus, as shown in FIG. 3, a semiconductor device having the NMOS transistor 50A and the PMOS transistor 50B built on the silicon substrate 1 is completed.

In the method of manufacturing a semiconductor device according to the first embodiment of the present invention, as is apparent from the above description, the NMOS transistor 50A formed on the silicon substrate 1
Then, after forming the silicon nitride film 8 so as to cover the PMOS transistor 50B, argon ions are implanted into the silicon nitride film 9 to reduce internal stress, that is, mechanical stress of the silicon nitride film 9. For this reason, an increase in the internal stress of the gate electrodes 5A and 5B of the NMOS transistor 50A and the PMOS transistor 50B and the gate insulating films 4A and 4B due to the large internal stress of the silicon nitride film 9 is prevented or suppressed.
As a result, the formation of the interface state at the interface between the gate insulating films 4A and 4B and the silicon substrate 1 is prevented or suppressed, and the increase in the fixed charge amount inside the gate insulating films 4A and 4B is also prevented or suppressed. Is done.

Therefore, deterioration of the hot carrier resistance of the NMOS transistor 50A can be prevented or suppressed, and the PMOS transistor 5A caused by the slow trap can be prevented.
An increase in the shift amount of the threshold voltage of 0B can also be prevented or suppressed. That is, the built-in NMOS transistor 50
A and the reliability of the PMOS transistor 50B can be improved. (Test Result) Next, a result of actually manufacturing a semiconductor device by using the above-described method for manufacturing a semiconductor device of the first embodiment of the present invention and evaluating its characteristics will be described.

In the manufactured semiconductor device, the length and width of the gate electrodes 5A and 5B of the NMOS transistor 50A and the PMOS transistor 50B are 0.18 μm and 1 μm, respectively.
0 μm, the thickness of each of the gate oxide films 4A and 4B is 4 nm,
The depth of the source / drain regions 7A and 7B was 100 nm. The planar shape of the contact holes 13Aa and 13Ba was a circle having a diameter of 0.24 μm. The amount of overlap between the contact hole 13Ba and the corresponding element isolation region 3 was 0.1 μm.

In the step of forming the contact holes 13Aa and 13Ba by dry-etching the silicon oxide film 8, the overetching rate was set to a desired etching amount, that is, 20% with respect to the total thickness of the silicon oxide film 8.

Then, while changing the thickness of the silicon nitride film 9, a voltage of 4 V was applied between the pair of source / drain regions 7A of the NMOS transistor 50A, and the change in the junction leak current was measured. As shown in FIG. Results were obtained.

As can be seen from FIG. 5, the silicon nitride film 9
The junction leakage current decreases with an increase in the thickness of the semiconductor substrate. When the film thickness is in the range of 20 nm or less, the degree of reduction in the junction leak current is remarkable, and in this range, it is reduced to about 1/100. From this result, the thickness of the silicon nitride film 9 was set to 20 nm.
With the above setting, it has been confirmed that the junction leakage current can be sufficiently suppressed as in the case of the conventional manufacturing method described above with reference to FIGS.

By forming the silicon nitride film 9,
The reason why the junction leakage current is suppressed is as follows.

When the silicon nitride film 9 is not formed, that is, when the silicon nitride film thickness is “0”, the silicon oxide film 8 as the first and second interlayer insulating films and the BPSG
The film 11 is etched at the same time. At this time, the etching amount (film thickness) is about 0.8 μm. On the other hand, when the silicon nitride film 9 is formed, the BPSG film 11 is etched using the silicon nitride film 9 as an etching stopper before the silicon oxide film 8 is etched. Therefore, in the etching process of the silicon oxide film 8, only the silicon oxide film 8 is etched, and the etching amount (film thickness) at this time is about 0.1 μm (= 100 μm).
nm).

As described above, when the silicon nitride film 9 is formed, the amount to be etched (film thickness) in the etching step of the silicon oxide film 8 is larger than that in the case where the silicon nitride film 9 is not formed (approximately).に). Therefore, in the etching process of the silicon oxide film 8, it is possible to precisely control the etching depth so that the over-etching amount of the silicon oxide film 8 becomes as small as possible. In other words, even if the over-etching rate of the silicon oxide film 8 is the same, the etching amount (film thickness) of the silicon oxide film 8 is greatly reduced, so that the controllability of the etching depth in the etching step is improved. For this reason, the element isolation region 3 exposed in the contact hole 13Ba
The etching amount of the silicon oxide film becomes small.

Therefore, the contact hole 13 is formed due to the etching of the silicon oxide film in the element isolation region 3.
There is no danger that the contact plug 41 in Ba approaches or comes into contact with a pn junction formed at the interface between the source / drain region 7B and the silicon substrate 1, and as a result, leakage occurring through the pn junction An increase in current is prevented.

Further, while changing the thickness of the silicon nitride film 9, the lifetime of hot carriers of the NMOS transistor 50A and the shift amount of the threshold voltage of the PMOS transistor 50B were measured. To measure the lifetime of a hot carrier,
The test was performed at room temperature while applying a gate voltage so that the substrate voltage of the NMOS transistor 50A became the maximum value. FIG.
Is the time required for the reversal ON current to degrade by 10%. The measurement of the shift amount of the threshold voltage is performed by using a PMOS.
A gate voltage of 2.0 V is applied to the transistor 50B,
This state was held in an atmosphere at a temperature of 175 ° C. for 1000 hours. The value in FIG. 9 is the amount by which the threshold voltage value measured after 1000 hours has elapsed has changed from the initial threshold voltage value.

As a result, the graph of FIG. 4 was obtained. FIG.
8 also shows, for comparison, results of a semiconductor device manufactured by using the conventional method for manufacturing a semiconductor device described with reference to FIGS.

In FIG. 4, curves A1 and B1 show the hot carrier lifetime of the NMOS transistor 50A and the threshold voltage shift amount of the PMOS transistor 50B when the method of manufacturing the semiconductor device according to the first embodiment of the present invention is used. Are respectively shown. Curves A2 and B2 show the hot carrier lifetime of the NMOS transistor 50A and the shift amount of the threshold voltage of the PMOS transistor 50B, respectively, when the conventional semiconductor device manufacturing method is used.

As can be seen from the curves A1 and A2 in FIG.
By providing the silicon nitride film 9 into which argon ions have been implanted, the lifetime of the hot carriers of the NMOS transistor 50A (curve A1) is longer than that of the conventional method (curve A2). This means that the hot stress resistance of the NMOS transistor 50A is improved by relaxing the internal stress of the silicon nitride film 9.

The lifetime of the hot carrier of the NMOS transistor 50A is determined when the thickness of the silicon nitride film is 1 nm to 10 nm.
It is the longest in the range of nm, that is, the hot carrier resistance is the best. When the thickness of the silicon nitride film exceeds 10 nm, the lifetime of the hot carrier gradually decreases with an increase in the thickness of the silicon nitride film, that is, the hot carrier resistance gradually deteriorates. This is because the stress exerted on the gate oxide film 4A by the silicon nitride film 9 increases as the thickness of the silicon nitride film 9 increases, so that an interface state is easily formed at the interface between the gate oxide film 4A and the p-well 2A. And a gate oxide film 4A on the p-well 2A.
This is because the fixed electric charge inside the element increases.

As can be seen from the curves B1 and B2 in FIG.
By providing the silicon nitride film 9 into which the argon ions are implanted, the shift amount of the threshold voltage of the PMOS transistor 50B (curve B1) is reduced as compared with the case of the conventional method (curve B2). This means that the shift amount of the threshold voltage of the PMOS transistor 50B is suppressed by relaxing the internal stress of the silicon nitride film 9.

Further, it can be seen that the shift amount of the threshold voltage of the PMOS transistor 50B gradually increases as the thickness of the silicon nitride film 9 increases. This is because the stress applied to the gate oxide film 4B increases as the thickness of the silicon nitride film 9 increases, and as a result, the gate oxide film 4B and n
This is because an interface state is easily formed at the interface of the well 2B and the fixed charge inside the gate oxide film 4B on the n-well 2B increases.

As is clear from the test results shown in FIGS. 4 and 5, according to the method of manufacturing the semiconductor device of the first embodiment of the present invention, the stress applied to the gate oxide films 4A and 4B is reduced, so that the NMOS It has been confirmed that deterioration of the hot carrier resistance of the transistor 50A and an increase in the shift amount of the threshold voltage of the PMOS transistor 50B are suppressed, and a highly reliable semiconductor device can be obtained.

(Second Embodiment) FIGS. 6 and 7 show a method of manufacturing a semiconductor device according to a second embodiment of the present invention. This method is different from the method for manufacturing a semiconductor device of the first embodiment in that the silicon oxide film 8 functioning as a first interlayer insulating film is omitted. Therefore, in FIGS. 6 and 7, the same components as those in the method of the first embodiment are denoted by the same reference numerals, and the description of the same configurations and processes will be omitted.

First, the structure shown in FIG. 6A is obtained in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment.

Next, as in the case of the first embodiment,
A thick silicon nitride film 9 used as an etching stopper is deposited over the entire silicon substrate 1, and the NMOS transistor 50A and the PMO
Covers the S transistor 50B. Since the silicon oxide film 8 according to the first embodiment does not exist, as shown in FIG.
And the PMOS transistor 50B.

Thereafter, as shown in FIG. 6B, argon ions 10 are ion-implanted into the silicon nitride film 9 to relax the internal stress of the silicon nitride film 9 as in the first embodiment. . After this ion implantation step,
This is the same as the case of the first embodiment (see FIGS. 2B to 3).

Thus, the semiconductor device having the structure shown in FIG. 7B is completed. The structure of this semiconductor device corresponds to the semiconductor device of the first embodiment in which the silicon oxide film 8 has been removed.

It is apparent that the same effect as that of the first embodiment can be obtained in the method of manufacturing the semiconductor device of the second embodiment. However, in the method of manufacturing the semiconductor device according to the second embodiment, the NMOS transistor 50A
And PMOS transistor 50B and silicon nitride film 9
Since no silicon oxide film is formed between the transistors 50A and 50A,
0B does not adversely affect the gate oxide films 4A and 4B. Therefore, there is an advantage that the effect of preventing or suppressing the deterioration of the hot carrier resistance of the NMOS transistor 50A and the effect of preventing or suppressing the increase in the threshold voltage shift amount of the PMOS transistor 50B in the first embodiment are further improved. That is, the reliability of the built-in NMOS transistor 50A and PMOS transistor 50B can be further enhanced as compared with the case of the first embodiment.

In the first and second embodiments described above, the silicon nitride film is used as an etching stopper when forming a contact hole in the interlayer insulating film. However, the present invention is not limited to this. However, the present invention can be applied to a case where a silicon nitride film is used as an etching stopper when a wiring groove is formed in an interlayer insulating film.

[0107]

As described above, according to the method of manufacturing a semiconductor device of the present invention, deterioration of hot carrier resistance of an n-channel field effect transistor and an increase in a shift amount of a threshold voltage of a p-channel field effect transistor are increased. Can be prevented or suppressed. Therefore, the reliability of the built-in field effect transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a main part showing each step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a main part schematic cross-sectional view showing each step of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, which is a continuation of FIG. 1;

FIG. 3 is a main part schematic cross-sectional view showing each step of the method for manufacturing the semiconductor device of the first embodiment of the present invention, which is a continuation of FIG. 2;

FIG. 4 shows the hot carrier lifetime, the threshold voltage shift amount, and the thickness of the silicon nitride film of the semiconductor device manufactured by the semiconductor device manufacturing method according to the first embodiment of the present invention and the conventional semiconductor device manufacturing method. It is a graph which shows the relationship with thickness.

FIG. 5 is a graph showing a relationship between a junction leak current and a thickness of a silicon nitride film of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a main part showing each step of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

7 is a fragmentary schematic cross-sectional view showing each step of a method for manufacturing a semiconductor device of the second embodiment of the present invention, and is a continuation of FIG. 6;

FIG. 8 is a schematic cross-sectional view of a main part showing each step of a conventional method for manufacturing a semiconductor device.

9 is a main part schematic cross-sectional view showing each step of a conventional semiconductor device manufacturing method, and is a continuation of FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2A p well 2B n well 3 Element isolation region 4A, 4B Gate oxide film 5A, 5B Gate electrode 6A, 6B Side wall 7A, 7B Source / drain region 8 Silicon oxide film 9 Silicon nitride film 10 Argon ion 11 BPSG film REFERENCE SIGNS LIST 12 photoresist film 13A, 13B contact hole 13Aa, 13Ba contact hole 14 barrier metal film 15 tungsten film 16, 18 titanium nitride film 17 aluminum alloy film 19 first wiring layer 20 liner oxide film 21 low dielectric constant film 22 silicon oxide film 23 Via hole 24 Barrier metal film 25 Tungsten film 26, 28 Titanium nitride film 27 Aluminum alloy film 29 Second wiring layer 30 Cover film (SiON film) 41 Contact plug 42 Via plug 50A NMOS transistor 0B PMOS transistor

Claims (7)

[Claims] A step of forming a field effect transistor on a semiconductor substrate; a step of forming a silicon nitride film so as to cover the field effect transistor; and implanting predetermined ions into the silicon nitride film to form the silicon nitride film. Relieving the internal stress of the film; and forming a first layer on the silicon nitride film into which the ions have been implanted.
Forming an interlayer insulating film; and selectively etching the first interlayer insulating film using the silicon nitride film as an etching stopper.
Forming a first connection hole penetrating the interlayer insulating film; and selectively etching the silicon nitride film through the first connection hole, thereby penetrating the silicon nitride film and forming the first connection hole with the first connection hole. Forming a communicating second connection hole; and forming a wiring layer connected to the source / drain region of the field effect transistor through the first connection hole and the second connection hole on the first interlayer insulating film. Forming the silicon nitride film by reducing the internal stress of the silicon nitride film in the ion implantation step of the silicon nitride film, thereby reducing the stress of the gate insulating film of the field effect transistor. Manufacturing method of a semiconductor device. 2. The implantation conditions in the step of implanting ions into the silicon nitride film are set such that the concentration distribution of ions implanted into the silicon nitride film is maximized substantially at the center in the thickness direction of the silicon nitride film. The method of manufacturing a semiconductor device according to claim 1, wherein: 3. A second step between the step of forming the field-effect transistor and the step of forming the silicon nitride film.
A step of forming an interlayer insulating film, wherein the silicon nitride film is formed on the second interlayer insulating film, and further includes a second insulating film formed through the first connection hole and the second connection hole. A step of selectively etching the interlayer insulating film to form a third connection hole penetrating the second interlayer insulating film and communicating with the first connection hole and the second connection hole. 3. The method for manufacturing a semiconductor device according to 1 or 2. 4. The method according to claim 1, wherein the silicon nitride film is formed on the field effect transistor without including a step of forming another film, and the silicon nitride film is in contact with the field effect transistor. 3. The method for manufacturing a semiconductor device according to 1 or 2. 5. The method according to claim 1, wherein the silicon nitride film has a thickness of 20 nm or more.
The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has a thickness of 0 nm or less. 6. The method according to claim 1, wherein the ions implanted into the silicon nitride film are ions of an inert gas. 7. The method according to claim 1, wherein the ions implanted into the silicon nitride film are at least one selected from the group consisting of argon ions, helium ions, and boron ions. A method for manufacturing a semiconductor device.