JP2000215108A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can provide a security function for a memory chip in the semiconductor integrated circuit having an MCP formed by mounting a memory chip and a CPU chip on one package. SOLUTION: In a semiconductor circuit(MCP) having the flash memory chip 6 and CPU chip 4 mounted on one package, a signature code read out of the flash memory chip 6 and a security resetting data inputted from an outside are compared by a comparison register 4f. Only when they match each other, a tri-state buffer 4g enables the flash memory chip 6 to be read.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the security of a semiconductor integrated circuit, and more particularly, to a nonvolatile memory chip and a memory device.
The present invention relates to security of a semiconductor integrated circuit (MCP) in which a PU (microprocessor) chip or the like is mounted in the same package.

[0002]

2. Description of the Related Art In recent years, with the progress of substrate and mounting technology,
MCP (Multi Chip Package) and MCM (Multi Chip M
A technique for mounting a plurality of chips in one package (single package) called an odule has been developed.

One of the advantages of the MCP is that it is easy to develop. An existing chip can be packaged with various chips with a slight modification, thereby facilitating product development. It is also effective in terms of process. Considering the case of an MCP in which a nonvolatile memory chip and an MPU chip (or a CPU (Central Processing Unit) chip and an MCU (Memory Control Unit) chip) are packaged in one, a memory-logic Various advantages can be considered, such as the necessity of mixed loading technology.

[0004]

Here, an MCP in which a nonvolatile memory (hereinafter referred to as NV memory) chip and a CPU chip are packaged in one package will be described as an example.

For example, an NV memory chip is a general-purpose product developed by another company, and a CPU chip is an existing company-developed product. in this case,
When the I / F of the NV memory chip is added to the CPU chip to form the MCP, when a user who can understand the specification of the NV memory chip uses the security function, the security function for the NV memory chip does not work. .

In view of the above, the present invention has been made in view of the above-mentioned problems, and in a semiconductor integrated circuit in which a memory chip and a CPU chip are mounted in one package to form an MCP, the memory chip is slightly changed by changing the CPU chip. It is an object of the present invention to provide a semiconductor integrated circuit capable of providing a chip with a security function.

[0007]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit (MCP) in which a nonvolatile memory chip and a logic IC chip are mounted in one package. Comparing means for comparing reference data pre-stored in the nonvolatile memory chip with collation data input from the outside; and reading data stored in the nonvolatile memory chip in accordance with a comparison result by the comparing means And permission means for permitting or prohibiting the operation.

Further, a semiconductor integrated circuit according to the present invention comprises:
In a semiconductor integrated circuit (MCP) in which a nonvolatile memory chip and a logic IC chip are mounted in one package, comparison means for comparing reference data previously stored in the nonvolatile memory chip with collation data input from the outside Means for permitting reading of data stored in the non-volatile memory chip when the comparison result by the comparing means matches, and prohibiting reading of the data when the result does not match.

Further, a semiconductor integrated circuit according to the present invention comprises:
A nonvolatile memory chip mounted on the package and storing the first data; a comparing means for comparing the first data with the second data input from the outside; And a permission unit for permitting or prohibiting the reading of data stored in the nonvolatile memory chip, the comparing unit and the permission unit, and are mounted on the same package as the package on which the nonvolatile memory chip is mounted. And a logic IC chip.

Further, a semiconductor integrated circuit according to the present invention comprises:
In a semiconductor integrated circuit (MCP) in which a non-volatile memory chip and a logic IC chip are mounted in one package, a comparing means for comparing a signature code stored in the non-volatile memory chip in advance with collation data inputted from the outside; Means for permitting reading of data stored in the nonvolatile memory chip when the comparison result by the comparing means matches, and prohibiting reading of data stored in the nonvolatile memory chip when the comparison result does not match. It is characterized by having.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. In the following embodiment, a CPU chip having a CPU formed thereon and a flash memory chip having a flash memory formed therein are mounted in a single package, and an MCP (Multi Chip P
ackage) will be described as an example.

FIG. 1 is a schematic diagram showing the appearance of an MCP according to an embodiment of the present invention. This figure shows a state before covering the package.

As shown in FIG. 1, a CPU 2
And a flash memory chip 6 on which a flash memory is formed.

Pads 8 are arranged on the CPU chip 4, and pads 10 are arranged on the flash memory chip 6. Pads 1 for external connection are provided on the periphery of the substrate 2.
2, a pad 1 used between the CPU chip 4 and the flash memory chip 6 to connect them.
4 are arranged. Then, between the pad 8 on the CPU chip 4 and the pad 12 for external connection, between the pad 10 on the flash memory chip 6 and the pad 12 for external connection, and between the CPU chip 4 and the flash memory chip 6
Bonding wires 16 are formed between the pads 14 to electrically connect them.

Next, the configuration of the MCP according to the embodiment of the present invention will be described.

FIG. 2 is a diagram showing a block diagram of the MCP according to the embodiment of the present invention. Here,
The flash memory chip is a general-purpose product without security functions.

The MCP is provided with a CPU chip 4, a flash memory chip 6, and first to fourth external terminals. In the CPU chip 4, a CPU 4a, multiplexers (hereinafter, MUX) 4b to 4d, an address decoder 4
e, compare register 4f, tristate buffer 4
g is provided. From the first external terminal, “CE, W
E, OE "is input, and" DAT
"A" is input, "ADDRESS" is input from the third external terminal, and "MODE" is input from the fourth external terminal.

First, in the MCP, it is necessary to be able to control writing, erasing, reading, and the like from the outside (a writer or the like) with respect to the flash memory formed in the flash memory chip 6. Therefore, the input signals “CE, WE, OE, ADDRESS, DATA” are supplied to the flash memory.
Can be input from outside, and “CE,
A path for controlling the input of WE, OE, ADDRESS, DATA ”is provided.

"MODE" = "1" is MUX4 from outside
When input to the select (S) terminals of b to 4d, the MU
"CE, WE, O" input to A terminal of X4b-4d
E, ADDRESS, DATA ”are supplied to the flash memory from the output (Z) terminals of the MUXs 4b to 4d.

"MODE" = "0" indicates that the MUX 4b
In the case of input to the select (S) terminals of .about.4d (CPU mode), "CE" input from the CPU 4a to the B terminal of the MUX 4b via the address decoder 4e is supplied from the output (Z) terminal to the flash memory. . Similarly, “WE (WR), OE (RD)” input to the B terminal of the MUX 4 b from the CPU 4 a is supplied to the flash memory from the output (Z) terminal, and the CPU 4 a outputs the MUX 4 b.
"DATA, ADDRESS" input to B terminal of c, 4d
Is supplied to the flash memory from the output (Z) terminal.

Next, the security function of the MCP will be described.

First data is input from a flash memory to a compare register 4f provided in the CPU chip 4, and second data is input from the outside. The compare register 4f compares the first data with the second data and outputs an output signal corresponding to the comparison result to the tristate buffer 4g. The tristate buffer 4g switches whether to activate the security function depending on whether the output signal of the compare register 4f is "1" or "0". The details of this security function are as follows.

First, a signature code previously stored in the flash memory is output from the first terminal of the flash memory and input to the compare register 4f. Further, an input code is input from the outside to the compare register 4f via the MUX 4c.

The input signature code and the input code are compared by the compare register 4f, and if they match, "1" is output from the compare register 4f. When "1" output from the compare register 4f is input to the tri-state buffer 4g, data output to the outside is permitted, and data stored in the flash memory is output to the outside via the tri-state buffer 4g. Is done.

On the other hand, if the signature code does not match the input code, "0" is output from the compare register 4f. When this "0" is input to the tristate buffer 4g, output of data to the outside is prohibited, and output of data stored in the flash memory is cut off by the tristate buffer 4f.

That is, the signature code stored in the flash memory and the input code input from the outside are compared by the compare register. When the signature code matches the input code, the data output to the outside is made valid, and the signature code is output. If the input code does not match, the external data output is prohibited. As described above, a security function is realized in which data output to the outside is permitted for a valid user and prohibited for an unauthorized user.

As described above, according to this embodiment, by making a slight modification to the CPU chip,
That is, a compare register for comparing reference data stored in advance in the nonvolatile memory chip with collation data (security release data) input from the outside,
By providing a tri-state buffer for switching data output to an enabled state or an inhibited state according to the comparison result of the compare register, a security function is provided for the MCP in which the nonvolatile memory chip and the CPU chip are packaged in one package. This can prevent illegal reading of data from the nonvolatile memory chip.

[0028]

As described above, according to the present invention, in a semiconductor integrated circuit in which a memory chip and a CPU chip are mounted in one package to form an MCP, a slight change in the CPU chip allows Thus, it is possible to provide a semiconductor integrated circuit which can provide a security function.

[Brief description of the drawings]

FIG. 1 shows a semiconductor integrated circuit (MC) according to an embodiment of the present invention.
It is the schematic which shows the external appearance of P).

FIG. 2 shows a semiconductor integrated circuit (MC) according to an embodiment of the present invention;
It is a figure which shows the block diagram of P) MCP.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 2 ... Substrate 4 ... CPU chip 6 ... Flash memory chip 8, 10, 12, 14 ... Pad 16 ... Bonding wire 4a ... CPU 4b-4d ... Multiplexer (hereinafter MUX) 4e ... Address decoder 4f ... Compare register 4g ... Tristate buffer

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L

Claims (3)

[Claims] 1. A semiconductor integrated circuit (M) having a nonvolatile memory chip and a logic IC chip mounted in one package.
CP) comparing means for comparing reference data previously stored in the non-volatile memory chip with collation data input from the outside; and storing in the non-volatile memory chip according to a comparison result by the comparing means. And a permission unit for permitting or prohibiting the reading of the read data. 2. A non-volatile memory chip mounted on a package and storing first data, comparison means for comparing second data inputted from outside with the first data, and A permission unit for permitting or prohibiting reading of data stored in the nonvolatile memory chip according to the comparison result; and a comparison unit and the permission unit, the same as a package on which the nonvolatile memory chip is mounted. And a logic IC chip mounted on the package. 3. The logic IC chip according to claim 1, wherein the logic IC chip is an MPU (microprocessor), a CPU or an MCU (memory control unit).
Or the semiconductor integrated circuit according to any one of 2.