JP2000294722A - Laminated chip semiconductor device - Google Patents
Laminated chip semiconductor deviceInfo
- Publication number
- JP2000294722A JP2000294722A JP11095091A JP9509199A JP2000294722A JP 2000294722 A JP2000294722 A JP 2000294722A JP 11095091 A JP11095091 A JP 11095091A JP 9509199 A JP9509199 A JP 9509199A JP 2000294722 A JP2000294722 A JP 2000294722A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- interposer
- semiconductor device
- chips
- metal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、積層化チップ半導
体装置に関し、特には、複数・チップが積層されるチッ
プスタック型パッケージの積層化チップ半導体装置に関
する。The present invention relates to a stacked chip semiconductor device, and more particularly, to a stacked chip semiconductor device of a chip stack type package in which a plurality of chips are stacked.
【０００２】[0002]
【従来の技術】実装面積の拡大を回避するために、チッ
プを積層化した積層構造のパッケージが用いられ、プリ
ント基板を含むインターポーザーの上にフェースアップ
で搭載され、第２チップが第１チップの表面に対して同
様にフェースアップで積み重ねられて搭載されるチップ
スタック型パッケージと称されるパッケージングが知ら
れている。そのような公知のパッケージは、図４に示さ
れるように、インターポーザーであるテープ基材０１の
上面にインターポーザーである金属配線層０２が接合さ
れ、金属配線層０２の上面側に第１マウント材０３を介
して第１チップ０４が搭載され、第２チップ０５が第２
マウント材０６を介して第１チップ０４の上面側に搭載
されている。２つのチップ０４，０５を重ね合わせた
際、第１チップ０４の電極パッド０７が第２チップ０５
によって隠蔽されて電極パッド０７に金属ワイヤ０８を
ボンディングすることが不可能になることがないよう
に、第２チップ０５は第１のチップ０４よりもサイズ的
に小さくなければならない。2. Description of the Related Art In order to avoid an increase in the mounting area, a package having a stacked structure in which chips are stacked is used. The package is mounted face-up on an interposer including a printed circuit board. There is also known a packaging called a chip stack type package which is similarly stacked face-up on a surface of the device and mounted. In such a known package, as shown in FIG. 4, a metal wiring layer 02 as an interposer is bonded to an upper surface of a tape base material 01 as an interposer, and a first mount is provided on an upper surface side of the metal wiring layer 02. The first chip 04 is mounted via the material 03, and the second chip 05
It is mounted on the upper surface side of the first chip 04 via the mounting material 06. When the two chips 04 and 05 are overlaid, the electrode pads 07 of the first chip 04
The second chip 05 must be smaller in size than the first chip 04 so as not to be obscured by the metal pads 08 and bonded to the electrode pads 07.
【０００３】電極パッドと金属配線層との間の電気的接
続が両方のチップについて金属ワイヤが用いられている
このような公知のパッケージには、その構造の点で制約
が多い。特に、第１チップ０４の電極パッド０７が第２
チップ０５によって隠れることがないようにするために
は、第２チップ０５を第１チップ０４よりも小さくしな
ければならない、と言った制約がある。[0003] Such known packages, in which the electrical connection between the electrode pads and the metal wiring layers uses metal wires for both chips, are limited in their structure. In particular, the electrode pads 07 of the first chip 04
There is a restriction that the second chip 05 must be smaller than the first chip 04 in order not to be hidden by the chip 05.
【０００４】積層搭載の構造上の制約が緩和されること
が望まれる。更には、複数・チップの組合せの制約が少
なく、且つ、実装密度が向上することが好ましい。[0004] It is desired that restrictions on the structure of the stacked mounting be relaxed. Furthermore, it is preferable that there are few restrictions on the combination of a plurality of chips and that the mounting density be improved.
【０００５】[0005]
【発明が解決しようとする課題】本発明の課題は、積層
搭載の構造上の制約を緩和することができる積層化チッ
プ半導体装置を提供することにある。本発明の他の課題
は、積層搭載の構造上の制約を緩和することができ、複
数・チップの組合せの制約が少なく、且つ、実装密度が
向上する積層化チップ半導体装置を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a laminated chip semiconductor device capable of alleviating the structural restriction of lamination. Another object of the present invention is to provide a laminated chip semiconductor device which can reduce the restrictions on the structure of lamination mounting, reduce the restrictions on the combination of a plurality of chips, and improve the mounting density. .
【０００６】[0006]
【課題を解決するための手段】本発明による積層化チッ
プ半導体装置は、第１チップ（１）と、第２チップ
（２）とからなり、第１チップ（１）の裏面側と第２チ
ップ（２）の裏面側とが対向し、第１チップ（１）と第
２チップ（２）の表面側に電極が形成されている。この
ような裏面対向配置による多層化チップは、配線構造に
関して配置の幾何学的制約から開放される。The laminated chip semiconductor device according to the present invention comprises a first chip (1) and a second chip (2), the back side of the first chip (1) and the second chip. The back side of (2) faces, and electrodes are formed on the front side of the first chip (1) and the second chip (2). The multilayer chip having such a back-facing arrangement is released from the geometrical restriction of the arrangement with respect to the wiring structure.
【０００７】第１チップ（１）の裏面側と第２チップ
（２）の裏面側との間に接合材（３）が介設されてい
る。この接合材は、絶縁性であることが好ましい。両チ
ップ（１，２）のいずれか一方のチップ（１）の表面が
インターポーザー（４）に接合されている。インターポ
ーザー（４）はプリント配線基板に接合する面を有して
いる。A bonding material (3) is provided between the back surface of the first chip (1) and the back surface of the second chip (2). This bonding material is preferably insulative. The surface of either one of the chips (1, 2) is joined to the interposer (4). The interposer (4) has a surface to be joined to the printed wiring board.
【０００８】インターポーザー（４）に接続電極（２
１）が形成され、第１チップ（１）はインターポーザー
（４）と第２チップ（２）の間に配設され、第２チップ
（２）の表面側に電極パッド（１２）が配置され、接続
電極（２１）と電極パッド（１２）の間は、ボンディン
グワイヤ（１３）により接続されていることが好まし
い。The connection electrode (2) is connected to the interposer (4).
1) is formed, the first chip (1) is disposed between the interposer (4) and the second chip (2), and the electrode pads (12) are disposed on the front side of the second chip (2). Preferably, the connection electrode (21) and the electrode pad (12) are connected by a bonding wire (13).
【０００９】インターポーザー（４）はそれの表裏面側
に２層の金属配線（２１，７）を有し、２層の金属配線
（２１，７）はスルーホールを介して接続され、第１チ
ップ（１）の表面側に接続電極（１１）が配置され、接
続電極（１１）は金属配線（２１）に接続していること
が好ましい。更に、半田バンプ（８）からなり、半田バ
ンプ（８）は金属配線（２１）に接続している。The interposer (4) has two layers of metal wirings (21, 7) on the front and back sides thereof, and the two layers of metal wirings (21, 7) are connected through through holes to form a first layer. It is preferable that a connection electrode (11) is arranged on the surface side of the chip (1), and the connection electrode (11) is connected to the metal wiring (21). Furthermore, it consists of a solder bump (8), and the solder bump (8) is connected to the metal wiring (21).
【００１０】[0010]
【発明の実施の形態】図に一致対応して、本発明による
実施の形態は、第１チップとともに第２チップが設けら
れている。図１に示されるように、その第１チップ１と
その第２チップ２は、マウント層３を介して接合されて
いる。第１チップ１は、マウント層３に対してフェース
ダウンで（裏面側で）接合され、第１チップ１はその裏
面側がマウント層３に密着している。第２チップ２は、
マウント層３に対してフェースダウンで接合され、第２
チップ２はその裏面側がマウント層３に密着している。
ここで、裏面は電極又は回路が形成されていな面として
定義され、表面は電極又は回路が形成されている面とし
て定義される。表面は、回路形成面、電極形成面として
表現することができる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Corresponding to the drawings, an embodiment according to the present invention includes a first chip and a second chip. As shown in FIG. 1, the first chip 1 and the second chip 2 are joined via a mount layer 3. The first chip 1 is bonded to the mount layer 3 face down (at the back side), and the back side of the first chip 1 is in close contact with the mount layer 3. The second chip 2
It is bonded face down to the mount layer 3 and the second
The back surface of the chip 2 is in close contact with the mount layer 3.
Here, the back surface is defined as a surface on which electrodes or circuits are not formed, and the front surface is defined as a surface on which electrodes or circuits are formed. The surface can be expressed as a circuit formation surface or an electrode formation surface.
【００１１】インターポーザー４は、第１チップ１の表
面側（下面側）に接合されている。インターポーザー４
は、接着層５、ベースフィルム６、金属配線層７、イン
ナー半田バンプ８、ソルダーレジスト９とから形成され
ている。ベースフィルム６は、接着層５を介して第１チ
ップに熱圧着により接合されている。接着層５には、熱
可塑性と熱硬化性がある材料が用いられている。第１電
極パッド１１は、第１チップ１に属し第１チップ１の表
面側に位置づけられている。インナー半田バンプ８は、
接着層５とベースフィルム６を貫通している。電極パッ
ド１１と金属配線層７とは、インナー半田バンプ８によ
り電気的に接続されている。The interposer 4 is joined to the front side (lower side) of the first chip 1. Interposer 4
Is formed from an adhesive layer 5, a base film 6, a metal wiring layer 7, an inner solder bump 8, and a solder resist 9. The base film 6 is bonded to the first chip via the adhesive layer 5 by thermocompression. A material having thermoplasticity and thermosetting properties is used for the adhesive layer 5. The first electrode pad 11 belongs to the first chip 1 and is located on the front surface side of the first chip 1. The inner solder bumps 8
It penetrates through the adhesive layer 5 and the base film 6. The electrode pads 11 and the metal wiring layers 7 are electrically connected by the inner solder bumps 8.
【００１２】第２チップ２は、フェースアップとなるよ
うに、第１チップ１の裏面（上面）にペースト状或いは
フィルム状のマウント材３により接合されている。第１
チップ１と第２チップ２とのサブストレートの電位が異
なる場合は、マウント層３は、その材料が絶縁性である
ことが必要である。第２チップ２の第２電極パッド１２
は、ワイアボンディングにより金等の金属ワイヤ１３に
よりインナー半田バンプ８に電気的に接続される。The second chip 2 is joined to the back surface (upper surface) of the first chip 1 by a paste-like or film-like mounting material 3 so as to face up. First
When the potentials of the substrates of the chip 1 and the second chip 2 are different, the material of the mount layer 3 needs to be insulative. Second electrode pad 12 of second chip 2
Are electrically connected to the inner solder bumps 8 by metal wires 13 such as gold by wire bonding.
【００１３】金属ワイヤ１３は、インターポーザー４の
金属配線層７とインナー半田バンプ８を介して接続され
ている。第２チップ２、金属ワイヤ１３、インターポー
ザー４の露出面は、封止樹脂１４により封止される。第
１チップ１の両側面１５と第２チップ２の両側面１６と
は、それぞれに同一面特に同一平面を形成し、第１チッ
プ１と第２チップ２は平面上で同一サイズを有している
ことが好ましい。ソルダーレジスト９により覆われてい
ない複数・部位で、金属配線層７には複数・半田ボール
１７が接合している。第１チップ１と第２チップ２とイ
ンターポーザー４とからなる積層パッケージは、図示外
のプリント配線基板に半田ボール１７を介して実装され
る。第１チップ１と第２チップ２は、裏面どうしの接合
であり、同一サイズ化が可能である。The metal wire 13 is connected to the metal wiring layer 7 of the interposer 4 via the inner solder bump 8. The exposed surfaces of the second chip 2, the metal wires 13, and the interposer 4 are sealed with a sealing resin 14. Both side surfaces 15 of the first chip 1 and both side surfaces 16 of the second chip 2 form the same plane, particularly the same plane, respectively. The first chip 1 and the second chip 2 have the same size on the plane. Is preferred. A plurality of solder balls 17 are joined to the metal wiring layer 7 at a plurality of sites not covered by the solder resist 9. A stacked package including the first chip 1, the second chip 2, and the interposer 4 is mounted on a printed wiring board (not shown) via solder balls 17. The first chip 1 and the second chip 2 are joints of the back surfaces, and can be made the same size.
【００１４】図２は、本発明による実施の他の形態を示
し、チップスタック型パッケージが示されている。電極
パッド１２と金属配線層７との接続のためには、インナ
ーバンプは用いられていない。インターポーザー４の適
当な部位に開口部１８が開けられ、金属ワイヤ１３の一
端はインナーバンプを介さないで、金属配線層７に直接
に電気的に接合している。FIG. 2 shows another embodiment according to the present invention, and shows a chip stack type package. No inner bump is used for connection between the electrode pad 12 and the metal wiring layer 7. An opening 18 is opened at an appropriate portion of the interposer 4, and one end of the metal wire 13 is directly electrically connected to the metal wiring layer 7 without passing through the inner bump.
【００１５】図３は、本発明による実施の更に他の形態
を示し、チップスタック型パッケージが示されている。
この実施の形態は、インターポーザーがプリント基板の
一部を形成する場合に実現が容易である。インターポー
ザー４のベースフィルム６は、プリント基板として形成
されている。第１チップ１とプリント基板６とはフリッ
プ実装され、第１チップ１とプリント基板６との間の隙
間には、液状の熱硬化性樹脂によるアンダーフィル１９
が充填されている。第２チップ２はフェースアップとな
るように、第１チップ１の裏面にペースト状或いはフィ
ルム状のマウント層３を介して接合されている。FIG. 3 shows still another embodiment according to the present invention, and shows a chip stack type package.
This embodiment is easy to realize when the interposer forms part of a printed circuit board. The base film 6 of the interposer 4 is formed as a printed board. The first chip 1 and the printed board 6 are flip-mounted, and an underfill 19 made of a liquid thermosetting resin is provided in a gap between the first chip 1 and the printed board 6.
Is filled. The second chip 2 is bonded to the back surface of the first chip 1 via a mount layer 3 in a paste or film shape so as to face up.
【００１６】ベースフィルム６の上面側に、上面側電極
２１が形成されている。第１電極パッド１１に位置合わ
せして、半田バンプ８が形成され、フリップチップ実装
後に、そのチップとインターポーザの間でアンダーフィ
ル１９が充填される。第１電極パッド１１は、半田バン
プ２２を介して上面側電極２１に接続している。このよ
うに、第１チップ１は、インターポザ４にフェースダウ
ンで搭載されてフリップチップ実装される。上面側電極
２１と金属配線層７とは、ベースフィルム６に形成され
るスルーホールを介して接続している。An upper electrode 21 is formed on the upper surface of the base film 6. A solder bump 8 is formed in alignment with the first electrode pad 11, and after flip-chip mounting, an underfill 19 is filled between the chip and the interposer. The first electrode pad 11 is connected to the upper electrode 21 via the solder bump 22. As described above, the first chip 1 is mounted face-down on the interposer 4 and flip-chip mounted. The upper electrode 21 and the metal wiring layer 7 are connected via a through hole formed in the base film 6.
【００１７】このように、２つのチップを裏面同士で接
合して積層化するため、すべての電極パッドは積層化チ
ップの両面に位置するようになる。この場合、インター
ポーザーと接する面側にある第１チップ１の電極パッド
は、インターポーザー４内に形成されたインナーバンプ
を用いて金属配線層と電気的に接続可能である。また、
インターポーザーと接しない面側にある第２チップ２の
電極パッドは、金属ワイヤを用いて金属配線層と電気的
に接続することができる。従って、配線上の制約からチ
ップサイズの組合せに制約が生じることはなく、同一サ
イズのチップであってもそれらのパッケージングが容易
に行える。また、金属ワイヤによる配線は第２チップと
金属配線層との接続にのみ使用され、パッケージ構造は
極めて単純になるだけでなく電極パッドのアクセス性が
向上する。このような第２チップとの簡単な電気的接続
の方法は、パッケージングにおける作業性及び集積性の
向上を可能とする。As described above, since the two chips are joined and laminated on the back surface, all the electrode pads are located on both sides of the laminated chip. In this case, the electrode pads of the first chip 1 on the side in contact with the interposer can be electrically connected to the metal wiring layer by using inner bumps formed in the interposer 4. Also,
The electrode pads of the second chip 2 on the side not in contact with the interposer can be electrically connected to the metal wiring layer using metal wires. Therefore, there is no restriction on the combination of chip sizes due to wiring restrictions, and packaging of chips of the same size can be easily performed. In addition, wiring using metal wires is used only for connection between the second chip and the metal wiring layer, so that not only the package structure becomes extremely simple, but also the accessibility of the electrode pads is improved. Such a simple method of electrical connection with the second chip makes it possible to improve workability and integration in packaging.
【００１８】[0018]
【発明の効果】本発明による積層化チップ半導体装置
は、立体配置されるチップの集積性が向上し、平面的サ
イズの拡大を抑制することができる。According to the laminated chip semiconductor device of the present invention, it is possible to improve the integration of chips arranged three-dimensionally and to suppress an increase in planar size.
【図１】図１は、本発明による積層化チップ半導体装置
の実施の形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a laminated chip semiconductor device according to the present invention.
【図２】図２は、本発明による積層化チップ半導体装置
の実施の他の形態を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the laminated chip semiconductor device according to the present invention.
【図３】図３は、本発明による積層化チップ半導体装置
の更に他の実施の他の形態を示す断面図である。FIG. 3 is a sectional view showing still another embodiment of the stacked chip semiconductor device according to the present invention.
【図４】図４は、公知のパッケージを示す断面図であ
る。FIG. 4 is a cross-sectional view showing a known package.
１…第１チップ ２…第２チップ ３…接合材 ４…インターポーザー １１…接続電極 １２…電極パッド １７…半田ボール ２１…接続電極 DESCRIPTION OF SYMBOLS 1 ... 1st chip 2 ... 2nd chip 3 ... Bonding material 4 ... Interposer 11 ... Connection electrode 12 ... Electrode pad 17 ... Solder ball 21 ... Connection electrode
Claims (8)
対向し、 前記第１チップと前記第２チップの表面側に電極が形成
されている積層化チップ半導体装置。A back surface of the first chip and a back surface of the second chip are opposed to each other, and a back surface of the first chip and a back surface of the second chip are opposed to each other; A laminated chip semiconductor device on which electrodes are formed.
間に接合材が介設されていることを特徴とする積層化チ
ップ半導体装置。2. The stacked chip semiconductor device according to claim 1, wherein a bonding material is interposed between the back side of the first chip and the back side of the second chip.
ポーザーに接合されていることを特徴とする積層化チッ
プ半導体装置。3. The stacked chip semiconductor device according to claim 1, wherein a surface of one of the chips is joined to an interposer.
を有していることを特徴とする積層化チップ半導体装
置。4. The laminated chip semiconductor device according to claim 3, wherein the interposer has a surface to be joined to a printed wiring board.
プの間に配設され、 前記第２チップの表面側に電極パッドが配置され、 前記接続電極と前記電極パッドの間は、ボンディングワ
イヤにより接続されていることを特徴とする積層化チッ
プ半導体装置。5. The interposer according to claim 3, wherein a connection electrode is formed on the interposer, the first chip is disposed between the interposer and the second chip, and an electrode pad is provided on a surface side of the second chip. Wherein the connection electrode and the electrode pad are connected by a bonding wire.
線を有し、 前記２層の金属配線はスルーホールを介して接続され、 前記第１チップの表面側に接続電極が配置され、 前記接続電極は前記金属配線に接続していることを特徴
とする積層化チップ半導体装置。6. The interposer according to claim 3, wherein the interposer has two layers of metal wiring on the front and back sides thereof, wherein the two layers of metal wiring are connected via through holes, and A connection electrode disposed on a side of the stacked chip semiconductor device, wherein the connection electrode is connected to the metal wiring.
徴とする積層化チップ半導体装置。7. The laminated chip semiconductor device according to claim 6, further comprising a solder bump, wherein the solder bump is connected to the metal wiring.
とする積層化チップ半導体装置。8. The stacked chip semiconductor device according to claim 1, wherein the two chips have the same planar shape.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11095091A JP2000294722A (en) | 1999-04-01 | 1999-04-01 | Laminated chip semiconductor device |
| KR1020000015422A KR20000076967A (en) | 1999-04-01 | 2000-03-27 | Laminate chip semiconductor device suitable for integration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11095091A JP2000294722A (en) | 1999-04-01 | 1999-04-01 | Laminated chip semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000294722A true JP2000294722A (en) | 2000-10-20 |
Family
ID=14128251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11095091A Pending JP2000294722A (en) | 1999-04-01 | 1999-04-01 | Laminated chip semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2000294722A (en) |
| KR (1) | KR20000076967A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001026155A1 (en) * | 1999-10-01 | 2001-04-12 | Seiko Epson Corporation | Semiconductor device, method and device for producing the same, circuit board, and electronic equipment |
| US6621156B2 (en) | 2001-01-24 | 2003-09-16 | Nec Electronics Corporation | Semiconductor device having stacked multi chip module structure |
| JP2010073893A (en) * | 2008-09-18 | 2010-04-02 | Shinko Electric Ind Co Ltd | Semiconductor device and production process thereof |
| JP2011023407A (en) * | 2009-07-13 | 2011-02-03 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| US7911064B2 (en) | 2005-03-07 | 2011-03-22 | Panasonic Corporation | Mounted body and method for manufacturing the same |
-
1999
- 1999-04-01 JP JP11095091A patent/JP2000294722A/en active Pending
-
2000
- 2000-03-27 KR KR1020000015422A patent/KR20000076967A/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001026155A1 (en) * | 1999-10-01 | 2001-04-12 | Seiko Epson Corporation | Semiconductor device, method and device for producing the same, circuit board, and electronic equipment |
| US6489687B1 (en) | 1999-10-01 | 2002-12-03 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment |
| US6621156B2 (en) | 2001-01-24 | 2003-09-16 | Nec Electronics Corporation | Semiconductor device having stacked multi chip module structure |
| US7911064B2 (en) | 2005-03-07 | 2011-03-22 | Panasonic Corporation | Mounted body and method for manufacturing the same |
| JP2010073893A (en) * | 2008-09-18 | 2010-04-02 | Shinko Electric Ind Co Ltd | Semiconductor device and production process thereof |
| JP2011023407A (en) * | 2009-07-13 | 2011-02-03 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| US8629001B2 (en) | 2009-07-13 | 2014-01-14 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000076967A (en) | 2000-12-26 |
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