JP2000285698A - Memory testing deivce - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the configuration of a memory testing device by using a multi-bit memory in a defect analyzing memory. SOLUTION: This semiconductor memory testing device is provided with a logical comparator 4 comparing data read out from a memory 3 to be tested with an expected value pattern signal and detecting a defective cell of the memory 3 to be tested, and a defect analyzing memory 7 storing a defective detected signal detected by the logical comparator 4 by accessing the same address as the memory 3 to be tested with position information of a defective cell of the memory 3 to be tested, a test in which contents are different is performed repeatedly for the same memory 3 to be tested. The defect analyzing memory 7 is composed of a multi-bit memory having plural data input/output terminals, and the device is provided with a control circuit 6 in which when uncoincidence is detected by the logical comparator 4, and uncoincidence detected signal detected by a test of the present time is added to a signal stored in the defect analyzing memory 7 in a test of the previous time. Also, when coincidence is detected by the logical comparator 4 in a test of the present time, an uncoincidence detected signal detected in a test of the present time is added to a signal stored in the defect analyzing memory 7 in a test of the previous time, these signals are stored in a multi- bit memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus, and more particularly to a memory test apparatus in which a failure analysis memory is constituted by a multi-bit memory.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a conventional memory test apparatus. The pattern generator 1 outputs a test pattern and an expected value pattern. The test pattern is provided to the memory under test 3 via the waveform generator 2. An address signal is added to the test pattern, and the memory under test 3 is accessed by the address signal to write and read the test pattern. The read data read from the memory under test 3 is supplied to a logical comparator 4, which compares the read data with an expected value pattern output from the pattern generator 1. A failure analysis memory 5 is provided on the output side of the logical comparator 4. The failure analysis memory 5 has the same address space as the memory under test 3 and is accessed by the same address signal as the memory 3 under test. When the mismatch is detected by the logical comparator 4, "1" indicating the occurrence of a failure is written into the failure analysis memory 5 at the address where the mismatch occurred. With this configuration, the position of the defective cell can be known by reading out the defect analysis memory 5 after the test and reading out the address where "1" is written.

The bit width of the memory under test 3 is
In many cases, input / output terminals are multi-bits such as 2, 4, 8, 16, and 32 bits. A memory having such a multi-bit input / output terminal is called a multi-bit memory, and most of the memories to be tested in the memory test are the multi-bit memories. Note that even when the bit width of the memory under test 3 is 1 bit, a plurality of 1-bit memories may be tested (so-called multiple units) at the same time. In order to test such multi-bit memory or 1-bit memory multi-cavity,
The failure analysis memory 5 also needs to have a multi-bit configuration. Conventionally, as shown in FIG. 4, 1-bit memories 51 to 5n are prepared as the failure analysis memory 5 by a required number of bits.

[0004]

However, if a plurality of 1-bit memories are individually prepared and configured as the failure analysis memory, the configuration becomes complicated as compared with the case where a multi-bit memory is used. However, if the multi-bit memory is used as it is, the following problem occurs.

When testing a multi-bit memory or a large number of 1-bit memories, the memory is initialized before the test to set all cells to "0". When a mismatch is detected by the logical comparator 4, "1" indicating the occurrence of a failure is written into the failure analysis memory 5 at the address where the mismatch occurred. When the logical comparator 4 detects a match, the failure analysis memory 5 employs a control method in which the address at which the match occurs retains the value in the memory. Therefore, data to be added to the failure analysis memory 5 is different depending on whether the detection result is defective or good, and it is necessary to set data for each bit channel to which data is to be added to the failure analysis memory 5.

However, if a multi-bit memory is used as the failure analysis memory 5, setting for each bit channel cannot be performed due to its structure. Therefore, "1" is written when a mismatch is detected, and an initial value is set when a match is detected. “0” cannot be held. That is, when "1" is written to one bit, "1" is also written to the remaining bits.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art by adopting a control method which makes it possible to set a bit channel substantially, and to provide a multi-bit memory as a failure analysis memory. An object of the present invention is to provide a memory test device that can be used.

[0008]

According to a first aspect of the present invention, there is provided a memory test apparatus for repeatedly performing tests having different contents on a memory under test having substantially n data input / output terminals. A logical comparator for detecting a defective cell of the memory under test by comparing read data read through n channels from the expected value pattern, and the logical comparator accessing the same address as that of the memory under test. A memory for storing the failure detection signal detected by the above-mentioned along with the position information of the defective cell of the memory under test via n channels, and having a plurality of data input / output terminals corresponding to the memory under test. A failure analysis memory constituted by a multi-bit memory. The memory under test having n data input / output terminals includes a case where a large number of 1-bit memories are taken in addition to a multi-bit memory.

Further, when a failure detection signal is detected by the logical comparator in the current test, the detection signal detected in the previous test is added to the failure detection signal, and a good detection is performed by the logical comparator in the current test. When a signal is detected, the detection signal detected in the previous test is added to the good detection signal,
A memory test apparatus comprising a control circuit for storing these added signals in a multi-bit memory constituting the failure analysis memory via the n channels. According to the present invention, the control circuit is provided between the failure analysis memory and the logical comparator, and the control method of the data input applied to the failure analysis memory is changed according to the detection result. Even if a multi-bit memory that cannot be set independently is used, correct writing according to the detection result can be performed. Therefore, the structure can be simplified as compared with a memory using n 1-bit memories as the failure analysis memory.

In a second aspect based on the first aspect, the control circuit temporarily stores a detection signal stored in the failure analysis memory in a previous test, and an output of the latch circuit. A memory test apparatus comprising: a gate circuit for taking an OR with a detection signal detected by the logical comparator in a test this time and storing the OR output in the failure analysis memory. According to the present invention, since the control circuit is constituted by a simple circuit including the latch circuit and the gate circuit, the structure can be further simplified.

[0011]

Embodiments of the present invention will be described below. FIG. 1 shows the configuration of the memory test apparatus according to the embodiment.

The pattern generator 1 outputs a test pattern and an expected value pattern. The test pattern is applied to a waveform generator 2, converted into an actual waveform by the waveform generator 2, and applied as a test pattern signal to a memory under test 3 consisting of n-bit, for example, 4-bit memory. An address signal is added to the test pattern data, and the memory under test 3 is accessed by the address signal to write and read the test pattern signal. The data read from the memory under test 3 is given to the logical comparator 4,
The logical comparator 4 compares the pattern with the expected value pattern output from the pattern generator 1.

A multi-bit memory on the output side of the logical comparator 4;
For example, a failure analysis memory 7 constituted by a 4-bit memory having four data input / output terminals 71... 74 is provided. The failure analysis memory 7 has the same address space as the memory under test 3 and is accessed by the same address signal as the memory 3 under test. A control circuit 6 for controlling the bit channel of the failure analysis memory 7 is provided between the logical comparator 4 and the failure analysis memory 7. The control circuit 6 has 1 to 4 channels according to the number of bits of the memory. Each of the channel circuits 61 to 64 includes a gate circuit 11 that ORs a latch output and a detection signal (defective detection signal / good detection signal), and a multiplexer 12 that selects one of the gate circuit output and the external input signal Din. , A driver 13 which shapes the waveform of the output of the multiplexer 12 and writes the waveform into the failure analysis memory 7
And a driver 14 for shaping the waveform of the data read from the failure analysis memory 7, and temporarily storing the output of the driver 14, and as a previous test result, the gate circuit 11
And a latch circuit 15 for adding to one input of the latch circuit. The output of the driver 14 is branched and output as a Dout signal outside the control circuit 6.

FIG. 2 is a timing chart for explaining the function of the control circuit 6 shown in FIG. Latch circuit 15
Reads the previous test result from the failure analysis memory 7 composed of a multi-bit memory at the first half of the timing when the memory address is accessed, and temporarily stores it until the next read timing. The latch output and the result (detection signal) obtained by ORing the current test result are written in the memory 7 at the latter half of the timing when the memory address is accessed.

Next, write control to the failure analysis memory according to the embodiment will be described with reference to FIG. 3 in comparison with a conventional example. Here, as a result of repeating three different tests on a specific cell, a good detection (Pass =
"0"), and in test 2, the failure detection (Fail =
“1”) and Test 3 illustrate a case where good detection (Pass = “0”) is performed.

Before the test, the memory is initialized to set all cells to "0". In the conventional example in which a plurality of 1-bit memories are used as the failure analysis memory, in test 1, the contents of the memory are left as they are, in test 2, "1" indicating the occurrence of a failure is written at the address where the mismatch occurred, The contents of the memory remain unchanged. On the other hand, in the embodiment in which one multi-bit memory is used as the failure analysis memory 7, in the test 1, "0" which is the result of the current test 1 is added to the result of the previous test (not the first time). In test 2, "1" is added to the result of test 1, and in test 3, "0" is added to the result of test 2. As can be seen from this embodiment, in each of the tests, a common control method is used for a channel in which the sum of the previous test result and the current test result is written to the failure analysis memory. Therefore, even if a multi-bit memory in which the channel cannot be individually set is used, there is no such a problem that a non-defective product is determined to be defective or an analysis for determining a defective to be non-defective is performed.

It is to be noted that the position of the defective cell can be known by reading the defect analysis memory 7 after the test and reading the address where "1" is written.

According to the above-described embodiment, since a multi-bit memory is used as the failure analysis memory, the circuit can be simplified as compared with the case where a plurality of 1-bit memories are used. The newly added control circuit is an existing L
Since it can be embedded in SI, it does not hinder simplification.

Further, when an attempt is made to protect data by using an SSRAM (synchronous SRAM) which can access a failure analysis memory at a high speed, the SSRAM has only a multi-bit memory and cannot be used in the conventional one. However, the present invention can be adopted and can be configured with a smaller number of memories than conventional memories because high-speed access is possible.

Here, a specific example in which the required number of memories of the conventional example and the present invention are compared will be described. For example, in a case where a memory test apparatus is operated at 200 MHz with four channels of 1 M words, the conventional one is 1M × 1 bit (15n).
In the case of using the 1-bit memory of s), the memory is expanded in units of one to make the interleaving 44 channels, so that 16 memories are required.

On the other hand, in the case of the present invention, 1M × 4
When a multi-bit memory of 15 bits (15 ns) is used, the interleaving is expanded in units of four to make 84 channels. From the above, eight memories are required. From this, it is clear that the present invention can simplify the configuration.

[0022]

According to the present invention, a control circuit is provided so that a channel can be commonly set, so that a multi-bit memory can be used as a failure analysis memory. Therefore, the structure can be simplified as compared with the case where a large number of memories are used as the failure analysis memory.

According to the present invention, the control circuit is constituted by a simple circuit including a latch circuit and a gate circuit.
The structure can be further simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory test device according to an embodiment.

FIG. 2 is a timing chart of a main part of FIG.

FIG. 3 is an explanatory diagram comparing write control contents for a failure analysis memory according to the embodiment and a conventional example.

FIG. 4 is a configuration diagram of a memory test device according to a conventional example.

[Explanation of symbols]

 Reference Signs List 3 memory under test 4 logic comparator 6 control circuit 7 failure analysis memory 11 gate circuit 15 latch circuit 71-74 data input / output terminal

Claims (2)

[Claims] 1. A memory test apparatus for performing tests having different contents repeatedly on a memory under test having substantially n data input / output terminals, wherein the memory under test is read out from the memory under test via n channels. A logical comparator for comparing the read data with the expected value pattern to detect a defective cell in the memory under test; and a defect detection signal detected by the logical comparator when the same address as the memory under test is accessed. A memory for storing via a number n of channels together with position information of a defective cell of a test memory, the failure analysis memory comprising a multi-bit memory having a plurality of data input / output terminals corresponding to the memory under test When a failure detection signal is detected by the logical comparator in the current test, the detection signal detected in the previous test is added to the failure detection signal, and the current test is performed. When a good detection signal is detected by the logical comparator, the detection signal detected in the previous test is added to the good detection signal, and the added signal is analyzed through the n channels for the failure analysis. A memory test apparatus comprising a control circuit for storing data in a multi-bit memory constituting a memory. 2. The control circuit according to claim 1, wherein said control circuit temporarily stores a detection signal stored in said failure analysis memory in a previous test, and said output of said latch circuit is detected by said logical comparator in a current test. 2. The memory test apparatus according to claim 1, further comprising: a gate circuit that takes an OR with the detected signal and stores the OR output in the failure analysis memory.