JP2000277726A - High breakdown strength semiconductor element - Google Patents
High breakdown strength semiconductor elementInfo
- Publication number
- JP2000277726A JP2000277726A JP11077198A JP7719899A JP2000277726A JP 2000277726 A JP2000277726 A JP 2000277726A JP 11077198 A JP11077198 A JP 11077198A JP 7719899 A JP7719899 A JP 7719899A JP 2000277726 A JP2000277726 A JP 2000277726A
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- conductivity
- semiconductor layer
- conductivity type
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015556 catabolic process Effects 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims description 302
- 230000002093 peripheral effect Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011002 quantification Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は高耐圧半導体素子に
係わり、終端構造と縦型スーパージャンクションを持つ
高耐圧半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a high breakdown voltage semiconductor device having a termination structure and a vertical super junction.
【０００２】[0002]
【従来の技術】近年のパワーエレクトロニクス分野にお
ける電源機器の小型化、高性能化への要求を受けて、パ
ワー半導体素子では、高耐圧・大電流化とともに、低損
失化、高速化、高破壊耐量化に対する性能改善が注力さ
れている。その中で、ストライプ状のｐ型半導体層とｎ
型半導体層が交互に繰り返して存在する、いわゆるスー
パージャンクション構造が考案されている。2. Description of the Related Art In response to recent demands for miniaturization and high performance of power supply devices in the field of power electronics, power semiconductor devices have high withstand voltage and large current, as well as low loss, high speed, and high breakdown resistance. Focus is on improving performance against quantification. Among them, a striped p-type semiconductor layer and n
A so-called super junction structure in which the type semiconductor layers are alternately repeated has been devised.
【０００３】このスーパージャンクション構造は、ダイ
オードやＭＯＳＦＥＴ等のパワー半導体素子に用いられ
た場合、オン状態において非常にオン抵抗が低くなると
ともに、オフ状態で容易に空乏化することから高耐圧特
性を示すという利点を持つ。[0003] When used in a power semiconductor device such as a diode or MOSFET, the super junction structure exhibits a high withstand voltage characteristic because it has a very low on resistance in an on state and is easily depleted in an off state. With the advantage that.
【０００４】例えば、特開平７−７１５４において示さ
れるように、パワーＭＯＳＦＥＴの内部領域にスーパー
ジャンクション構造に相当する補助領域を形成すること
が述べている。しかしながら、かかる補助領域では逆電
圧が印加された際にその電荷キャリアが空にされること
が開示されているのみであり、実際にスーパージャンク
ション構造を有する素子を実用化するに際して重要な終
端構造については具体的な開示はない。For example, as disclosed in Japanese Patent Application Laid-Open No. 7-7154, it is described that an auxiliary region corresponding to a super junction structure is formed in an internal region of a power MOSFET. However, it is only disclosed that the charge carriers are emptied when a reverse voltage is applied in such an auxiliary region, and a termination structure that is important in actually putting a device having a super junction structure into practical use is disclosed. Has no specific disclosure.
【０００５】[0005]
【発明が解決しようとする課題】本発明者らは、スーパ
ージャンクション構造を有する素子を実用化する場合
に、スーパージャンクション構造の最外部、特に終端構
造において、高耐圧化が不十分であり、これにより素子
の破壊が起こることを見出した。SUMMARY OF THE INVENTION The inventors of the present invention have found that when a device having a super junction structure is put into practical use, the withstand voltage is not sufficiently increased at the outermost portion of the super junction structure, particularly at the termination structure. It was found that destruction of the device occurred due to.
【０００６】本発明は、かかる実情に鑑みてなされたも
のであり、スーパージャンクション構造の高耐圧化を図
り素子破壊を防止する終端構造を提供することを目的と
するものである。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a termination structure that increases the breakdown voltage of a super junction structure and prevents element destruction.
【０００７】[0007]
【課題を解決するための手段】前述した課題を解決する
ために、本発明の第１は、第１導電型半導体領域と、こ
の第１導電型半導体領域に接して形成された第１導電型
半導体層と、前記第１導電型半導体領域及び前記第１導
電型半導体層に接して形成された第２導電型半導体層
と、前記第１導電型半導体層及び前記第２導電型半導体
層に接して形成された第２導電型半導体領域とを備え、
前記第１導電型半導体層及び前記第２導電型半導体層は
交互に繰り返して配置されており、その最外部の第１導
電型半導体層又は前記第２導電型半導体層の層厚み方向
のキャリア濃度の積分値が、その内部に配置された前記
第１導電型半導体層及び前記第２導電型半導体層の層厚
み方向のキャリア濃度の積分値の概略半分であることを
特徴とする高耐圧半導体素子を提供する。In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a first conductive type semiconductor region and a first conductive type semiconductor region formed in contact with the first conductive type semiconductor region. A semiconductor layer, a second conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor region and the first conductivity type semiconductor layer, and a semiconductor layer in contact with the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A second conductivity type semiconductor region formed by
The first conductivity type semiconductor layer and the second conductivity type semiconductor layer are alternately and repeatedly arranged, and a carrier concentration in a thickness direction of the outermost first conductivity type semiconductor layer or the second conductivity type semiconductor layer is arranged. Is approximately half the integral value of the carrier concentration in the thickness direction of the first conductive type semiconductor layer and the second conductive type semiconductor layer disposed therein. I will provide a.
【０００８】また、本発明の第２は、第１導電型半導体
領域と、第２導電型半導体領域と、これらの第１導電型
半導体領域と第２導電型半導体領域との間に挟まれて形
成され、交互に繰り返して配置された第１導電型半導体
層及び第２導電型半導体層とを備え、この第１導電型半
導体層及び第２導電型半導体層の繰り返し配置方向は、
前記第１導電型半導体領域と前記第２導電型半導体領域
とを結ぶ方向に対して概略垂直であるとともに、前記第
１導電型半導体層はオン状態でドリフト電流を流すとと
もにオフ状態で空乏化し、前記第２導電型半導体層はオ
フ状態で空乏化し、かつ最外部の第１導電型半導体層又
は前記第２導電型半導体層の層厚み方向のキャリア濃度
の積分値が、その内部に配置された前記第１導電型半導
体層及び前記第２導電型半導体層の層厚み方向のキャリ
ア濃度の積分値の概略半分であることを特徴とする高耐
圧半導体素子を提供する。A second aspect of the present invention is a first conductivity type semiconductor region, a second conductivity type semiconductor region, and a semiconductor device sandwiched between the first conductivity type semiconductor region and the second conductivity type semiconductor region. A first conductivity type semiconductor layer and a second conductivity type semiconductor layer which are formed and arranged alternately and repeatedly. The direction in which the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are repeatedly arranged is:
While being substantially perpendicular to the direction connecting the first conductivity type semiconductor region and the second conductivity type semiconductor region, the first conductivity type semiconductor layer flows a drift current in an on state and is depleted in an off state, The second conductivity type semiconductor layer is depleted in the off state, and the integrated value of the carrier concentration in the outermost first conductivity type semiconductor layer or the layer thickness direction of the second conductivity type semiconductor layer is disposed therein. A high-breakdown-voltage semiconductor element is provided, wherein the integrated value is approximately half the integral value of the carrier concentration in the thickness direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.
【０００９】また、本発明の第３は、高濃度第１導電型
半導体領域と、この高濃度第１導電型半導体領域に接し
て形成された第１導電型半導体層と、前記高濃度第１導
電型半導体領域及び前記第１導電型半導体層に接して形
成された第２導電型半導体層と、前記第１導電型半導体
層及び前記第２導電型半導体層に接して形成された高濃
度第２導電型半導体領域と、前記第１導電型半導体層及
び前記第２導電型半導体層を取り囲んで形成された低濃
度第１導電型半導体領域と、この低濃度第１導電型半導
体領域及び前記高濃度第２導電型半導体領域に接して形
成され、前記高濃度第２導電型半導体領域より低濃度の
低濃度第２導電型半導体領域とを備え、前記第１導電型
半導体層及び前記第２導電型半導体層は交互に繰り返し
て配置されており、その最外部の第１導電型半導体層又
は前記第２導電型半導体層の層厚み方向のキャリア濃度
の積分値が、その内部に配置された前記第１導電型半導
体層及び前記第２導電型半導体層の層厚み方向のキャリ
ア濃度の積分値の概略半分であることを特徴とする高耐
圧半導体素子を提供する。A third aspect of the present invention is a high-concentration first-conductivity-type semiconductor region, a first-conductivity-type semiconductor layer formed in contact with the high-concentration first-conductivity-type semiconductor region, A second conductive type semiconductor layer formed in contact with the conductive type semiconductor region and the first conductive type semiconductor layer; and a high concentration semiconductor layer formed in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer. A two-conductivity-type semiconductor region; a low-concentration first-conductivity-type semiconductor region formed surrounding the first and second-conductivity-type semiconductor layers; A low-concentration second-conductivity-type semiconductor region formed in contact with the second-concentration second-conductivity-type semiconductor region and having a lower concentration than the high-concentration second-conductivity-type semiconductor region; Type semiconductor layers are arranged alternately and repeatedly. The outermost first conductivity type semiconductor layer or the second conductivity type semiconductor layer has an integrated value of a carrier concentration in a thickness direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. Provided is a high withstand voltage semiconductor device, wherein the integrated value is approximately half of the integral value of the carrier concentration in the layer thickness direction of the layer.
【００１０】また、本発明の第４は、高濃度第１導電型
半導体領域と、高濃度第２導電型半導体領域と、これら
の高濃度第１導電型半導体領域と高濃度第２導電型半導
体領域との間に挟まれて形成され、交互に繰り返して配
置された第１導電型半導体層及び第２導電型半導体層
と、これらの第１導電型半導体層及び第２導電型半導体
層を取り囲んで形成された低濃度第１導電型半導体領域
と、この低濃度第１導電型半導体領域及び前記高濃度第
２導電型半導体領域に接して形成され、前記高濃度第２
導電型半導体領域より低濃度の低濃度第２導電型半導体
領域とを備え、前記第１導電型半導体層及び第２導電型
半導体層の繰り返し配置方向は、前記高濃度第１導電型
半導体領域と前記高濃度第２導電型半導体領域とを結ぶ
方向に対して概略垂直であるとともに、前記第１導電型
半導体層はオン状態でドリフト電流を流すとともにオフ
状態で空乏化し、前記第２導電型半導体層はオフ状態で
空乏化し、かつ最外部の第１導電型半導体層又は前記第
２導電型半導体層の層厚み方向のキャリア濃度の積分値
が、その内部に配置された前記第１導電型半導体層及び
前記第２導電型半導体層の層厚み方向のキャリア濃度の
積分値の概略半分であることを特徴とする高耐圧半導体
素子を提供する。A fourth aspect of the present invention is a high-concentration first-conductivity-type semiconductor region, a high-concentration second-conductivity-type semiconductor region, and a high-concentration first-conductivity-type semiconductor region and a high-concentration second-conductivity-type semiconductor region. A first conductivity type semiconductor layer and a second conductivity type semiconductor layer which are formed and alternately and repeatedly arranged between the first and second conductivity type semiconductor layers; and surround the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. The low-concentration first conductivity type semiconductor region formed by the above, and the low-concentration first conductivity-type semiconductor region and the high-concentration second conductivity-type semiconductor region are formed in contact with the low-concentration second conductivity-type semiconductor region.
A low-concentration second conductivity-type semiconductor region having a lower concentration than the conductivity-type semiconductor region; and the first and second conductivity-type semiconductor layers are repeatedly arranged in the same direction as the high-concentration first conductivity-type semiconductor region. The second conductivity type semiconductor layer is substantially perpendicular to a direction connecting the high concentration second conductivity type semiconductor region, and the first conductivity type semiconductor layer flows a drift current in an on state and is depleted in an off state. The layer is depleted in the off state, and the integrated value of the carrier concentration in the thickness direction of the outermost first conductivity type semiconductor layer or the second conductivity type semiconductor layer is the first conductivity type semiconductor layer disposed therein. A high withstand voltage semiconductor device characterized in that the integrated value of the carrier concentration in the layer thickness direction of the layer and the second conductivity type semiconductor layer is approximately half.
【００１１】また、本発明の第５は、高濃度第１導電型
半導体領域と、この高濃度第１導電型半導体領域に接し
て形成された第１導電型半導体層と、前記高濃度第１導
電型半導体領域及び前記第１導電型半導体層に接して形
成された第２導電型半導体層と、前記第１導電型半導体
層及び前記第２導電型半導体層に接して形成された高濃
度第２導電型半導体領域と、前記第１導電型半導体層及
び前記第２導電型半導体層を取り囲んで形成された低濃
度第１導電型半導体領域と、この低濃度第１導電型半導
体領域に接して形成され、前記高濃度第２導電型半導体
領域を取り囲むように当該領域から離間して設けられた
リング状の第２導電型半導体領域層とを備え、前記第１
導電型半導体層及び前記第２導電型半導体層は交互に繰
り返して配置されており、その最外部の第１導電型半導
体層又は前記第２導電型半導体層の層厚み方向のキャリ
ア濃度の積分値が、その内部に配置された前記第１導電
型半導体層及び前記第２導電型半導体層の層厚み方向の
キャリア濃度の積分値の概略半分であることを特徴とす
る高耐圧半導体素子を提供する。A fifth aspect of the present invention is a high-concentration first-conductivity-type semiconductor region, a first-conductivity-type semiconductor layer formed in contact with the high-concentration first-conductivity-type semiconductor region, A second conductive type semiconductor layer formed in contact with the conductive type semiconductor region and the first conductive type semiconductor layer; and a high concentration semiconductor layer formed in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer. A two-conductivity-type semiconductor region; a low-concentration first-conductivity-type semiconductor region formed surrounding the first and second-conductivity-type semiconductor layers; A ring-shaped second conductivity type semiconductor region layer formed so as to surround the high concentration second conductivity type semiconductor region and spaced apart from the region.
The conductive semiconductor layer and the second conductive semiconductor layer are alternately and repeatedly arranged, and the integral value of the carrier concentration in the thickness direction of the outermost first conductive semiconductor layer or the second conductive semiconductor layer is arranged. Is approximately half the integrated value of the carrier concentration in the thickness direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer disposed therein. .
【００１２】さらにまた、本発明の第６は、高濃度第１
導電型半導体領域と、高濃度第２導電型半導体領域と、
これらの高濃度第１導電型半導体電極層と高濃度第２導
電型半導体電極層との間に挟まれて形成され、交互に繰
り返して配置された第１導電型半導体層及び第２導電型
半導体層と、これらの第１導電型半導体層及び第２導電
型を取り囲んで形成された低濃度第１導電型半導体領域
と、この低濃度第１導電型半導体領域に接して形成さ
れ、前記高濃度第２導電型半導体領域を取り囲むように
当該領域から離間して設けられたリング状の第２導電型
半導体領域層とを備え、前記第１導電型半導体層及び第
２導電型半導体層の繰り返し配置方向は、前記高濃度第
１導電型半導体領域と前記高濃度第２導電型半導体領域
とを結ぶ方向に対して概略垂直であるとともに、前記第
１導電型半導体層はオン状態でドリフト電流を流すとと
もにオフ状態で空乏化し、前記第２導電型半導体層はオ
フ状態で空乏化し、かつ最外部の第１導電型半導体層又
は前記第２導電型半導体層の層厚み方向のキャリア濃度
の積分値が、その内部に配置された前記第１導電型半導
体層及び前記第２導電型半導体層の層厚み方向のキャリ
ア濃度の積分値の概略半分であることを特徴とする高耐
圧半導体素子を提供する。Further, a sixth aspect of the present invention is a high-concentration first
A conductive semiconductor region, a high-concentration second conductive semiconductor region,
The first conductivity type semiconductor layer and the second conductivity type semiconductor are formed between the high concentration first conductivity type semiconductor electrode layer and the high concentration second conductivity type semiconductor electrode layer, and are alternately and repeatedly arranged. A low-concentration first-conductivity-type semiconductor region formed surrounding the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer; A ring-shaped second conductivity type semiconductor region layer provided separately from the second conductivity type semiconductor region so as to surround the second conductivity type semiconductor region, and the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are repeatedly arranged. A direction is substantially perpendicular to a direction connecting the high-concentration first conductivity type semiconductor region and the high-concentration second conductivity type semiconductor region, and the first conductivity type semiconductor layer allows a drift current to flow in an on state. Depleted with off The second conductivity type semiconductor layer is depleted in the off state, and the integrated value of the carrier concentration in the outermost first conductivity type semiconductor layer or the layer thickness direction of the second conductivity type semiconductor layer is disposed therein. A high breakdown voltage semiconductor element, wherein the integrated value of the carrier concentration in the thickness direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer is approximately half.
【００１３】上述した本発明の第３、４においては、前
記第２導電型半導体領域はオフ状態で空乏化し、その空
乏領域は前記第１導電型半導体層及び前記第２導電型半
導体層において空乏化により生ずる空乏領域と接するこ
とが好ましい。In the third and fourth aspects of the present invention, the second conductivity type semiconductor region is depleted in an off state, and the depletion region is depleted in the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. It is preferable to contact with a depletion region generated by the formation.
【００１４】また、上述した本発明の第５、６において
は、前記リング状の第２導電型半導体領域層に接する低
濃度第１導電型半導体領域はオフ状態で空乏化し、その
空乏領域は前記第１導電型半導体層及び前記第２導電型
半導体層において空乏化により生ずる空乏領域と接する
ことが好ましい。In the fifth and sixth aspects of the present invention described above, the low-concentration first-conductivity-type semiconductor region in contact with the ring-shaped second-conductivity-type semiconductor region layer is depleted in an off state, and the depletion region is in the depletion region. It is preferable that the first conductive type semiconductor layer and the second conductive type semiconductor layer are in contact with a depletion region generated by depletion.
【００１５】また、上述した各発明において、前記第１
導電型半導体層及び前記第２導電型半導体層は、お互い
に平行なストライプ状の層であることが好ましい。さら
に、前記第１導電型半導体層及び前記第２導電型半導体
層は、奇数個存在することが好ましい。さらにまた、前
記高耐圧半導体素子は縦型の構造を有するものであるこ
とが好ましい。In each of the above-mentioned inventions,
The conductive semiconductor layer and the second conductive semiconductor layer are preferably striped layers parallel to each other. Further, it is preferable that an odd number of the first conductive type semiconductor layers and the second conductive type semiconductor layers exist. Furthermore, it is preferable that the high withstand voltage semiconductor element has a vertical structure.
【００１６】[0016]
【発明の実施の形態】以下、本発明の実施形態について
図面を参照しつつ詳細に説明する。 （第１の実施形態）図１は、本発明の第１の実施形態に
係る高耐圧半導体素子の構造を示す上面図である。図２
は、図１の点線ＡＡ´を通る断面における断面図であ
る。この断面図では図１の素子構造の半分のみを示して
いる。Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) FIG. 1 is a top view showing the structure of a high breakdown voltage semiconductor device according to a first embodiment of the present invention. FIG.
FIG. 2 is a cross-sectional view taken along a dotted line AA ′ in FIG. This cross-sectional view shows only half of the element structure of FIG.
【００１７】図１、図２に示される高耐圧半導体素子は
縦型のダイオードに係るものである。これらの図に示す
ように、本実施形態の縦型のダイオードは、低濃度のｎ
型層５の一方の面に高濃度のｎ型層１０が形成され、ま
た他方の面には高濃度のｐ型層３が選択的に形成されて
おり、これらのｎ型層１０とｐ型層３との間にはスーパ
ージャンクション構造が設けられている。このスーパー
ジャンクション構造は、ストライプ状のｐ型層１とｎ型
層２が交互に繰り返して設けられており、その数は奇数
個である。素子上面から見た場合、かかるストライプ状
のｐ型層１とｎ型層２の存在領域は高濃度のｐ型層３の
存在領域の中に含まれた形となっている。本来ならばス
トライプ状のｐ型層１とｎ型層２とは高濃度のｐ型層３
の下に隠れていて見えない筈であるが、分かりやすくす
るためにここでは電極等を省略してスーパージャンクシ
ョン構造を示した。The high breakdown voltage semiconductor device shown in FIGS. 1 and 2 relates to a vertical diode. As shown in these figures, the vertical diode of the present embodiment has a low concentration of n.
A high concentration n-type layer 10 is formed on one surface of the mold layer 5 and a high concentration p-type layer 3 is selectively formed on the other surface. A super junction structure is provided between the layer 3. In this super junction structure, stripe-shaped p-type layers 1 and n-type layers 2 are provided alternately and repeatedly, and the number thereof is an odd number. When viewed from the upper surface of the element, the existence region of the striped p-type layer 1 and the n-type layer 2 is included in the existence region of the high-concentration p-type layer 3. Originally, the p-type layer 1 and the n-type layer 2 in the form of stripes are composed of the high-concentration p-type layer 3.
Although it should not be visible because it is hidden underneath, the electrodes and the like are omitted here for simplicity, and the super junction structure is shown.
【００１８】その最外部のｐ型層１の層厚み方向のキャ
リア濃度の積分値は、一番外側を除いた残りの内部に配
置されたｐ型層１とｎ型層２の層厚み方向のキャリア濃
度の積分値の概略半分となっている。これらの一番外側
を除いた残りのｐ型層１とｎ型層２の層厚み方向のキャ
リア濃度の積分値は一定となっている。ここでは一番外
側のストライプ状の層をｐ型層１としたが、ｎ型層２で
あっても上記キャリア濃度積分値の条件を満たせば効果
は同様である。The integrated value of the carrier concentration in the layer thickness direction of the outermost p-type layer 1 is calculated by calculating the integrated value of the p-type layer 1 and the n-type layer 2 disposed inside except for the outermost layer. It is approximately half of the integral value of the carrier concentration. The integral value of the carrier concentration in the layer thickness direction of the remaining p-type layer 1 and n-type layer 2 excluding the outermost layer is constant. Here, the outermost stripe-shaped layer is the p-type layer 1, but the same effect can be obtained with the n-type layer 2 as long as the above-described condition of the carrier concentration integral value is satisfied.
【００１９】例えば、一番外側のｐ型層１の濃度及び厚
みを１×１０15ｃｍ-3、３．５μｍ、或いは５×１０14
ｃｍ-3、７．０μｍ、一番外側を除いた残りの内部に配
置されたｐ型層１とｎ型層２の濃度及び厚みを、それぞ
れ１×１０15ｃｍ-3、７．０μｍとすることが可能であ
り、かかる条件の下で上記キャリア濃度積分値の条件を
満足する。したがって、例えば逆電圧４０００Ｖを印加
する条件下では、ＯＦＦ状態において上記スーパージャ
ンクション構造はその最外周部分においても完全空乏化
し高耐圧特性を示すようになる。For example, the concentration and thickness of the outermost p-type layer 1 are 1 × 10 15 cm −3 , 3.5 μm, or 5 × 10 14
cm -3, 7.0 .mu.m, most outside the remaining layer 1 and the n-type layer 2 p-type which is disposed within the concentration and thickness excluding each 1 × 10 15 cm -3, and 7.0 .mu.m It is possible to satisfy the above-mentioned condition of the carrier concentration integrated value under such conditions. Therefore, for example, under the condition that a reverse voltage of 4000 V is applied, in the OFF state, the super junction structure is completely depleted even in the outermost peripheral portion, and exhibits a high breakdown voltage characteristic.
【００２０】ストライプ状のｐ型層１とｎ型層２と接す
る高濃度のｐ型層３は、低濃度のｐ型層４（例えば、濃
度は１×１０13ｃｍ-3。後述する実施形態も同様。）で
囲まれており、この層がリサーフ層として電界を緩和す
る働きをする。例えば、ｐ型層３の深さは６．０μｍ、
濃度は２×１０17ｃｍ-3であり、また、ｐ型層４の深さ
は５．０μｍ、濃度は３×１０15ｃｍ-3である。The high-concentration p-type layer 3 in contact with the striped p-type layer 1 and the n-type layer 2 is a low-concentration p-type layer 4 (for example, the concentration is 1 × 10 13 cm −3 . This layer also functions as a RESURF layer to reduce the electric field. For example, the depth of the p-type layer 3 is 6.0 μm,
The concentration is 2 × 10 17 cm −3 , the depth of the p-type layer 4 is 5.0 μm, and the concentration is 3 × 10 15 cm −3 .
【００２１】かかる条件の下では、ｐ型層４とｎ型ベー
ス層５とのｐｎ接合から伸びる空乏層は上記スーパージ
ャンクション構造において形成される空乏層と完全に接
続され、この終端部分における耐圧を十分に確保するこ
とが可能である。例えば逆電圧４０００Ｖを印加する条
件下では、ＯＦＦ状態において上記スーパージャンクシ
ョン構造の終端部分は完全空乏化し高耐圧特性を示すよ
うになる。Under these conditions, the depletion layer extending from the pn junction between the p-type layer 4 and the n-type base layer 5 is completely connected to the depletion layer formed in the super junction structure. It is possible to secure enough. For example, under the condition that a reverse voltage of 4000 V is applied, the terminal portion of the super junction structure is completely depleted in the OFF state and exhibits high withstand voltage characteristics.
【００２２】なお、図１、図２において、６は高濃度の
ｎ型ストッパー層であり、リサーフ層であるｐ型層４か
ら伸びる空乏層が基板エッジ部分にまで到達することを
防止して耐圧を確保するために設けられる。また、７は
絶縁膜、８はアノード電極、９はストッパー電極、１１
はカソード電極である。In FIGS. 1 and 2, reference numeral 6 denotes a high-concentration n-type stopper layer which prevents a depletion layer extending from the p-type layer 4 which is a RESURF layer from reaching the edge of the substrate. Is provided to ensure 7 is an insulating film, 8 is an anode electrode, 9 is a stopper electrode, 11
Is a cathode electrode.
【００２３】以上述べた構造による縦型のスーパージャ
ンクション構造を有するダイオードによれば、ＯＦＦ状
態においてスーパージャンクション構造はその最外周部
分においても完全空乏化し高耐圧特性を示すようにな
る。また、ＯＦＦ状態においてスーパージャンクション
構造の終端部分において完全空乏化を図り高耐圧特性を
確保することが可能である。According to the diode having the vertical super junction structure having the above-described structure, the super junction structure is completely depleted even in the outermost peripheral portion in the OFF state, and exhibits a high breakdown voltage characteristic. Further, in the OFF state, complete depletion can be achieved at the terminal portion of the super junction structure, and high breakdown voltage characteristics can be secured.
【００２４】図３は、図１に示す本実施形態に係る縦形
のダイオードの漏れ電流特性を示す特性図である。横軸
は印加電圧、縦軸は漏れ電流を示している。図３に示さ
れるように本実施形態に係る縦形のダイオードは４４０
０Ｖ程度の耐圧を持っていることがわかる。また、かか
るダイオードのオン抵抗は０．０３Ωｃｍ2 であり、非
常に低いオン抵抗を示した。FIG. 3 is a characteristic diagram showing leakage current characteristics of the vertical diode according to the present embodiment shown in FIG. The horizontal axis shows the applied voltage, and the vertical axis shows the leakage current. As shown in FIG. 3, the vertical diode according to this embodiment is 440
It turns out that it has a withstand voltage of about 0V. In addition, the on-resistance of such a diode was 0.03 Ωcm 2 , indicating a very low on-resistance.
【００２５】（第２の実施形態）図４は、本発明の第２
の実施形態に係る高耐圧半導体素子の構造を示す上面図
である。図５は、図４の点線ＢＢ´を通る断面における
断面図である。この断面図では図４の素子構造の半分の
みを示している。なお、図１と同一部分には同一符号を
付して示し詳細な説明は省略する。(Second Embodiment) FIG. 4 shows a second embodiment of the present invention.
FIG. 4 is a top view showing the structure of the high breakdown voltage semiconductor element according to the embodiment. FIG. 5 is a cross-sectional view of a cross section taken along a dotted line BB ′ in FIG. This cross-sectional view shows only half of the element structure of FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.
【００２６】本実施形態の高耐圧半導体素子も縦型のダ
イオードに係るものである。図４、図５に示すように、
本実施形態の縦型のダイオードが第１の実施形態のダイ
オードと異なる点は、ストライプ状のｐ型層１とｎ型層
２と接する高濃度のｐ型層３を囲む低濃度のｐ型層（リ
サーフ層）４の代わりに、複数の同心円状の高濃度のｐ
型層（ガードリング層）１２が設けられている点であ
る。かかるｐ型層（ガードリング層）１２はｐ型層３の
周囲を取り囲むように設けられており、このｐ型層１２
がリサーフ層と同様に電界を緩和する働きをする。例え
ば、ｐ型層３の深さは６．０μｍ、濃度は２×１０17ｃ
ｍ-3であり、また、ｐ型層１２の深さは６．０μｍ、幅
は１０．０μｍ、濃度は５×１０18ｃｍ-3、ｐ型層３か
らの距離は１０．０μｍ、お互いの間隔は１０．０〜４
０．０μｍである。The high breakdown voltage semiconductor device of the present embodiment also relates to a vertical diode. As shown in FIGS. 4 and 5,
The vertical diode of the present embodiment is different from the diode of the first embodiment in that a low-concentration p-type layer surrounding a high-concentration p-type layer 3 in contact with a striped p-type layer 1 and n-type layer 2. (Resurf layer) Instead of 4, a plurality of concentric high concentration p
The point is that a mold layer (guard ring layer) 12 is provided. The p-type layer (guard ring layer) 12 is provided so as to surround the periphery of the p-type layer 3.
Acts to alleviate the electric field similarly to the RESURF layer. For example, the depth of the p-type layer 3 is 6.0 μm and the concentration is 2 × 10 17 c
m −3 , the depth of the p-type layer 12 is 6.0 μm, the width is 10.0 μm, the concentration is 5 × 10 18 cm −3 , the distance from the p-type layer 3 is 10.0 μm, The interval is 10.0-4
0.0 μm.
【００２７】かかる条件の下では、上記スーパージャン
クション構造において第１の実施形態と同様に完全空乏
化が達成されるとともに、ｐ型層１２とｎ型ベース層５
とのｐｎ接合から伸びる空乏層は上記スーパージャンク
ション構造の空乏層と完全に接続され、この終端部分に
おける耐圧を十分に確保することが可能である。例えば
逆電圧４０００Ｖを印加する条件下では、ＯＦＦ状態に
おいて上記スーパージャンクション構造の終端部分は完
全空乏化し図３と同様な高耐圧特性を示すことがわかっ
た。また、かかるダイオードのオン抵抗は０．０３Ωｃ
ｍ2 であり、非常に低いオン抵抗を示した。Under these conditions, complete depletion is achieved in the super junction structure as in the first embodiment, and the p-type layer 12 and the n-type base layer 5 are formed.
A depletion layer extending from the pn junction with the depletion layer is completely connected to the depletion layer of the super junction structure, and it is possible to secure a sufficient withstand voltage at the terminal portion. For example, it was found that under the condition of applying a reverse voltage of 4000 V, in the OFF state, the terminal portion of the super junction structure was completely depleted, and exhibited high breakdown voltage characteristics similar to FIG. The on-resistance of such a diode is 0.03Ωc
m 2 , indicating a very low on-resistance.
【００２８】（第３の実施形態）図６は、本発明の第３
の実施形態に係る高耐圧半導体素子の構造を示す断面斜
視図である。図１と同一部分には同一符号を付して示し
詳細な説明は省略する。(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
FIG. 4 is a cross-sectional perspective view showing a structure of a high breakdown voltage semiconductor element according to the embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.
【００２９】図６に示すように、本実施形態の高耐圧半
導体素子は縦型のプレーナ型ＭＯＳ構造を有する素子
（例えばＭＯＳＦＥＴ）である。低濃度のｎ型層（ベー
ス層）５の一方の面には高濃度のｎ型ドレイン層１５が
形成され、また他方の面にはｐ型ベース層１３が選択的
に形成されており、これらのｎ型ドレイン層１５とｐ型
ベース層１３との間には第１の実施形態と同様のスーパ
ージャンクション構造（ｐ型層１とｎ型層２）が設けら
れている。As shown in FIG. 6, the high breakdown voltage semiconductor device of this embodiment is a device (for example, MOSFET) having a vertical planar MOS structure. On one surface of the low-concentration n-type layer (base layer) 5, a high-concentration n-type drain layer 15 is formed, and on the other surface, a p-type base layer 13 is selectively formed. A super junction structure (p-type layer 1 and n-type layer 2) similar to that of the first embodiment is provided between the n-type drain layer 15 and the p-type base layer 13.
【００３０】ｐ型ベース層１３の表面には選択的にｎ型
ソース層１４が形成され、スーパージャンクション構造
（ｐ型層１とｎ型層２）、ｎ型ソース層１４、及びｐ型
ベース層１３の表面上には、ゲート絶縁膜（シリコン酸
化膜等）１６を介してゲート電極１７が設けられてい
る。この実施形態の場合には、ゲート絶縁膜１６及びゲ
ート電極１７はスーパージャンクション構造（ｐ型層１
とｎ型層２）の部分まで延在している。これにより、効
率よくスーパージャンクション構造に電子を注入するこ
とが可能である。An n-type source layer 14 is selectively formed on the surface of the p-type base layer 13, and has a super junction structure (p-type layer 1 and n-type layer 2), an n-type source layer 14, and a p-type base layer. On the surface of 13, a gate electrode 17 is provided via a gate insulating film (such as a silicon oxide film) 16. In this embodiment, the gate insulating film 16 and the gate electrode 17 have a super junction structure (p-type layer 1).
And the n-type layer 2). As a result, electrons can be efficiently injected into the super junction structure.
【００３１】本実施形態に係るＭＯＳ構造を有する素子
も、ＯＦＦ状態においてスーパージャンクション構造は
その最外周部分においても完全空乏化し高耐圧特性を示
すようになる。また、ＯＦＦ状態において、ｐ型層４と
ｎ型層５とのｐｎ接合から伸びる空乏層は上記スーパー
ジャンクション構造において形成される空乏層と完全に
接続され、この終端部分における耐圧を十分に確保する
ことが可能である。本実施形態では、終端構造としてリ
サーフ層（ｐ型層４）を示したが、図４、図５に示した
ガードリング層（ｐ型層１２）を用いても高耐圧を得る
ことができた。また、終端構造がリサーフ層であって
も、ガードリング層であっても、オン抵抗は非常に低か
った。In the device having the MOS structure according to the present embodiment, the super junction structure in the OFF state is also completely depleted even in the outermost peripheral portion, and exhibits a high breakdown voltage characteristic. In the OFF state, the depletion layer extending from the pn junction between the p-type layer 4 and the n-type layer 5 is completely connected to the depletion layer formed in the super junction structure, and ensures a sufficient breakdown voltage at the terminal portion. It is possible. In this embodiment, the RESURF layer (p-type layer 4) is shown as the termination structure. However, a high breakdown voltage can be obtained even by using the guard ring layer (p-type layer 12) shown in FIGS. . Also, whether the termination structure was a RESURF layer or a guard ring layer, the ON resistance was very low.
【００３２】（第４の実施形態）図７は、本発明の第４
の実施形態に係る高耐圧半導体素子の構造を示す断面斜
視図である。図６と同一部分には同一符号を付して示し
詳細な説明は省略する。(Fourth Embodiment) FIG. 7 shows a fourth embodiment of the present invention.
FIG. 4 is a cross-sectional perspective view showing a structure of a high breakdown voltage semiconductor element according to the embodiment. The same parts as those in FIG. 6 are denoted by the same reference numerals, and detailed description will be omitted.
【００３３】図７に示すように、本実施形態の高耐圧半
導体素子は縦型のトレンチ型ＭＯＳ構造を有する素子
（例えばＭＯＳＦＥＴ）である。ｐ型ベース層２３が低
濃度のｎ型層（ベース層）５の一方の面に選択的に形成
されており、このｐ型ベース層２３とｎ型ドレイン層１
５との間には第１の実施形態と同様のスーパージャンク
ション構造（ｐ型層１とｎ型層２）が設けられている。As shown in FIG. 7, the high breakdown voltage semiconductor device of this embodiment is a device (for example, a MOSFET) having a vertical trench MOS structure. The p-type base layer 23 is selectively formed on one surface of the low-concentration n-type layer (base layer) 5, and the p-type base layer 23 and the n-type drain layer 1 are formed.
5, a super junction structure (p-type layer 1 and n-type layer 2) similar to that of the first embodiment is provided.
【００３４】ｐ型ベース層２３の表面には選択的にｎ型
ソース層２４が形成され、これらのｎ型ソース層２４及
びｐ型ベース層２３を貫通してトレンチ２８が設けられ
ている。このトレンチ２８はスーパージャンクション構
造（ｐ型層１とｎ型層２）が設けられたｎ型層５に到達
するように形成されている。トレンチ２８の内部にはゲ
ート絶縁膜（シリコン酸化膜等）２６を介してゲート電
極２７が設けられている。An n-type source layer 24 is selectively formed on the surface of the p-type base layer 23, and a trench 28 is provided through the n-type source layer 24 and the p-type base layer 23. The trench 28 is formed so as to reach the n-type layer 5 provided with the super junction structure (the p-type layer 1 and the n-type layer 2). A gate electrode 27 is provided inside the trench 28 via a gate insulating film (such as a silicon oxide film) 26.
【００３５】本実施形態に係るＭＯＳ構造を有する素子
も、ＯＦＦ状態においてスーパージャンクション構造は
その最外周部分においても完全空乏化し高耐圧特性を示
すようになる。また、ＯＦＦ状態において、ｐ型層４と
ｎ型層５とのｐｎ接合から伸びる空乏層は上記スーパー
ジャンクション構造において形成される空乏層と完全に
接続され、この終端部分における耐圧を十分に確保する
ことが可能である。本実施形態では、終端構造としてリ
サーフ層（ｐ型層４）を示したが、図４、図５に示した
ガードリング層（ｐ型層１２）を用いても高耐圧を得る
ことができた。また、終端構造がリサーフ層であって
も、ガードリング層であっても、オン抵抗は非常に低か
った。In the element having the MOS structure according to the present embodiment, the super junction structure in the OFF state is also completely depleted even in the outermost peripheral portion, and exhibits a high breakdown voltage characteristic. In the OFF state, the depletion layer extending from the pn junction between the p-type layer 4 and the n-type layer 5 is completely connected to the depletion layer formed in the super junction structure, and ensures a sufficient breakdown voltage at the terminal portion. It is possible. In this embodiment, the RESURF layer (p-type layer 4) is shown as the termination structure. However, a high breakdown voltage can be obtained even by using the guard ring layer (p-type layer 12) shown in FIGS. . Also, whether the termination structure was a RESURF layer or a guard ring layer, the ON resistance was very low.
【００３６】なお、本発明は上記実施形態に限定される
ことはない。例えば、縦型の高耐圧半導体素子に限ら
ず、横型の高耐圧半導体素子等の様々な型の高耐圧半導
体素子に対して本発明を適用することも可能である。ま
た、スーパージャンクション構造におけるｐ型層１とｎ
型層２とを入れ換えて配置しても良く、この場合にもＯ
ＦＦ状態においてスーパージャンクション構造はその最
外周部分においても完全空乏化し高耐圧特性を示すよう
になる。その他、本発明の趣旨を逸脱しない範囲で種々
変形して実施することが可能である。The present invention is not limited to the above embodiment. For example, the present invention can be applied to various types of high-breakdown-voltage semiconductor elements such as horizontal high-breakdown-voltage semiconductor elements as well as vertical high-breakdown-voltage semiconductor elements. Also, the p-type layer 1 and n in the super junction structure
The mold layer 2 may be replaced and arranged.
In the FF state, the super junction structure is completely depleted even in the outermost peripheral portion, and exhibits a high breakdown voltage characteristic. In addition, various modifications can be made without departing from the spirit of the present invention.
【００３７】[0037]
【発明の効果】本発明により、スーパージャンクション
構造を有する半導体素子の高耐圧化を実現することが可
能である。According to the present invention, it is possible to realize a high breakdown voltage of a semiconductor element having a super junction structure.
【図１】 本発明の第１の実施形態に係るスーパージャ
ンクション構造を有する縦型ダイオードの構造を示す上
面図。FIG. 1 is a top view showing a structure of a vertical diode having a super junction structure according to a first embodiment of the present invention.
【図２】 図１の破線ＡＡ´に沿った面における断面
図。FIG. 2 is a sectional view of a plane along a broken line AA ′ in FIG. 1;
【図３】 図１に示す縦型ダイオードの漏れ電流特性を
示す特性図。FIG. 3 is a characteristic diagram showing leakage current characteristics of the vertical diode shown in FIG.
【図４】 本発明の第２の実施形態に係るスーパージャ
ンクション構造を有する縦型ダイオードの構造を示す上
面図。FIG. 4 is a top view showing the structure of a vertical diode having a super junction structure according to a second embodiment of the present invention.
【図５】 図４の破線ＢＢ´に沿った面における断面
図。FIG. 5 is a sectional view of a plane along a broken line BB ′ in FIG. 4;
【図６】 本発明の第３の実施形態に係るスーパージャ
ンクション構造を有する縦型のプレーナ型ＭＯＳ構造素
子を示す断面斜視図。FIG. 6 is a sectional perspective view showing a vertical planar MOS structure element having a super junction structure according to a third embodiment of the present invention.
【図７】 本発明の第４の実施形態に係るスーパージャ
ンクション構造を有する縦型のトレンチ型ＭＯＳ構造素
子を示す断面斜視図。FIG. 7 is a sectional perspective view showing a vertical trench type MOS structure element having a super junction structure according to a fourth embodiment of the present invention.
１…ストライプ状のｐ型層 ２…ストライプ状のｎ型層 ３…高濃度のｐ型層 ４…低濃度のｐ型層（リサーフ層） ５…低濃度のｎ型層 ６…高濃度のｎ型ストッパー層 ７…絶縁膜 ８…アノード電極 ９…ストッパー電極 １０…高濃度のｎ型層 １１…カソード電極 １２…高濃度のｐ型層（ガードリング層） １３、２３…ｐ型ベース層 １４、２４…ｎ型ソース層 １５…ｎ型ドレイン層 １６、２６…ゲート絶縁膜 １７、２７…ゲート電極 ２８…トレンチ DESCRIPTION OF SYMBOLS 1 ... Striped p-type layer 2 ... Striped n-type layer 3 ... High-concentration p-type layer 4 ... Low-concentration p-type layer (Resurf layer) 5 ... Low-concentration n-type layer 6 ... High-concentration n Mold stopper layer 7 insulating film 8 anode electrode 9 stopper electrode 10 high-concentration n-type layer 11 cathode electrode 12 high-concentration p-type layer (guard ring layer) 13, 23 p-type base layer 14, 24 n-type source layer 15 n-type drain layer 16, 26 gate insulating film 17, 27 gate electrode 28 trench
Claims (11)
型半導体領域に接して形成された第１導電型半導体層
と、前記第１導電型半導体領域及び前記第１導電型半導
体層に接して形成された第２導電型半導体層と、前記第
１導電型半導体層及び前記第２導電型半導体層に接して
形成された第２導電型半導体領域とを備え、前記第１導
電型半導体層及び前記第２導電型半導体層は交互に繰り
返して配置されており、その最外部の第１導電型半導体
層又は前記第２導電型半導体層の層厚み方向のキャリア
濃度の積分値が、その内部に配置された前記第１導電型
半導体層及び前記第２導電型半導体層の層厚み方向のキ
ャリア濃度の積分値の概略半分であることを特徴とする
高耐圧半導体素子。A first conductive type semiconductor region; a first conductive type semiconductor layer formed in contact with the first conductive type semiconductor region; and a first conductive type semiconductor region and the first conductive type semiconductor layer. A second conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor layer, and a second conductivity type semiconductor region formed in contact with the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; The layer and the second conductivity type semiconductor layer are alternately and repeatedly arranged, and the outermost first conductivity type semiconductor layer or the integral value of the carrier concentration in the layer thickness direction of the second conductivity type semiconductor layer is the same. A high withstand voltage semiconductor element, wherein the integrated value is approximately half of an integral value of a carrier concentration in a thickness direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer disposed inside.
導体領域と、これらの第１導電型半導体領域と第２導電
型半導体領域との間に挟まれて形成され、交互に繰り返
して配置された第１導電型半導体層及び第２導電型半導
体層とを備え、この第１導電型半導体層及び第２導電型
半導体層の繰り返し配置方向は、前記第１導電型半導体
領域と前記第２導電型半導体領域とを結ぶ方向に対して
概略垂直であるとともに、前記第１導電型半導体層はオ
ン状態でドリフト電流を流すとともにオフ状態で空乏化
し、前記第２導電型半導体層はオフ状態で空乏化し、か
つ最外部の第１導電型半導体層又は前記第２導電型半導
体層の層厚み方向のキャリア濃度の積分値が、その内部
に配置された前記第１導電型半導体層及び前記第２導電
型半導体層の層厚み方向のキャリア濃度の積分値の概略
半分であることを特徴とする高耐圧半導体素子。2. A first conductivity type semiconductor region, a second conductivity type semiconductor region, and formed between the first conductivity type semiconductor region and the second conductivity type semiconductor region, and are alternately repeated. A first conductivity type semiconductor layer and a second conductivity type semiconductor layer, wherein the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are repeatedly arranged in the first conductivity type semiconductor region and the second conductivity type semiconductor layer. The first conductivity type semiconductor layer is substantially perpendicular to a direction connecting the two conductivity type semiconductor regions, and the first conductivity type semiconductor layer flows a drift current in an on state and is depleted in an off state, and the second conductivity type semiconductor layer is in an off state. And the integrated value of the carrier concentration in the thickness direction of the outermost first conductivity type semiconductor layer or the second conductivity type semiconductor layer is the first conductivity type semiconductor layer and the second conductivity type semiconductor layer disposed therein. Layer thickness of two conductivity type semiconductor layer A high withstand voltage semiconductor element characterized by being approximately half the integral value of the carrier concentration in the direction.
濃度第１導電型半導体領域に接して形成された第１導電
型半導体層と、前記高濃度第１導電型半導体領域及び前
記第１導電型半導体層に接して形成された第２導電型半
導体層と、前記第１導電型半導体層及び前記第２導電型
半導体層に接して形成された高濃度第２導電型半導体領
域と、前記第１導電型半導体層及び前記第２導電型半導
体層を取り囲んで形成された低濃度第１導電型半導体領
域と、この低濃度第１導電型半導体領域及び前記高濃度
第２導電型半導体領域に接して形成され、前記高濃度第
２導電型半導体領域より低濃度の低濃度第２導電型半導
体領域とを備え、前記第１導電型半導体層及び前記第２
導電型半導体層は交互に繰り返して配置されており、そ
の最外部の第１導電型半導体層又は前記第２導電型半導
体層の層厚み方向のキャリア濃度の積分値が、その内部
に配置された前記第１導電型半導体層及び前記第２導電
型半導体層の層厚み方向のキャリア濃度の積分値の概略
半分であることを特徴とする高耐圧半導体素子。3. A high-concentration first-conductivity-type semiconductor region, a first-conductivity-type semiconductor layer formed in contact with the high-concentration first-conductivity-type semiconductor region, A second conductivity type semiconductor layer formed in contact with the one conductivity type semiconductor layer, a high concentration second conductivity type semiconductor region formed in contact with the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, A low-concentration first-conductivity-type semiconductor region formed surrounding the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer; a low-concentration first-conductivity-type semiconductor region and the high-concentration second-conductivity-type semiconductor region; And a low-concentration second-conductivity-type semiconductor region having a lower concentration than the high-concentration second-conductivity-type semiconductor region.
The conductivity type semiconductor layers are alternately and repeatedly arranged, and the integral value of the carrier concentration in the layer thickness direction of the outermost first conductivity type semiconductor layer or the second conductivity type semiconductor layer is arranged therein. A high breakdown voltage semiconductor device, wherein the integrated value is approximately half of an integrated value of a carrier concentration in a thickness direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer.
第２導電型半導体領域と、これらの高濃度第１導電型半
導体領域と高濃度第２導電型半導体領域との間に挟まれ
て形成され、交互に繰り返して配置された第１導電型半
導体層及び第２導電型半導体層と、これらの第１導電型
半導体層及び第２導電型半導体層を取り囲んで形成され
た低濃度第１導電型半導体領域と、この低濃度第１導電
型半導体領域及び前記高濃度第２導電型半導体領域に接
して形成され、前記高濃度第２導電型半導体領域より低
濃度の低濃度第２導電型半導体領域とを備え、前記第１
導電型半導体層及び第２導電型半導体層の繰り返し配置
方向は、前記高濃度第１導電型半導体領域と前記高濃度
第２導電型半導体領域とを結ぶ方向に対して概略垂直で
あるとともに、前記第１導電型半導体層はオン状態でド
リフト電流を流すとともにオフ状態で空乏化し、前記第
２導電型半導体層はオフ状態で空乏化し、かつ最外部の
第１導電型半導体層又は前記第２導電型半導体層の層厚
み方向のキャリア濃度の積分値が、その内部に配置され
た前記第１導電型半導体層及び前記第２導電型半導体層
の層厚み方向のキャリア濃度の積分値の概略半分である
ことを特徴とする高耐圧半導体素子。4. A high-concentration first-conductivity-type semiconductor region, a high-concentration second-conductivity-type semiconductor region, and sandwiched between the high-concentration first-conductivity-type semiconductor region and the high-concentration second-conductivity-type semiconductor region. A first conductivity type semiconductor layer and a second conductivity type semiconductor layer, which are alternately and repeatedly arranged, and a low-concentration semiconductor layer formed by surrounding the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. A low-concentration second conductivity type semiconductor region formed in contact with the one-conductivity-type semiconductor region and the low-concentration first-conductivity-type semiconductor region and the high-concentration second-conductivity-type semiconductor region; The first semiconductor region.
The repeated arrangement direction of the conductive semiconductor layer and the second conductive semiconductor layer is substantially perpendicular to a direction connecting the high-concentration first conductive semiconductor region and the high-concentration second conductive semiconductor region, and The first conductivity type semiconductor layer causes a drift current to flow in the on state and is depleted in the off state, the second conductivity type semiconductor layer is depleted in the off state, and an outermost first conductivity type semiconductor layer or the second conductivity type. The integral value of the carrier concentration in the layer thickness direction of the type semiconductor layer is approximately half of the integral value of the carrier concentration in the layer thickness direction of the first conductive type semiconductor layer and the second conductive type semiconductor layer disposed therein. A high-breakdown-voltage semiconductor element characterized by the following.
濃度第１導電型半導体領域に接して形成された第１導電
型半導体層と、前記高濃度第１導電型半導体領域及び前
記第１導電型半導体層に接して形成された第２導電型半
導体層と、前記第１導電型半導体層及び前記第２導電型
半導体層に接して形成された高濃度第２導電型半導体領
域と、前記第１導電型半導体層及び前記第２導電型半導
体層を取り囲んで形成された低濃度第１導電型半導体領
域と、この低濃度第１導電型半導体領域に接して形成さ
れ、前記高濃度第２導電型半導体領域を取り囲むように
当該領域から離間して設けられたリング状の第２導電型
半導体領域層とを備え、前記第１導電型半導体層及び前
記第２導電型半導体層は交互に繰り返して配置されてお
り、その最外部の第１導電型半導体層又は前記第２導電
型半導体層の層厚み方向のキャリア濃度の積分値が、そ
の内部に配置された前記第１導電型半導体層及び前記第
２導電型半導体層の層厚み方向のキャリア濃度の積分値
の概略半分であることを特徴とする高耐圧半導体素子。5. A high-concentration first-conductivity-type semiconductor region, a first-conductivity-type semiconductor layer formed in contact with the high-concentration first-conductivity-type semiconductor region; A second conductivity type semiconductor layer formed in contact with the one conductivity type semiconductor layer, a high concentration second conductivity type semiconductor region formed in contact with the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, A low-concentration first-conductivity-type semiconductor region formed surrounding the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer; and a low-concentration first-conductivity-type semiconductor region formed in contact with the low-concentration first-conductivity-type semiconductor region. A ring-shaped second conductivity type semiconductor region layer provided separately from the two conductivity type semiconductor regions so as to surround the two conductivity type semiconductor regions, wherein the first conductivity type semiconductor layers and the second conductivity type semiconductor layers are alternately arranged. It is arranged repeatedly and its outermost The integral value of the carrier concentration in the layer thickness direction of the one conductivity type semiconductor layer or the second conductivity type semiconductor layer is determined by the thickness direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer disposed therein. A high withstand voltage semiconductor device, wherein the integrated value is approximately half of the integrated value of the carrier concentration.
第２導電型半導体領域と、これらの高濃度第１導電型半
導体電極層と高濃度第２導電型半導体電極層との間に挟
まれて形成され、交互に繰り返して配置された第１導電
型半導体層及び第２導電型半導体層と、これらの第１導
電型半導体層及び第２導電型を取り囲んで形成された低
濃度第１導電型半導体領域と、この低濃度第１導電型半
導体領域に接して形成され、前記高濃度第２導電型半導
体領域を取り囲むように当該領域から離間して設けられ
たリング状の第２導電型半導体領域層とを備え、前記第
１導電型半導体層及び第２導電型半導体層の繰り返し配
置方向は、前記高濃度第１導電型半導体領域と前記高濃
度第２導電型半導体領域とを結ぶ方向に対して概略垂直
であるとともに、前記第１導電型半導体層はオン状態で
ドリフト電流を流すとともにオフ状態で空乏化し、前記
第２導電型半導体層はオフ状態で空乏化し、かつ最外部
の第１導電型半導体層又は前記第２導電型半導体層の層
厚み方向のキャリア濃度の積分値が、その内部に配置さ
れた前記第１導電型半導体層及び前記第２導電型半導体
層の層厚み方向のキャリア濃度の積分値の概略半分であ
ることを特徴とする高耐圧半導体素子。6. A high-concentration first-conductivity-type semiconductor region, a high-concentration second-conductivity-type semiconductor region, and a portion between the high-concentration first-conductivity-type semiconductor electrode layer and the high-concentration second-conductivity-type semiconductor electrode layer. A first conductivity type semiconductor layer and a second conductivity type semiconductor layer formed so as to be sandwiched and alternately repeated, and a low-concentration semiconductor layer formed surrounding the first conductivity type semiconductor layer and the second conductivity type; A ring-shaped second conductive layer formed in contact with the one-conductivity-type semiconductor region and the low-concentration first-conductivity-type semiconductor region and spaced apart from the high-concentration second-conductivity-type semiconductor region; A first semiconductor layer and a second conductivity type semiconductor layer, wherein the repeated arrangement direction of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer connects the high concentration first conductivity type semiconductor region and the high concentration second conductivity type semiconductor region. Approximately perpendicular to the direction and forward The first conductivity type semiconductor layer flows a drift current in an on state and is depleted in an off state, the second conductivity type semiconductor layer is depleted in an off state, and the outermost first conductivity type semiconductor layer or the second The integrated value of the carrier concentration in the layer thickness direction of the conductive type semiconductor layer is approximately half the integrated value of the carrier concentration in the layer thickness direction of the first conductive type semiconductor layer and the second conductive type semiconductor layer disposed therein. A high breakdown voltage semiconductor device characterized by the following.
電型半導体層は、お互いに平行なストライプ状の層であ
ることを特徴とする請求項１乃至６記載の高耐圧半導体
素子。7. The high breakdown voltage semiconductor device according to claim 1, wherein the first conductivity type semiconductor layer and the second conductivity type semiconductor layer are striped layers parallel to each other.
電型半導体層は、奇数個存在することを特徴とする請求
項１乃至７記載の高耐圧半導体素子。8. The high breakdown voltage semiconductor device according to claim 1, wherein an odd number of said first conductive type semiconductor layers and said second conductive type semiconductor layers are present.
状態で空乏化し、その空乏領域は前記第１導電型半導体
層及び前記第２導電型半導体層において空乏化により生
ずる空乏領域と接することを特徴とする請求項３、４、
７、又は８記載の高耐圧半導体素子。9. The low-concentration second conductivity type semiconductor region is depleted in an off state, and the depletion region is in contact with a depletion region generated by depletion in the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. Claims 3 and 4, characterized in that:
7. The high withstand voltage semiconductor device according to 7 or 8.
層に接する低濃度第１導電型半導体領域はオフ状態で空
乏化し、その空乏領域は前記第１導電型半導体層及び前
記第２導電型半導体層において空乏化により生ずる空乏
領域と接することを特徴とする請求項５乃至８記載の高
耐圧半導体素子。10. The low-concentration first-conductivity-type semiconductor region in contact with the ring-shaped second-conductivity-type semiconductor region layer is depleted in an off state, and the depletion region is the first-conductivity-type semiconductor layer and the second-conductivity-type. 9. The high breakdown voltage semiconductor device according to claim 5, wherein the semiconductor layer is in contact with a depletion region generated by depletion in the semiconductor layer.
有するものであることを特徴とする請求項１乃至９記載
の高耐圧半導体素子。11. The high breakdown voltage semiconductor device according to claim 1, wherein the high breakdown voltage semiconductor device has a vertical structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07719899A JP3751463B2 (en) | 1999-03-23 | 1999-03-23 | High voltage semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07719899A JP3751463B2 (en) | 1999-03-23 | 1999-03-23 | High voltage semiconductor element |
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| Publication Number | Publication Date |
|---|---|
| JP2000277726A true JP2000277726A (en) | 2000-10-06 |
| JP3751463B2 JP3751463B2 (en) | 2006-03-01 |
Family
ID=13627137
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07719899A Expired - Fee Related JP3751463B2 (en) | 1999-03-23 | 1999-03-23 | High voltage semiconductor element |
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| Country | Link |
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| JP (1) | JP3751463B2 (en) |
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