JP2000270170A - Image signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable grain amplifier that assures wide gain variable width against a high speed image signal and can realize a gain setting curve inversely proportional to the setting value which can be set at an optimum value without the need for unnecessary arithmetic operations from read image data. SOLUTION: An R string circuit 3 employs an analog OR circuit consisting of analog switches 4 (S0-S511) and source followers 5 (SF0-SF15) as a selection means 2 of an optional voltage division position of a resistance string 1 being a variable gain major components so as to reduce the ON-resistance of the analog switches 4 and a parasitic capacitance to the analog switches. Thus, the frequency band of signal transmission by the analog switches 4 is extended, and the drive capacity of a load is improved by using the source followers 5 so as to suppress deterioration in the frequency characteristic due to the reduction in the input impedance of an amplifier. Then a variable gain amplifier with a inversely proportional characteristic to a broad band gain variable by a very small step and set data can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD linear image sensor which is a photoelectric conversion element used for a reading section of a digital copying machine or a facsimile apparatus or an image reading apparatus such as an image scanner. The present invention relates to an image signal processing circuit that converts only an image signal component corresponding to an input light amount from an output signal into digital data.

[0002]

2. Description of the Related Art Generally, in this type of image reading apparatus, a CCD linear image sensor is frequently used as a photoelectric conversion element for reading an image. In this case, some kind of amplifier is provided in a signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of the CCD linear image sensor into digital data. More specifically, the output signal from the CCD linear image sensor is sampled and held, and the peak value is detected and A / D converted.
The dynamic range of the A / D converter is widened by changing the gain of the variable gain amplifier so that the peak value becomes the maximum output level and inputting the gain to the A / D converter. That is, in the signal processing path between the peak hold circuit and the A / D converter, a variable gain amplifier whose gain is variable by digital data such as an A / D converted peak value is interposed.

As a first conventional example, as shown in FIG. 26, a variable gain amplifier 103 in which a signal attenuator 102 having an R-2R ladder resistor 101 is interposed in front of a fixed gain amplifier 100 is used. is there. Where R
The −2R ladder resistor 101 connects the plurality of resistors R and the resistors 2R in a ladder shape as shown in FIG.
The damping rate can be varied by switching and controlling the number of stages of combination of the resistor R and the resistor 2R based on. Now, assuming that the gain of the fixed gain amplifier 100 is A and the number of bits of the setting data DD is L, the variable gain amplifier 103
Is G = A * (DD + 1) / 2 ^L (times).

[0004] As a second conventional example, as shown in FIG. 28, a variable gain amplifier 113 in which a signal attenuator 112 including an R-2R ladder resistor 111 is interposed in a feedback loop of an operational amplifier 110 is used. is there. Where R
The −2R ladder resistor 111 is the same as that shown in FIG. 27 (the same applies to the R-2R ladder resistor described later). In this case, the gain G of the variable gain amplifier 113 is G = 2 ^L / (DD + 1) (times). In the case of the second conventional example, since the gain setting curve is inversely proportional to the setting data DD (1 / D curve), the peak value of the signal after A / D conversion is used as the setting data. There is an advantage that adjustment and setting can be performed.

As a third conventional example, as shown in FIG. 29, a gain attenuator 12
There is a device using a variable gain amplifier 122 formed by connecting the variable gain amplifiers 1 and 2. Here, the gain attenuator 121 is, for example, as shown in FIG.
As shown by 0, the π-type (or T-type) attenuator 123 is connected in multiple stages, and the attenuation factor of the gain (dB) can be varied by switching the signal passing attenuator according to the setting data DD. Now, the minimum attenuation rate of the attenuator 123 (d
Assuming that B) is a, the gain G of the variable gain amplifier 122 is as follows: G = A− (a * DD) (dB)

As a fourth conventional example, as shown in FIG. 31, a gain attenuator 13 is provided in a feedback loop of an operational amplifier 130.
There is a device using a variable gain amplifier 132 formed by connecting 1 to each other. Here, the gain attenuator 131 is the same as that shown in FIG. 30. The π-type (or T-type) attenuator is connected in multiple stages, and the signal-passage attenuator is switched according to the setting data DD. (DB) can be varied. In this case, the gain G of the variable gain amplifier 132 is as follows: G = a * DD (dB)

As a fifth conventional example, although not particularly shown,
There is a combination of a voltage-controlled variable gain amplifier and a digital / analog converter.

As a sixth conventional example, although not particularly shown,
For example, as disclosed in Japanese Patent Application Laid-Open No. 10-243188, a multi-bit R-2 digitally adjustable attenuation factor is provided.
An attenuator having an R ladder resistor and a maximum attenuation rate defining resistor connected in parallel to the R-2R ladder resistor, to which an output signal from the CCD linear image sensor is input;
There is a type in which an R-2R ladder resistor is used as a main gain switching element by providing a variable gain amplifier including a fixed gain amplifier connected to a stage subsequent to the attenuator. Similarly,
There is also a variable gain amplifier using a resistor string as a main gain switching element.

[0009]

However, according to the first and second conventional examples, the variable width of the gain is too large and the variable step is too coarse. For example, in the variable gain amplifier 103 shown in FIG. 26, when the setting data DD based on the peak value or the like is the most common 8-bit, the variable width of the gain is 1/256 to 256/256 (= 1). , The step width is only about 1/256, and the adjustment and setting of the gain are insufficient for realizing high-resolution reading, high-speed reading, and the like required for this type of image reading apparatus in recent years. I will.

In the third and fourth conventional examples, the gain variable width and the variable step can be freely set. However, if the small gain variable width and the small variable step are set, the attenuators 121 and 131 are not used. Are too large in the case of a monolithic IC configuration, the resistance itself becomes extremely large, or it is difficult to secure required accuracy, and it is difficult to realize the configuration. Further, since the gain setting curve is proportional to the setting data DD in dB (dB curve), fine gain setting can be performed with the minimum setting data length, but only one gain setting curve can be realized for each configuration. It will be decided.

In the case of the fifth conventional example, although the gain variable width, variable step, and gain setting curve can be set relatively freely, it is difficult in principle to achieve high precision.

In the case of the sixth conventional example, a highly accurate R-2
In order to realize the R ladder resistor, a high-precision IC process is required, and the ON resistance of the analog switch for selecting the R-2R ladder resistor must be reduced (the element size must be increased). Therefore, it is difficult or expensive to realize a highly accurate variable gain amplifier. In the case of using a resistor string, many analog switches are configured, and the analog switches are turned on.
It is difficult to secure a wide frequency band due to resistance and parasitic capacitance. Although monotonicity can be ensured, the absolute accuracy depends on the relative accuracy between the resistance value of the resistor string and the resistance value of the resistance switching circuit, so that it is also difficult to achieve high accuracy.

Accordingly, the present invention can secure a wide variable gain range for a high-speed image signal,
A gain setting curve (that is, 1 / D curve) that is inversely proportional to a set value at which an optimum gain can be set without performing unnecessary calculation from the read image data can be realized, and fine gain fine adjustment is possible. It is an object of the present invention to provide an image signal processing circuit having a variable gain amplifier that can be easily made into a monolithic IC.

[0014]

According to the first aspect of the present invention,
Converts only image signal components corresponding to the input light amount from the output signal of the CCD linear image sensor into digital data.
The CD analog signal processing circuit has a small step variable gain amplifier comprising a digital setting type signal attenuator using a resistor string and a fixed gain amplifier, and comprises an analog OR circuit comprising a one-stage or multi-stage analog switch and a source follower. And selecting means for selecting a divided voltage signal at an arbitrary point of the resistor string.

According to a second aspect of the present invention, in a CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, a digital setting type signal attenuator using a resistor string is provided. A variable gain amplifier using an operational amplifier that uses a feedback as a feedback signal, comprising a one-stage or multi-stage analog switch and an analog OR circuit with a source follower,
There is provided selection means for selecting a divided voltage signal at an arbitrary point in the resistor string.

According to a third aspect of the present invention, there is provided a CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data. A small step variable gain amplifier comprising a setting type signal attenuator and an operational amplifier using a digital setting type signal attenuator with a second resistor string for feedback; an analog switch comprising a single-stage or multi-stage analog switch and a source follower; It comprises an OR circuit, and has a selection means for selecting a divided voltage signal at an arbitrary point of each of the resistor strings.

Therefore, according to the first to third aspects of the present invention, an analog OR circuit including an analog switch and a source follower is used as means for selecting an arbitrary voltage dividing point of a resistor string which is a main element of a variable gain. Therefore, the on-resistance of the analog switch and the parasitic capacitance attached to the analog switch can be reduced, the frequency band of signal transmission by the analog switch is extended, and the drive capability of the load is increased because the source follower is used, so the input impedance of the amplifier Thus, it is possible to suppress the deterioration of the frequency characteristic due to the decrease of the gain, and to realize a variable gain amplifier having a variable gain of a fine step in a wide band and a characteristic inversely proportional to the setting data.

According to a fourth aspect of the present invention, there is provided a CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, wherein a digital setting type signal using a resistor string is provided. It has a small step variable gain amplifier with an attenuator and a fixed gain amplifier, has an output for each block, and each block is composed of an analog OR circuit with a one-stage or multi-stage analog switch and a source follower,
When the fixed gain amplifier has an input corresponding to an output of each block of the resistor string and an output of a certain block is valid The corresponding input is enabled.

According to a fifth aspect of the present invention, there is provided a CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, wherein a digital setting type signal attenuator using a resistor string is provided. A variable gain amplifier is provided by an operational amplifier using feedback for each block, each block has an output, and each block is configured by an analog OR circuit including a single-stage or multi-stage analog switch and a source follower. Selecting means for selecting a divided voltage signal at a point, wherein the operational amplifier has an inverting input corresponding to the output of each block of the resistor string, and when the output of a certain block is valid, the inverting input corresponding thereto is Enabled.

According to a sixth aspect of the present invention, there is provided a CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, wherein a digital signal using a first resistor string is used. A small step variable gain amplifier comprising a setting type signal attenuator and an operational amplifier using a digital setting type signal attenuator with a second resistor string for feedback has an output for each block, and each block has one stage or Analog OR with multi-stage analog switch and source follower
A selection circuit for selecting a divided voltage signal at an arbitrary point of each of the resistor strings, wherein the operational amplifier has an inverting / non-inverting input corresponding to an output of each block of the resistor string, and When the output of a block is valid, the corresponding inverted / non-inverted input is now valid.

Therefore, according to the present invention, an analog switch divided into blocks is used to select an arbitrary voltage dividing point of the resistor string, which is a main element of variable gain, and an output is output for each block. The on-resistance of the analog switch and the parasitic capacitance attached to the analog switch can be reduced, and the frequency band of signal transmission by the analog switch is extended. A variable gain amplifier having the same can be realized.

According to a seventh aspect of the present invention, in the image signal processing circuit according to the first or fourth aspect, feedback to a drive amplifier at a stage prior to driving the resistor string is performed by a signal at a corresponding voltage dividing point of the resistor string. Is performed through an analog switch group equivalent to an analog switch group that supplies a signal to the fixed gain amplifier.

Therefore, since the gain of the drive amplifier in the preceding stage for driving the resistor string is determined through an analog switch for selecting a voltage dividing point or a source follower similar to the output of the attenuation signal of the resistor string, the feedback path of the drive amplifier is determined. It has the same frequency characteristics as the attenuated signal output, which can be corrected by the drive amplifier. Therefore, the frequency characteristics of the attenuated signal output are also corrected, and the band can be widened. In addition, since the gain of the drive amplifier is determined using the resistor string that attenuates the signal, an error in the attenuation factor due to the relative accuracy of the constituent resistors of the resistor string can be corrected to some extent. I can do it.

According to an eighth aspect of the present invention, in the image signal processing circuit according to the second or fifth aspect, a signal passing through the analog switch and the source follower from an arbitrary voltage dividing point of the resistor string is supplied to the operational amplifier. It is used as a signal for phase compensation, and the voltage dividing point of the resistor string selected for each gain range of the variable gain amplifier is switched.

Therefore, a variable gain amplifier having a resistor string on the feedback path of the operational amplifier and feeding back an arbitrary voltage dividing point of the resistor string, the arbitrary voltage dividing point of the resistor string on the feedback path is determined by the analog switch and the source follower. Since the signal is used as a phase compensation signal through a voltage buffer, if the gain decreases due to variations in the relative accuracy of the constituent resistors, the amplitude of the phase compensation signal increases, so deep phase compensation is applied, and conversely, the gain increases. In this case, the phase compensation becomes shallow, and the variation in the overall frequency characteristics is reduced. Further, since the amplitude of the phase compensation signal can be changed by the gain, optimal phase compensation can be performed at each gain.

According to a ninth aspect of the present invention, in the image signal processing circuit according to the third or sixth aspect, feedback to a drive amplifier in a preceding stage for driving the first resistor string is performed by the first signal amplifier.
The signal at the corresponding voltage dividing point of the resistor string is passed through an analog switch group equivalent to an analog switch group that supplies a signal to the fixed gain amplifier, and the analog switch and the analog switch are connected from an arbitrary voltage dividing point of the second resistor string. A signal passed through the source follower is used as a signal for phase compensation of the operational amplifier, and a voltage dividing point of the second resistor string selected for each gain range of the variable gain amplifier is switched.

Therefore, the gain of the drive amplifier in the preceding stage for driving the first resistor string is determined through an analog switch for selecting a voltage dividing point and a source follower similar to the output of the attenuation signal of the resistor string. The feedback path has the same frequency characteristics as the attenuation signal output, and this can be corrected by the drive amplifier. Therefore, the frequency characteristics of the attenuation signal output are also corrected, and the band can be widened. Further, since the gain of the drive amplifier is determined by using the first resistor string for attenuating the signal, the error of the attenuation factor due to the relative accuracy of the constituent resistors of the first resistor string can be corrected to some extent, and as a whole, Of the gain can be improved. Further, since the phase compensation signal is output from the second resistor string in the feedback path of the operational amplifier, the variation in the overall frequency characteristics is reduced even when the gain varies. Furthermore, since the amplitude of the phase compensation signal can be changed by the gain, optimal phase compensation can be performed at each gain.

[0028]

FIG. 1 shows a first embodiment of the present invention.
A description will be given based on FIG. In this embodiment, an R string circuit 3 is provided by adding a common selection means 2 to the resistor string 1 according to the first to third aspects of the present invention.
1 shows an example of the configuration.

The resistor string 1 in the R string circuit 3 is composed of, for example, a series circuit of 512 (9 bits) resistors having a resistance value r indicated by R0 to R511. The selecting means 2 for selecting a voltage division signal from each voltage division point of the resistor string 1 includes, for example, 512 analog switches 4 (S0 to S51) connected to each voltage division point.
1) and the analog switch 4 having a one-stage configuration and S0 to S3
1, S32 to S61,..., S480 to S511,
It is configured as an analog OR circuit in combination with source followers 5 (SF0 to SF15) having a 16-block configuration connected to one block of 32 blocks each. ON / OFF of the analog switches 4 (S0 to S511) and the source followers 5 (SF0 to SF15) is controlled by the decoder 6 based on the gain setting data DD1.
Each source follower 5 (SF0 to SF15) is, for example,
As shown in FIG. 2, two FET transistors M1 and M
2, the control terminal CONT is connected to the gate of the FET transistor M2 whose drain is connected to the gate of the FET transistor M1 as the main transistor. The gate of the FET transistor M1 serves as an input terminal, is connected to the analog switch, and the source terminal serves as an output terminal.

Here, the relationship between the gain setting data DD1 and the on / off state of each analog switch 4 (S0 to S511) is shown in Table 1. The gain setting data DD1 and the on / off state of each source follower 5 (SF0 to SF15) are shown. Table 2 shows the relationship with the off (active / non-active) state.

[0031]

[Table 1]

[0032]

[Table 2]

In this configuration, in FIG. 1, one of the analog switches 4 (S0 to S511) is turned on by the decoder 6 based on the gain setting data DD1, and at the same time, each of the source followers 5 (SF0 to SF0) is turned on. SF1
One source follower 5 to which the analog switch 4 turned on in 5) is connected becomes active. When the source follower 5 becomes active, the FET transistor M2 is turned off (CONT: "L") in FIG. 2 showing a detailed configuration example of the source follower 5, and the input signal IN is connected to the gate of the FET transistor M1. When the source follower 5 is inactive, the FET transistor M2 is ON (CONT: "H"), and
Since the analog switches 4 connected to the source follower 5 are all off, the gate of the FET transistor M1 is connected to GND, the common bias current Ibias of the source follower 5 flows only to the active source follower 5, and the output terminal VO A divided voltage signal at the selected voltage dividing point of the resistor string 1 is output with an offset corresponding to the gate-source voltage Vgs of the source follower 5.

Generally, both ends of a resistor string 1 composed of 2 ^L resistors R0 to R (2 ^L -1) are set to V1 and V2, respectively, and gain setting data DD1 is decoded, and S0 to S2 are decoded.
(2 ^L -1) 2 ^L analog switches 4 and SF0 to SF
Of the source follower 5 m, when selecting each only one voltage output to the output terminal VO is ^{VO = {V1 × (2 L} -DD1) × r + V2 × DD1 × r} / (2 L × r ) the -Vgs = V1 × (1-DD1 / 2 L) + V2 × DD1 / 2 L -Vgs.

A second embodiment of the present invention will be described with reference to FIG. 1 and 2 are denoted by the same reference numerals (the same applies to each of the following embodiments). This embodiment shows another configuration example of the R string circuit 3 in which the common selection means 7 is added to the resistor string 1 according to the first to third aspects of the present invention.

The selecting means 7 of this embodiment is configured as an analog OR circuit formed by a combination of a two-stage analog switch 4 and a source follower 5 connected to the second-stage analog switch 4. That is, the first stage of the analog switch for selecting each voltage dividing point of the resistor string 1 is S
0 to S511, S0 to S15, S16 to S3
1,..., S496 to S511, 16 blocks are divided into eight blocks, and the second stage is composed of eight analog switches 4 (SA0 to SA7) provided for each block. Then, the analog switch 4 (SA0 to SA)
7) 4 source followers 5 to be a set of 2
(SF0 to SF3) are provided. These source followers 5 (SF0 to SF3) are also configured as shown in FIG. 2, for example.

Here, the relationship between the gain setting data DD1 and the on / off state of each analog switch 4 (S0 to S511) is shown in Table 3, and the gain setting data DD1 and each analog switch 4 (SA0 to SA7) and the source Table 4 shows the relationship between the follower 5 (SF0 to SF3) and the on / off state.
Shown in

[0038]

[Table 3]

[0039]

[Table 4]

In such a configuration, in FIG. 3, any one of the analog switches 4 (S 0 to S 511) and any one of the analog switches 4 (SA 0 to SA 7) are used by the decoder 6 based on the gain setting data DD 1. One of them is turned on, and among the source followers 5 (SF0 to SF3),
One source follower 5 connected to the analog switch 4 that is turned on at the same time becomes active.

Generally, both ends of a resistor string 1 composed of 2 ^L resistors of R0 to R (2 ^L -1) are set to V1 and V2, respectively, and gain setting data DD1 is decoded.
(2 ^L -1) 2 ^L analog switches 4 and SA0 to SA
When only one of each of the analog switch 4 of n and the source follower 5 of SF0 to SFm is selected, the output terminal V
The voltage output to O is the same as that described in FIG.

A third embodiment of the present invention will be described with reference to FIG. This embodiment shows another configuration example of the R string circuit 3 in which the common selection means 8 is added to the resistor string 1 according to the first to third aspects of the present invention.

The resistance strings 1 in the R string circuit 3 are, for example, 257 resistance strings R0 to R256, and two analog switches 4 adjacent to each other are simultaneously turned on in order to obtain a resolution of 9 bits. The midpoint of the voltage dividing point at both ends of one resistor is set by the resistor. However, as a condition in this case, it is necessary that the on-resistance ron of the analog switch 4 is sufficiently larger than the resistance value r of the resistance of the resistor string 1 (r≪ron). Therefore, the number of analog switches 4 for selecting each voltage dividing point of the resistor string 1 and the middle point of the voltage dividing points at both ends of the resistor is 256 (S0 to S255) +16 in a one-stage configuration.
(SA0-SA15), of which S0-S1
5, SA0, and 17 in each combination are connected to one source follower 5 (SF0 to SF15).
It shows a case in which it is composed of a set of blocks. These source followers 5 (SF0 to SF15) are also configured as shown in FIG. 2, for example.

Here, the gain setting data DD1 and each analog switch 4 (S0 to S255, SA0 to SA15)
Table 5 shows the relationship between the on / off states of the gain setting data DD1 and the source followers 5 (SF0 to SF15).
Table 6 shows the relationship with the on / off state of the.

[0045]

[Table 5]

[0046]

[Table 6]

In such a configuration, in FIG. 4, the decoder 6 selects one of the analog switches 4 (S0 to S255, SA0 to SA15) based on the gain setting data DD1.
One or two are turned on at the same time and the source follower 5
Among (SF0 to SF15), one source follower 5 to which the two analog switches 4 turned on at the same time are connected becomes active.

In general, as shown in FIG.
^(L-1) becomes 2 and ^(L-1) each at both ends of the resistor string 1 consisting of pieces of resistors V1, V2, decodes the gain setting data DD1, S0~S2 ^(L-1) of the 2 ^{(L- 1)} One of the analog switches 4 and the analog switches 4 of SA0 to SAm
, And one of the source followers 5 of SF0 to SFm is selected, the voltage output to the output terminal VO is the same as that in FIG.

Next, various modifications of the source follower 5 which can be used in these embodiments and the like are shown in FIG. First, FIG.
The example shown in (a) has the same configuration as that of FIG. 2, and an N-type M
An OS transistor is used. Here, when the control terminal CONT = “L”, the FET transistor M2 is turned off, the input terminal IN is connected to the gate of the FET transistor M1, and the source follower 5 becomes valid (active). Control terminal CONT = "H"
Then, the FET transistor M2 is turned on, and the gate of the FET transistor M1 is connected to GND.
This source follower 5 becomes invalid (non-active).

In the example shown in FIG.
As in the case of (a), the current source I1 and the P-type MOS transistor M3 are connected to the drain of the FET transistor M1.
By adding a connection between the sources, the load drive capability of the source follower 5 is enhanced.

In the example shown in FIG. 5C, a P-type MOS transistor is used as the FET transistor M1 as the main transistor. In this example, FIGS. 5A and 5B
When the control terminal CONTB = "H", the FET transistor M2 is turned off, and the input terminal IN
Is connected to the gate of the FET transistor M1, and the source follower 5 becomes effective (active). When the control terminal CONTB is "L", the FET transistor M2 is turned on, the gate of the FET transistor M1 is connected to Vcc, and the source follower 5 becomes invalid (non-active).

In the example shown in FIG. 5D as in FIG. 5B, the current source I1 and the P-type MOS transistor M3 are connected between the drain and source of the FET transistor M1. 5 (c), the load drive capability of the source follower 5 is increased.

FIGS. 5 (e) and 5 (f) respectively show FIGS.
(B) The load drive capability enhancement circuit shown in (d) is separated from the source follower 5 and is externally connected to each of the source followers 5 in the same manner as the common bias current Ibias. Since only one of the source followers 5 is active, no bias current flows through the non-active source follower 5 and the active source follower 5 is not affected by the other source follower 5. Drive capacity can be increased.

FIGS. 6 and 7 show a fourth embodiment of the present invention.
It will be described based on. This embodiment corresponds to the first aspect of the present invention. A small step variable gain amplifier 11 according to the present embodiment, which is provided at a portion to which an output signal from a CCD linear image sensor (not shown) is input, includes a fixed gain amplifier 12 and a stage preceding the fixed gain amplifier 12. And a digital setting type signal attenuator 13 connected thereto. This digital setting type signal attenuator 13 has the configuration described in the first to third embodiments and the like.
It is composed of a string circuit 3 and a resistance switching circuit 14.

More specifically, the input signal is connected to one input (V2) of the R string circuit 3, and the other input (V1) of the R string circuit 3 is connected to one input (V1) of the resistance switching circuit 14. The other input (V2) of the resistance switching circuit 14 is connected to GND. Resistance switching circuit 1
As shown in FIG. 7, reference numeral 4 denotes a configuration in which 2 ⁿ resistors R1 to R (2 ⁿ ) are selectively connected in parallel, and an arbitrary resistor Ri is selected by the setting data DD3. The output (VO) of the R string circuit 3 depends on the gain setting data DD1, and the attenuation rate is 1 (no attenuation) to Ri / (Ri + R) (R:
The attenuation rate is selected within the range of the total resistance value of the resistor string 1).

The output (VO) of the R string circuit 3 is input to a fixed gain amplifier 12 composed of an operational amplifier 15 having a gain A1, a feedback resistor R1, a signal source resistor R2, an N-type MOS transistor M1, and a current source Ibias. 1 + R1 / R
2) Multiplied and output. Here, the FET transistor M1 and the current source Ibias of the source follower on the inverting terminal side of the operational amplifier 15 are the same as the FET transistor M1 and the bias current Ibias in the source follower 5 included in the R string circuit 3, and have the same reference numerals. Indicated by. The source follower formed by the FET transistor M1 and the current source Ibias is for canceling the offset voltage Vgs of the source follower 5 in the R string circuit 3. Here, the total gain is Av = (1 + R
1 / R2) × (R × DD1 / 2 ^L + Ri) / (R + Ri)
(Times).

When the source follower 5 of the R string circuit 3 has a modified configuration as shown in FIG. 5, the FET transistor M on the inverting terminal side of the operational amplifier 15 is used.
By using the same configuration for the source follower 1 and the current source Ibias, the overall offset voltage can be reduced.

Therefore, according to the present embodiment, the analog OR circuit using the analog switch 4 and the source follower 5 as the means 2, 7, or 8 for selecting an arbitrary voltage dividing point of the resistor string 1 which is a main element of the variable gain. , The on-resistance of the analog switch 4 and the parasitic capacitance attached to the analog switch 4 can be reduced, the frequency band of signal transmission by the analog switch 4 is extended, and the driving capability of the load is increased because the source follower 5 is used. As a result, the deterioration of the frequency characteristic due to the decrease of the input impedance of the amplifier can be suppressed, and the variable gain amplifier 11 having a variable gain of a fine step in a wide band and a characteristic inversely proportional to the gain setting data DD1 can be realized. Setting data DD
If 1 is 8 bits, the attenuation rate becomes 1/512 to 1 and the step width becomes 1/512, which is half. As a result, a minute variable step can be realized with setting data having the same number of bits. Since a minute variable step is realized, fine gain adjustment is possible. Further, since the variable step is basically determined based on the voltage dividing point of the resistor string 1, there is no need to use a wide range of resistance values for the resistor string 1, and the variable gain amplifier 1 can be easily made into a monolithic IC. Can also. Further, since only one operational amplifier 12 is provided on the signal path between the input and output, the deterioration of the frequency characteristics is very small and the increase in noise due to the amplifier 2 is minimized. The configuration is suitable for processing.

A fifth embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the second aspect of the present invention. The variable gain amplifier 16 of the present embodiment includes an operational amplifier 17 and a digital setting type signal attenuator 18 interposed in a feedback path of the operational amplifier 17. This digital setting type signal attenuator 18 is configured by a series circuit of the R string circuit 3 having the configuration described in the first to third embodiments and the like and the resistance switching circuit 19 shown in FIG.

More specifically, an input signal is input to a non-inverting terminal of an operational amplifier 17 (gain A1) through a source follower formed by an N-type MOS transistor M1 and a current source Ibias. Connected to one input (V2), the other input (V1) of the resistance switching circuit 17 and one input (V
2) is connected to the other input (V) of the R string circuit 3.
1) is connected to GND. In the resistance switching circuit 19, an arbitrary resistor Rj is selected by the setting data DD5, and the output (VO) of the R string circuit 3 is set to the attenuation factor RB / (Rj with respect to the output of the operational amplifier 17 by the setting data DD4.
+ RB) (where RB is the total resistance value of the resistor string 1, Rj is the resistance value selected in the resistance switching circuit 19)
The attenuation factor is selected in the range of ∞ (infinity), and the operational amplifier 1
7 is fed back to the inverted input. Here, regarding the source follower by the N-type MOS transistor M1 and the current source Ibias, the source follower 5 included in the R string circuit 3 is also included.
These are the same as the FET transistor M1 and the bias current Ibias in the middle, and are denoted by the same reference numerals. The source follower by the N-type MOS transistor M1 and the current source Ibias is R
This is for canceling the offset voltage Vgs of the source follower 5 inside the string circuit 3. here,
Assuming that the number of bits of the setting data DD4 is o, Av = (RB + Rj) / RB × 2 ^o / DD4
(Times).

When the source follower 5 of the R string circuit 3 has a modified configuration as shown in FIG. 5, the source follower for the non-inverting terminal side of the operational amplifier 15 by the N-type MOS transistor M1 and the current source Ibias is also required. With a similar configuration, the overall offset voltage can be kept low.

Therefore, according to the present embodiment, the analog OR circuit using the analog switch 4 and the source follower 5 as the means 2, 7, or 8 for selecting an arbitrary voltage dividing point of the resistor string 1 which is a main element of the variable gain. , The on-resistance of the analog switch 4 and the parasitic capacitance attached to the analog switch 4 can be reduced, the frequency band of signal transmission by the analog switch 4 is extended, and the driving capability of the load is increased because the source follower 5 is used. As a result, the deterioration of the frequency characteristic due to the decrease in the input impedance of the amplifier can be suppressed, and the variable gain amplifier 16 having a variable gain of a fine step in a wide band and an inversely proportional characteristic to the gain setting data DD1 can be realized.

A sixth embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the third aspect of the present invention. The variable gain amplifier 21 of the present embodiment includes a fixed gain amplifier 12, a digital setting type signal attenuator 13 connected to a stage preceding the fixed gain amplifier 12, and a feedback path of an operational amplifier 17 in the fixed gain amplifier 12. And a digital setting type signal attenuator 18 interposed therebetween. The digital setting type signal attenuator 13 includes the R string circuit 3A having the configuration described in the first to third embodiments and the like, and the resistance switching circuit 14A. The digital setting type signal attenuator 18 is configured by a series circuit of the R string circuit 3B having the configuration described in the first to third embodiments and the like and the resistance switching circuit 19 shown in FIG.

More specifically, the input signal is connected to one input (V2) of R string circuit 3A, and the other input (V1) of R string circuit 3A is connected to resistance switching circuit 14A.
And the other input (V2) of the resistance switching circuit 14 is connected to GND. In the resistance switching circuit 14, an arbitrary resistance Ri is selected by the setting data DD3, and the output (VO) of the R string circuit 3A is attenuated from 1 (no attenuation) to Ri by the gain setting data DD1.
/ (Ri + RA) (where RA: R string circuit 3
The attenuation rate is selected within the range of the total resistance value of the first resistor string 1 of A, and the output (VO) of the R string circuit 3A is selected.
Is input to the non-inverting terminal of the operational amplifier 15.

The output of the operational amplifier 15 is connected to a resistance switching circuit 19
The other input (V1) of the resistance switching circuit 19 is connected to one input (V2) of the R string circuit 3B, and the other input (V1) of the R string circuit 3B is connected to the other input (V1) of the R string circuit 3B. It is connected to GND. In the resistance switching circuit 19, an arbitrary resistance Rj is selected by the setting data DD5, and the output (VO) of the R string circuit 3B is set to the attenuation rate R with respect to the output of the operational amplifier 15 by the setting data DD4.
The attenuation rate is selected in the range of B / (Rj + RB) (where RB is the total resistance value of the resistor string 1 of the R string circuit 3B, Rj is the selected resistance value of the resistance switching circuit 19) to ∞ (infinity). Is fed back to the inverting input of the operational amplifier 15. Here, the total gain is: Av = (RA × DD1 / 2 ^L + Ri) / (RA + Ri) × (R
B + Rj) / RB × 2 ^o / DD4 (times).

The digital setting type signal attenuators 13, 1
In the case where the source followers 5 of the R string circuits 3A and 3B in FIG. 8 have a modified configuration as shown in FIG. 5, the same offset configuration can be used to reduce the overall offset voltage.

Therefore, according to the present embodiment, the analog OR circuit using the analog switch 4 and the source follower 5 as the means 2, 7, or 8 for selecting an arbitrary voltage dividing point of the resistor string 1, which is the main element of the gain variable. , The on-resistance of the analog switch 4 and the parasitic capacitance attached to the analog switch 4 can be reduced, the frequency band of signal transmission by the analog switch 4 is extended, and the driving capability of the load is increased because the source follower 5 is used. As a result, the deterioration of the frequency characteristic due to the decrease of the input impedance of the amplifier can be suppressed, and the variable gain amplifier 21 having a variable gain of a fine step in a wide band and a characteristic inversely proportional to the gain setting data DD1 can be realized.

A seventh embodiment of the present invention will be described with reference to FIGS. In the present embodiment, an R string circuit 32 is provided by adding a common selecting means 31 to the resistor string 1 according to the invention of claims 4 to 6.
1 shows an example of the configuration.

In the R string circuit 32, for example,
512 (9-bit) resistance values r indicated by R0 to R511
The selection means 31 is configured to be divided into 32 blocks so as to have outputs with respect to a resistor string 33 composed of a series circuit of resistors. The selection means 31 includes an analog switch 34 (S0 to S511) and an amplifier input unit 35 (IQ0 to IQ15). In the illustrated example, the analog switch 34 for selecting each voltage dividing point of the resistor string 33 is configured by 16 sets of blocks (outputs: VO0 to VO15) each having 32 blocks in one stage. I have. Each amplifier input unit 35 (I
Q0 to IQ15) are, for example, 2 as shown in FIG.
The control terminal CONT is connected to the gate of the FET transistor M2 which is composed of two FET transistors M1 and M2 and whose drain is connected to the gate of the FET transistor M1 as the main transistor. The gate of the FET transistor M1 serves as an input terminal, is connected to the analog switch, and the source terminal serves as an output terminal.

The relationship between the gain setting data DD1 and the on / off state of each analog switch 34 (S0 to S511) is shown in Table 7, and the gain setting data DD1 and the on / off state of the amplifier input unit 35 (IQ0 to IQ15) are shown. Table 8 shows the relationship with the off (active / non-active) state.

[0071]

[Table 7]

[0072]

[Table 8]

In this configuration, in FIG. 10, one of the analog switches 34 (S0 to S511) is turned on by the decoder 36 based on the gain setting data DD1, and the output of the block (VO0 to VO15) is turned on. Are determined, and the other output is in a high impedance state. At the same time, the amplifier input unit 35 (IQ0 to IQ0)
One of the amplifier input sections 35 to which the activated block is connected becomes active.
When the amplifier input section 35 becomes active, the FET transistor M in the configuration example of the amplifier input section 35 shown in FIG.
2 is turned off (control terminal CONT: “L”), and FET
The input signal is connected to the gate of the transistor M1. When the amplifier input unit 35 is non-active, the FET transistor M2 is on (control terminal CONT: "H") and the analog switches 34 connected to the amplifier input unit 35 are all off. Is connected to GND, and only the active amplifier input unit 35 is enabled. Although not shown, the enabled amplifier input unit 35 operates as a differential pair of another transistor Tr and an amplifier input stage.

Generally, both ends of a resistor string 33 composed of 2 ^L resistors R0 to R2 ^L -1 are set to V1 and V2, respectively, and gain setting data DD1 is decoded, and S0 to S2
^When only one of the 2 ^L analog switches 34 of ^L− 1 is selected, the voltage output to the active output terminal among the block outputs VO0 to VOn is VO = (V1 × (2 ^L − DD1) × r + V2 × DD1 × r) / (2 L × r) = V1 × (1-DD1 / 2 L) + V2 × DD1 / 2 L , and the other output becomes a high impedance.

In the case of a resistor string as shown in FIGS.
The same configuration as in the case of can be obtained.

FIG. 12 shows a modification of the amplifier input unit 35. First, the example shown in FIG. 12A has the same configuration as that of FIG. 11, and an N-type MOS transistor is used as an FET transistor as a main transistor. Here, when the control terminal CONT = "L", the FET transistor M2 is turned off, the input IN is connected to the gate of the N-type MOS transistor M1, and this amplifier input unit 35
Becomes effective. When the control terminal CONT = "H", the FET transistor M2 is turned on and the N-type MOS transistor M
The gate of No. 1 is connected to GND, and the amplifier input unit 35 is disabled.

In the example shown in FIG. 12B, a P-type MOS transistor is used as an FET transistor as a main transistor. In this example, the logic is opposite to that of FIG. 12A, and when the control terminal CONTB = "H", the FE
T-transistor M2 is turned off, and input IN becomes P-type MO
The state is connected to the gate of the S transistor M1,
This amplifier input section 35 becomes effective. Control terminal CONT
When B = "L", the FET transistor M2 is turned on and P
The gate of the type MOS transistor M1 is connected to Vcc, and the amplifier input unit 35 is disabled.

Also, the offset voltage can be reduced by using the same transistor as the FET transistor M1 for the transistor forming the differential pair with the amplifier input unit 35.

An eighth embodiment of the present invention will be described with reference to FIGS. This embodiment relates to claim 4
This corresponds to the described invention. The variable gain amplifier 41 of the present embodiment, which is provided at a portion to which an output signal from a CCD linear image sensor (not shown) is input, is connected to a fixed gain amplifier 42 and a stage preceding the fixed gain amplifier 42. And a digital setting type signal attenuator 43. The digital setting type signal attenuator 43 includes the R string circuit 32 and the resistance switching circuit 44 having the configuration described in the seventh embodiment and the like.

More specifically, the input signal is connected to one input (V2) of the R string circuit 32, and the other input (V1) of the R string circuit 32 is connected to one input (V1) of the resistance switching circuit 44. The other input (V2) of the resistance switching circuit 44 is connected to GND. As shown in FIG. 14, the resistance switching circuit 44 includes 2 ⁿ resistors R1 to R (2 ⁿ
) Are connected in parallel in a selectable manner, and an arbitrary resistor Ri is selected by the setting data DD3. R
One of the outputs (VO0 to VO15) of the string circuit 32 outputs an attenuated signal according to the gain setting data DD1, and the other outputs become high impedance. The terminal which became the attenuation signal output is attenuation ratio 1 (no attenuation) to Ri / (Ri + R).
The attenuation rate is selected within the range of (R: the total resistance value of the R string 33). The output of the R string circuit 32 (VO0 to V
O15) is an operational amplifier 45 having a gain A1 and a feedback resistor R
1 and the non-inverting input (IN0 to IN15) of the fixed gain amplifier 42 by the signal source resistance R2, and (1 + R1 /
R2) is output. Here, the total gain is: Av = (1 + R1 / R2) × (R × DD1 / 2 ^L + R
i) / (R + Ri) (times).

FIG. 15 shows a configuration example of the operational amplifier 45.
In FIG. 15, M10, M20, M11, M21,
, M115, M215 constitute the amplifier input unit 35 (IQ0 to IQ15) shown in FIG.
To M115 and a FET transistor M2 constitute a differential pair. A current source IS1 is connected to a common source of the differential pair, and a current mirror of FET transistors M3 and M4 is connected to each drain. Further, an output of the current mirror is connected to a common-source amplifier constituted by an FET transistor M5, thereby forming an operational amplifier. C1 is a phase compensation capacitor.

Therefore, according to the present embodiment, an analog switch 34 divided into blocks is used to select an arbitrary voltage dividing point of the resistor string 33, which is a main element of the variable gain, and an output is output for each block. As a result, the on-resistance of the analog switch 34 and the parasitic capacitance of the analog switch 34 can be reduced, and the frequency band of signal transmission by the analog switch 34 is extended. Variable gain amplifier 41 can be realized.

A ninth embodiment of the present invention will be described with reference to FIGS. This embodiment corresponds to the invention described in claim 5. The variable gain amplifier 46 according to the present embodiment includes an operational amplifier 47 and a digital setting type signal attenuator 48 interposed in a feedback path of the operational amplifier 47. This digital setting type signal attenuator 4
Reference numeral 8 denotes a series circuit of the R string circuit 32 having the configuration described in the seventh embodiment and the like and the resistance switching circuit 44 shown in FIG.

More specifically, the input signal is supplied to the operational amplifier 47.
The output of the operational amplifier 47 is connected to one input (V2) of the resistance switching circuit 44, and the other input (V1) of the resistance switching circuit 44 and the R string circuit 32
Is connected to one input (V2) of the R string circuit 3
The other input (V1) of 2 is connected to GND. The resistance switching circuit 44 determines an arbitrary resistance R according to the setting data DD5.
j is selected and the output of the R string circuit 32 (VO0 to VO0)
VO15), one output outputs an attenuated signal and the other becomes high impedance according to the setting data DD4. The terminal which became the attenuation signal output is the attenuation ratio RB / (Rj + RB) (RB: R string 3) with respect to the output of the operational amplifier 47.
3, the attenuation factor is selected in the range of Rj: the selected resistance value of the resistance switching circuit 44) to ∞ (infinity), and is fed back to the inverting inputs (IN0 to IN15) of the operational amplifier 47. Here, the overall gain is Av = (RB + Rj) / RB × 2 ^o / DD4 (times).

FIG. 17 shows an example of the configuration of the operational amplifier 47.
In FIG. 15, M10, M20, M11, M21,
, M115, M215 constitute the amplifier input unit 35 (IQ0 to IQ15) shown in FIG.
A differential pair is formed by any of active elements 0 to M115 and the FET transistor M2. A current source IS1 is connected to a common source of the differential pair, and a current mirror of FET transistors M3 and M4 is connected to each drain. Further, an output of the current mirror is connected to a common-source amplifier constituted by an FET transistor M5 to form an operational amplifier 47. C1 is a phase compensation capacitor.

A tenth embodiment of the present invention will be described with reference to FIGS. This embodiment corresponds to the invention described in claim 6. The variable gain amplifier 51 of the present embodiment includes a fixed gain amplifier 42 and a digital setting type signal attenuator 4 connected in front of the fixed gain amplifier 42.
3 and a digital setting type signal attenuator 48 interposed in the feedback path of the operational amplifier 52 having the gain A1 in the fixed gain amplifier 42. The digital setting type signal attenuator 43 includes the R string circuit 32A having the configuration described in the seventh embodiment and the like, and the resistance switching circuit 44A. In addition, a digital setting type signal attenuator 4
Reference numeral 8 denotes an R string circuit 32B having the configuration described in the seventh embodiment and the like, and a resistance switching circuit 44B shown in FIG.
And a series circuit.

More specifically, the input signal is connected to one input (V2) of the R string circuit 32A, and the other input (V1) of the R string circuit 32A is connected to the resistance switching circuit 44.
A is connected to one input (V1) of A and the resistance switching circuit 44
The other input (V2) of A is connected to GND. In the resistance switching circuit 44A, an arbitrary resistance Ri is selected by the setting data DD3, and the output (VO) of the R string circuit 32A is selected.
0 to VO15), one output outputs an attenuated signal and the others become high impedance according to the gain setting data DD1. The terminal that became the attenuation signal output is attenuation factor 1 (no attenuation)
To Ri / (Ri + RA) (RA: R string circuit 32
The attenuation rate is selected within a range of (the total resistance value of the R string 33 in A). The output (VO) of the R string circuit 32A
0 to VO15) are input to the non-inverting inputs (IN0 to IN15) of the fixed gain amplifier 42 including the operational amplifier 52, the feedback resistor R1, and the signal source resistor R2.

The output of the operational amplifier 52 is connected to the resistance switching circuit 44
B is connected to one input (V2) of B, and the resistance switching circuit 44
The other input (V1) of B and one input (V2) of the R string circuit 32B are connected, and the R string circuit 32B
The other input (V1) is connected to GND. The resistance switching circuit 44B sets an arbitrary resistance R according to the setting data DD5.
j is selected, and the output of the R string circuit 32B (VO0
To VO15), one output outputs an attenuated signal and the others become high impedance according to the setting data DD4. The terminal which became the attenuation signal output is the attenuation ratio RB / (Rj + RB) (RB: the total resistance value of the R string 33 in the R string circuit 32B, R
j: The attenuation rate is selected within the range of the selected resistance value of the resistance switching circuit 44B to ∞ (infinity), and is fed back to the inverting inputs (IN0 to IN15) of the operational amplifier 52. Here, the total gain is: Av = (RA × DD1 / 2 ^L + Ri) / (RA + Ri)
× (RB + Rj) / RB × 2 ^o / DD4 (times).

FIG. 19 shows a configuration example of the operational amplifier 52.
In FIG. 15, MN10, MN20, MN11, MN
21, ..., MN115, MN215 and MP10, MP
20, MP11, MP21,..., MP115, MP21
5 is an amplifier input unit 35 on the R string circuit 32B side.
(IQ0 to IQ15) and an amplifier input unit 35 (IQ0 to IQ15) on the R string circuit 32A side.
Any one of MN10 to MN115 active element and MP
A differential pair is formed with any of the active elements 10 to 115. A current source IS1 is connected to a common source of the differential pair, and a current mirror of FET transistors M3 and M4 is connected to each drain. Further, an output of the current mirror is connected to a common-source amplifier constituted by an FET transistor M5 to form an operational amplifier 52. C1 is a phase compensation capacitor.

The eleventh embodiment of the present invention will be described with reference to FIG. This embodiment is equivalent to the seventh aspect of the present invention.

In this embodiment, for example, an R switch having a configuration using the selection means 2 including the analog switch 4 shown in FIG.
This shows a case where the gain of a drive amplifier (not shown) at the preceding stage for driving the resistor string 1 is set to 1 in the string circuit 61 portion. As shown in the figure, the signal (VO2) on the side that is fed back to the drive amplifier is the on-resistance and the parasitic capacitance of the analog switch equivalent to VO1 on the side connected to the fixed gain amplifier 12, and the two analog switches 62 (SW1, SW2).
2), and the output of the source follower is also V
The output resistance and the parasitic capacitance equivalent to O1 are provided to the two source followers 63 (SF1, SF2). A current source Ibias, together with the analog switch 62 and the source follower 63, forms an analog switch group 64 equivalent to the analog switch group by the selection unit 2. In the illustrated example, the input / output of the analog switch 61 (SW2) is short-circuited with respect to the number m of the analog switches 4 connected to one block (one source follower 5) on the VO1 side by setting the parasitic capacitance of the analog switch to (m). -1) / 2
Similarly, when the number of blocks (the number of the source followers 5) is n, the parasitic capacitance applied to the source follower 63 (SF1) is nil.
3 (SF2) is realized by setting the element size to (n-1) times. Here, the ON state of the analog switch 62 means a low resistance state, the OFF state means a high resistance state, the ON state of the source follower 63 indicates that the internal shunt switch M2 is OFF, and the OFF state means This means that the shunt switch M2 is on.

In the example shown in FIG. 20, the example shown in FIG. 1 is used as an example of the selecting means. However, in the case of the multi-stage selecting means 7 shown in FIG. 3, the analog switch 4 shown in FIG. In the case of the selecting means 8 which further divides the voltage dividing point of the constituent resistance of the resistor string 1 by the on-resistance, or the selecting means 31 which divides the output into blocks as shown in FIG.
Also in the case of the above, feedback to the drive amplifier can be similarly performed with an equivalent configuration.

A twelfth embodiment of the present invention will be described with reference to FIG. This embodiment is equivalent to the seventh aspect of the present invention.

In FIG. 21, the R string circuit 61 has the structure shown in FIG. 20, and the resistance switching circuit 14
7 and FIG.

An input signal is input to a non-inverting terminal of an operational amplifier 66 having a gain of A2 through a source follower 65 formed by an N-type MOS transistor M2 and a current source Ibias2, and the output of the operational amplifier 66 is supplied to one input (V2 ), The other input (V1) of the R string circuit 61 is connected to one input (V1) of the resistance switching circuit 14, and the other input (V2) of the resistance switching circuit 14 is G
Connected to ND. In the resistance switching circuit 14, an arbitrary resistance Ri is selected by the setting data DD3, and the output (VO) of the R string circuit 61 is controlled by the gain setting data DD1 to have an attenuation rate of 1 (no attenuation) to Ri / (Ri + R) (R: R
The attenuation rate is selected within the range of the total resistance value of the string circuit 61). The output (VO2) of the R string circuit 61 is fed back to the inverting input of the operational amplifier 66 through an analog switch 62 and a source follower 63 equivalent to the other output (VO1). VO1 is input to a fixed gain amplifier 12 composed of an operational amplifier 15 having a gain A1, a feedback resistor R1, a signal source resistor R2, an N-type MOS transistor M1, and a current source Ibias1, and is output after being multiplied by (1 + R1 / R2). . Here, the N-type MOS transistor M2 and the current source I
A source follower 65 by bias2, an N-type MOS transistor M1 and a source follower 67 by current source Ibias1 are for canceling the offset voltage Vgs of the source follower 5 inside the R string circuit 61, respectively.
This is the same as the source follower 5 in the R string circuit 61. Here, the total gain is: Av = (1 + R1 / R2) × (R × DD1 / 2 ^L + R
i) / (R + Ri) (times).

Although the gain of the drive amplifier of the resistor string 1 is set to 1 here, it is possible to provide a gain or to switch some gains.

Therefore, according to the present embodiment, the gain of the drive amplifier in the preceding stage for driving the resistor string 1 is adjusted by the analog switch 62 and the source follower 63 for selecting the voltage dividing point similar to the attenuation signal output of the resistor string 1. For example, the feedback path of the drive amplifier has a frequency characteristic similar to that of the output of the attenuation signal, which can be corrected by the drive amplifier. Therefore, the frequency characteristic of the output of the attenuation signal is also corrected, and the band can be widened. In addition, since the gain of the drive amplifier is determined using the resistor string 1 that attenuates the signal, an error in the attenuation factor due to the relative accuracy of the constituent resistors of the resistor string 1 can be corrected to some extent. Can be done.

A thirteenth embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the eighth aspect of the present invention.

In the present embodiment, for example, an R switch having a configuration using the selecting means 2 including the analog switch 4 shown in FIG.
A signal used for phase compensation of an operational amplifier (not shown) for driving the resistor string 1 is a part of the string circuit 71, and a second selection means 7 is provided from an arbitrary voltage dividing point of the resistor string 1
2 through the analog switch and source follower. That is, a signal passed through an analog switch and a source follower from an arbitrary voltage dividing point of the resistor string 1 is used as a phase compensation signal of an operational amplifier, and a voltage dividing point of the resistor string selected for each gain range of the variable gain amplifier is determined. It is designed to be switched.

In the example shown in FIG. 22, the example shown in FIG. 1 is used as an example of the selecting means. However, in the case of the multi-stage selecting means 7 shown in FIG. 3, the analog switch 4 shown in FIG. In the case of the selecting means 8 which further divides the voltage dividing point of the constituent resistance of the resistor string 1 by the on-resistance, or the selecting means 31 which divides the output into blocks as shown in FIG.
In the same manner, the voltage can be supplied from an arbitrary voltage dividing point of the resistor string 1 through the analog switch and the source follower.

A fourteenth embodiment of the present invention will be described with reference to FIGS. This embodiment relates to claim 8
This corresponds to the described invention.

Referring to FIG. 23, R string circuit 71 has the structure shown in FIG.
This is shown in FIG.

The input signal is input to the non-inverting terminal of the operational amplifier 74 having the gain A1 through the source follower 73 composed of the N-type MOS transistor M1 and the current source Ibias. V
2) and the other input (V
1) and one input (V2) of the R string circuit 71 are connected, and the other input (V1) of the R string circuit 71 is connected to GND. The resistor switching circuit 14 selects an arbitrary resistor Rj according to the setting data DD5, and the output (VO1) of the R string circuit 71 uses the setting data DD4 to set an attenuation rate RB / (Rj) with respect to the output of the operational amplifier 74.
+ RB) (RB: total resistance value of R string circuit 71, R
j: The attenuation rate is selected in the range of the selected resistance value of the resistance switching circuit 14) to ∞ (infinity), and is fed back to the inverting input of the operational amplifier 74. The output VO2 for phase compensation of the R string circuit 71 is connected to the compensation terminal of the operational amplifier 74 through the compensation capacitor C1. Where N-type M
The source follower 73 formed by the OS transistor M1 and the current source Ibias is for canceling the offset voltage Vgs of the source follower 5 in the R string circuit 71. Here, the overall gain is Av = (RB + Rj) / RB × 2 ^o / DD4 (times), and the output level of the phase compensation output VO2 can be changed according to the gain, so that optimal phase compensation can be performed. .

In the example shown in FIG. 23, it is described that all the voltage dividing points of the resistor string 1 can be selected. However, since it is not necessary to change the signal level for the phase compensation at all the gain settings, the resistance is not changed. It is sufficient that only the necessary voltage dividing points of the string 1 can be selected. If the frequency characteristics can be improved by selecting several to several tens of voltage dividing points, the number of analog switches is also several.
Since only ten or more are required, switching of the source follower can be eliminated.

Here, a configuration example of the operational amplifier 74 is shown in FIG.
Shown in In the illustrated example, a current source IS1 is connected to a common source of a differential pair formed by the FET transistors M1 and M2, a current mirror is connected to each drain by FET transistors M3 and M4, and an output of the current mirror is connected to an FET transistor M5 and a current mirror. The source grounded amplifier by the source IS2 is connected. The drain of the FET transistor M5 is an output terminal, and the gate of the FET transistor M5 is a compensation terminal. The gates of the FET transistors M1 and M2 have inverting and non-inverting inputs, respectively.

Therefore, according to the present embodiment, the variable gain amplifier having the resistor string 1 in the feedback path of the operational amplifier 74 and feeding back an arbitrary voltage dividing point of the resistor string 1 is used. Since an arbitrary voltage dividing point is used as a signal for phase compensation through a voltage buffer consisting of an analog switch and a source follower, if the gain decreases due to variation in the relative accuracy of the constituent resistors, the amplitude of the signal for phase compensation increases. Deep phase compensation is applied, and conversely, when the gain is increased, it becomes shallow phase compensation,
Variations in the overall frequency characteristics are reduced. Further, since the amplitude of the phase compensation signal can be changed by the gain, optimal phase compensation can be performed at each gain.

The fifteenth embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the ninth aspect of the present invention.

In FIG. 25, R string circuit 61 has the structure shown in FIG. 20, R string circuit 71 has the structure shown in FIG. 22, and resistance switching circuits 14A, 1
4B is shown in FIG.

An input signal is input to a non-inverting terminal of an operational amplifier 66 through a source follower 65 formed by an N-type MOS transistor M1 and a current source Ibias, and an output of the operational amplifier 66 is connected to one input (V2) of an R string circuit 61. The other input (V1) of the R string circuit 61 is connected to one input (V1) of the resistance switching circuit 14A, and the other input (V2) of the resistance switching circuit 14A is connected to GND. In the resistance switching circuit 14A, an arbitrary resistance Ri is selected according to the setting data DD3.
Output (VO) is set to an attenuation rate of 1 according to the setting data DD1.
The decay rate is selected from the range of (no attenuation) to Ri / (Ri + R) (R: the total resistance value of the resistor string 1 in the R string circuit 61). The output of the R string circuit 61 (V
O2) is a selecting means 72 equivalent to the other output (VO1).
Is fed back to the inverting input of the operational amplifier 66 through the analog switch and the source follower. The output (VO1) of the R string circuit 61 is connected to the non-inverting input of the operational amplifier 74, the output of the operational amplifier 74 is connected to one input (V2) of the resistance switching circuit 14B, and the other of the resistance switching circuit 14B. Input (V1) and R string circuit 7
1 is connected to one input (V2), and the other input (V1) of the R string circuit 71 is connected to GND.
In the resistance switching circuit 14B, an arbitrary resistance Rj is selected by the setting data DD5, and the output (VO) of the R string circuit 71 is selected.
1) Attenuation rate RB / (Rj + RB) (RB: total resistance value of resistance string 1 in R string circuit 71, R
j: The attenuation rate is selected in the range of the selected resistance value of the resistance switching circuit 14B) to ∞ (infinity), and is fed back to the inverting input of the operational amplifier 74. The output VO2 for phase compensation of the R string circuit 71 is connected to the compensation terminal of the operational amplifier 74 through the compensation capacitor C1. Here, the source follower 65 formed by the N-type MOS transistor M1 and the current source Ibias is for canceling the offset voltage Vgs of the source follower 5 in the R string circuit 61, and is the same as the source follower 5 in the R string circuit 61. Things. Here, the total gain is Av = (RA × DD1 / 2 ^L + Ri) / (RA + Ri) × (R
B + Rj) / RB × 2 ^o / DD4 (times) Since the output level of the phase compensation output VO2 can be changed according to the gain set by DD4, optimal phase compensation can be performed.

Therefore, according to the present embodiment, the gain of the drive amplifier in the R string circuit 61 before driving the first resistor string is selected by selecting a voltage dividing point similar to the attenuation signal output of the first resistor string. Since the feedback path of the drive amplifier has the same frequency characteristics as the attenuation signal output, which can be corrected by the drive amplifier, the attenuation signal output also has a frequency characteristic. Characteristics are corrected,
Broadband is possible. Further, since the gain of the drive amplifier is determined using the first resistor string in the R string circuit 61 for attenuating the signal, the error of the attenuation factor due to the relative accuracy of the resistance of the resistor string can be corrected to some extent. The accuracy of the gain can be improved. The R string circuit 71 in the feedback path of the operational amplifier 74
Since the phase compensation signal is output from the second resistor string in the above, even if the gain varies, the variation in the overall frequency characteristics is reduced. Furthermore, since the amplitude of the phase compensation signal can be changed by the gain, optimal phase compensation can be performed at each gain. In addition, since the gain of the drive amplifier of the resistor string is determined through the same voltage dividing point selection switch and source follower as the attenuation signal output of the resistor string, the attenuation signal output is simultaneously corrected by correcting the frequency characteristics of the drive amplifier. Therefore, the band can be widened and the error in the attenuation rate can be corrected to some extent, so that the gain can be made more accurate.

In the example shown in FIG. 25, it is described that all the voltage dividing points of the resistor string 1 can be selected. However, since it is not necessary to change the signal level for phase compensation at all the gain settings, the resistance is not changed. It is sufficient that only the necessary voltage dividing points of the string 1 can be selected. If the frequency characteristics can be improved by selecting several to several tens of voltage dividing points, the number of analog switches is also several.
Since only ten or more are required, switching of the source follower can be eliminated.

Although the gain of the drive amplifier of the R string circuit 61 is set to 1 here, it is possible to provide a gain or to switch some gains.

[0113]

According to the first to third aspects of the present invention,
Since the analog OR circuit using the analog switch and the source follower is used as a means for selecting an arbitrary voltage dividing point of the resistor string which is a main element of the variable gain, the on-resistance of the analog switch and the parasitic capacitance attached to the analog switch can be reduced. The frequency bandwidth of signal transmission by analog switches is extended, and the use of a source follower enhances the driving capability of the load. A variable gain amplifier having a characteristic that is inversely proportional to the gain and the setting data can be realized.

According to the present invention, an analog switch divided into blocks is used for selecting an arbitrary voltage dividing point of a resistor string which is a main element of a variable gain.
Since the output is output for each block, the on-resistance of the analog switch and the parasitic capacitance attached to the analog switch can be reduced, and the frequency band of signal transmission by the analog switch is extended. On the other hand, a variable gain amplifier having an inversely proportional characteristic can be realized.

According to the seventh aspect of the present invention, the gain of the drive amplifier in the preceding stage for driving the resistor string is determined through an analog switch for selecting a voltage dividing point and a source follower similar to the attenuation signal output of the resistor string. For,
The feedback path of the drive amplifier has the same frequency characteristics as the output of the attenuation signal, which can be corrected by the drive amplifier. Therefore, the frequency characteristics of the output of the attenuation signal are also corrected, and the band can be widened. In addition, since the gain of the drive amplifier is determined using the resistor string that attenuates the signal, an error in the attenuation factor due to the relative accuracy of the constituent resistors of the resistor string can be corrected to some extent. I can do it.

According to the eighth aspect of the present invention, there is provided a variable gain amplifier having a resistor string in a feedback path of an operational amplifier and feeding back an arbitrary voltage dividing point of the resistor string. Since the point is used as a signal for phase compensation through a voltage buffer consisting of an analog switch and a source follower, if the gain decreases due to variation in the relative accuracy of the constituent resistors, the amplitude of the signal for phase compensation increases, so deep phase compensation is required. On the contrary, when the gain is increased, the phase compensation becomes shallow, and the variation in the overall frequency characteristics is reduced. Further, since the amplitude of the phase compensation signal can be changed by the gain, optimal phase compensation can be performed at each gain.

According to the ninth aspect of the present invention, the gain of the drive amplifier in the preceding stage for driving the first resistor string is adjusted by selecting an analog switch or a source follower for selecting a voltage dividing point similar to the attenuation signal output of the resistor string. Therefore, the feedback path of the drive amplifier has the same frequency characteristics as the output of the attenuated signal, and this can be corrected by the drive amplifier. Therefore, the frequency characteristic of the output of the attenuated signal is also corrected, and the band can be widened. In addition, since the gain of the drive amplifier is determined using the first resistor string that attenuates the signal, an error in the attenuation factor due to the relative accuracy of the constituent resistors of the resistor string can be corrected to some extent. Accuracy can be improved. Further, since the phase compensation signal is output from the second resistor string in the feedback path of the operational amplifier, the variation in the overall frequency characteristics is reduced even when the gain varies. Furthermore, since the amplitude of the phase compensation signal can be changed by the gain, optimal phase compensation can be performed at each gain.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an R string circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of the source follower.

FIG. 3 is a circuit diagram of an R string circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of an R string circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing various modifications of the source follower.

FIG. 6 is a circuit diagram of a variable gain amplifier according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram showing the resistance switching circuit.

FIG. 8 is a circuit diagram of a variable gain amplifier according to a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram of a variable gain amplifier according to a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram of an R string circuit showing a seventh embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration example of the amplifier input unit.

FIG. 12 is a circuit diagram showing a modification of the amplifier input unit.

FIG. 13 is a circuit diagram of a variable gain amplifier according to an eighth embodiment of the present invention.

FIG. 14 is a circuit diagram showing the resistance switching circuit.

FIG. 15 is a circuit diagram showing a configuration example of the operational amplifier.

FIG. 16 is a circuit diagram of a variable gain amplifier according to a ninth embodiment of the present invention.

FIG. 17 is a circuit diagram showing a configuration example of the operational amplifier.

FIG. 18 is a circuit diagram of a variable gain amplifier according to a tenth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a configuration example of the operational amplifier.

FIG. 20 is a circuit diagram of an R string circuit showing an eleventh embodiment of the present invention.

FIG. 21 is a circuit diagram of a variable gain amplifier according to a twelfth embodiment of the present invention.

FIG. 22 is a circuit diagram of an R string circuit showing a thirteenth embodiment of the present invention.

FIG. 23 is a circuit diagram of a variable gain amplifier according to a fourteenth embodiment of the present invention.

FIG. 24 is a circuit diagram showing a configuration example of the operational amplifier.

FIG. 25 is a circuit diagram of a variable gain amplifier according to a fifteenth embodiment of the present invention.

FIG. 26 is a circuit diagram showing a first conventional variable gain amplifier.

FIG. 27 is a circuit diagram showing the R-2R ladder resistor.

FIG. 28 is a circuit diagram showing a second conventional variable gain amplifier.

FIG. 29 is a circuit diagram showing a third conventional variable gain amplifier.

FIG. 30 is a circuit diagram showing the attenuator.

FIG. 31 is a circuit diagram showing a fourth conventional variable gain amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Resistance string 2 Selection means 4 Analog switch 5 Source follower 7, 8 Selection means 11 Variable gain amplifier 12 Fixed gain amplifier 13 Digital setting type signal attenuator 16 Variable gain amplifier 17 Operational amplifier 18 Digital setting type signal attenuator 21 Variable gain amplifier 31 Selection means 33 Resistor string 34 Analog switch 41 Variable gain amplifier 42 Fixed gain amplifier 43 Digital setting type signal attenuator 45 Operational amplifier 46 Variable gain amplifier 47 Operational amplifier 48 Digital setting type signal attenuator 51 Variable gain amplifier 52 Operational amplifier 62 Analog Switch 63 Emitter follower 64 Analog switch group 74 Operational amplifier

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5C051 AA01 BA03 DA03 DB01 DB15 DE15 DE17 EA02 FA01 FA04 5C072 AA01 BA04 EA05 UA05 UA06 XA01 5C077 LL17 LL18 MM03 PP11 PQ03 PQ04 PQ08 PQ11 RR01 5J100 AA03 BC CA02 CA05 CA12 CA20 CA28 CA29 JA01 KA05 LA10 LA11 QA01 QA02 QA04

Claims (9)

[Claims] 1. A CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, comprising: a digital setting type signal attenuator using a resistor string; and a fixed gain amplifier. A variable step-up gain amplifier comprising a single-stage or multi-stage analog switch and a source follower, and a selection means for selecting a divided voltage signal at an arbitrary point in the resistor string. Image signal processing circuit. 2. A CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, wherein a digital setting type signal attenuator using a resistor string is used for feedback. A variable gain amplifier comprising an amplifier, an analog OR circuit comprising a one-stage or multi-stage analog switch and a source follower, and a selecting means for selecting a divided voltage signal at an arbitrary point of the resistor string. Image signal processing circuit. 3. A CCD analog signal processing circuit for converting only an image signal component according to an input light amount from an output signal of a CCD linear image sensor into digital data, comprising: a digital setting type signal attenuator using a first resistor string; A small step variable gain amplifier using a digital setting type signal attenuator using a second resistor string for feedback, and an analog OR circuit using a one-stage or multi-stage analog switch and a source follower. An image signal processing circuit comprising a selection means for selecting a divided voltage signal at an arbitrary point of each resistor string. 4. A CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, comprising: a digital setting type attenuator using a resistor string; and a fixed gain amplifier. A variable step-up gain amplifier having an output for each block, each block comprising an analog OR circuit comprising an analog switch having one or more stages and a source follower, and a voltage divider at an arbitrary point of the resistor string. Selecting means for selecting a signal, wherein the fixed gain amplifier has an input corresponding to an output of each block of the resistor string, and an input corresponding thereto is enabled when an output of a certain block is enabled. An image signal processing circuit characterized by: 5. A CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor to digital data, wherein a digital setting type signal attenuator using a resistor string is used for feedback. It has a variable gain amplifier by an amplifier, has an output for each block, and each block is composed of an analog OR circuit composed of a one-stage or multi-stage analog switch and a source follower, and outputs a divided voltage signal at an arbitrary point of the resistor string. Selecting means for selecting, wherein the operational amplifier has an inverting input corresponding to the output of each block of the resistor string, and when the output of a certain block is valid, the inverting input corresponding thereto is valid. An image signal processing circuit, characterized in that: 6. A CCD analog signal processing circuit for converting only an image signal component corresponding to an input light amount from an output signal of a CCD linear image sensor into digital data, comprising: a digital setting type signal attenuator using a first resistor string; A small step variable gain amplifier using a digital setting type signal attenuator using a second resistor string as a feedback, and an output for each block, each block having an analog switch of one-stage or multi-stage configuration, A source follower and an analog OR circuit having selection means for selecting a divided voltage signal at an arbitrary point in each of the resistor strings, wherein the operational amplifier has an inverting / non-inverting circuit corresponding to an output of each block of the resistor string. It has an inverting input, and when the output of a block is valid, the corresponding inverting / non-inverting input is valid. An image signal processing circuit characterized in that: 7. A group of analog switches equivalent to a group of analog switches for supplying a signal to the fixed gain amplifier to a signal at a corresponding voltage dividing point of the resistor string by feedback to a drive amplifier at a preceding stage for driving the resistor string. 5. The image signal processing circuit according to claim 1, wherein the image signal processing circuit is configured to perform the processing. 8. A signal passing through the analog switch and the source follower from an arbitrary voltage dividing point of the resistor string is used as a signal for phase compensation of the operational amplifier, and is selected for each gain range of the variable gain amplifier. 6. The image signal processing circuit according to claim 2, wherein a voltage dividing point of the resistor string is switched. 9. An analog switch group for supplying feedback to a drive amplifier in a preceding stage for driving the first resistor string and supplying a signal at a corresponding voltage dividing point of the first resistor string to the fixed gain amplifier. Using a signal passed through the analog switch and the source follower from an arbitrary voltage dividing point of the second resistor string as a phase compensating signal of the operational amplifier. 7. The image signal processing circuit according to claim 3, wherein a voltage dividing point of said second resistor string selected for each gain range is switched.