JP2000259394A - Floating point multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a floating point multiplier which performs floating point multiplication at high speed by generating a sticky bit in parallel to the multiplication of mantissa part of floating point data. SOLUTION: Mantissa part M0 and M1 of the floating point data are inputted to a multiplication array 1 and also inputted to zero counting means 4-1 and 4-2 at the same time. The zero counting means 4-1 and 4-2 count the number of zero during the period until 1 appears for the first time from the least significant digit bits of the mantissa part M0 and M1 and an adder 5 sums up their zero count results of the mantissa parts M0 and M1. A comparison circuit 6 compares the adding results of the adder 5 with a constant, 1 as the sticky bit is outputted if the constant is larger than the adding result of the adder 5 and 0 as the sticky bit is outputted if the constant is smaller than the adding result of the adder 5 or the constant is equal to the result. Consequently, it becomes possible to obtain a result of the floating multiplication at high speed because a sticky bit can be generated without using the result which is from the multiplication array 1 and a mantissa part adder 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a floating-point multiplier, and more particularly, to a multiplier that performs high-speed floating-point multiplication by generating sticky bits in parallel with a multiplication operation of a mantissa part of floating-point data.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, an exponent adder 3, a multiplication array 1, a mantissa adder 2, an OR circuit 8, a rounding digit matching circuit 7, It was constituted having. The operation in this configuration is as follows. First, the exponent parts E0 and E1 of the floating-point data cut out in the preprocessing stage are added by the exponent part adder 3, and the mantissa parts M0 and M1 of m (positive integer) bits of the floating-point data. Is input to the multiplication array 1 to perform multiplication, and the two outputs A and B of the multiplication array 1 are added by the mantissa adder 2 to obtain (2
(m-1) A mantissa multiplication result C of bits is obtained. In the output of the mantissa adder 2, the total OR S ′ of the lower (m−1) bits J to be truncated is obtained by the OR circuit 8. The rounding and digit matching circuit 7 outputs the output I of the floating point multiplier from the output D of the exponent part adder 3 and the upper m bits C of the output of the mantissa part adder 2 using the total OR S ′ as a control signal. It was that. In this configuration, the output of the mantissa adder required by the rounding digit matching circuit 7 is the upper m bits C
And the sticky bit indicated by the total logical sum S ′ of the truncated lower (m−1) bits J. The total OR S 'can be obtained only after the multiplication is completely completed. Therefore, the total delay time of the conventional floating-point multiplier is: pre-processing + mantissa multiplication + calculation of total OR S ′ + rounding digit alignment. One of the maximum delay paths in the vessel. A method for obtaining an input to the OR circuit without waiting for the end of the multiplication is described in, for example, Japanese Patent Application Laid-Open No. 2-224121.
In the publication, as shown in FIG. 3, a multiplication array 100, a zero counting means 103 provided in parallel with a multiplication circuit for mantissa data by an adder 101, an operation means 104, and an OR circuit 10
5 describes a technique for obtaining a sticky bit. By using the result of passing through the zero counting means 103 and the arithmetic means 104 as an input to the OR circuit 105, the operation of calculating the total OR is started without waiting for the output of the multiplication circuit of the mantissa data.

[0003]

However, this prior art has the following problems. That is, the problem is that the time required for sticky bit generation is long. Since sticky bit generation occupies one step of the total delay time of the floating point multiplier, if the sticky bit generation takes time, the operation speed of the floating point multiplier as a whole decreases. The reason is that a signal passing through the output of the multiplication circuit of the mantissa data is used as the control signal used in the OR circuit. On the other hand, Japanese Patent No. 2676410 does not describe a technique of generating sticky bits from a multiplication circuit of mantissa data, but inputs multiplicand mantissa data and multiplier mantissa data and performs processing from the least significant bit until 1 appears. A technique using zero counting means for counting the number of zeros has been disclosed. The present invention also provides a floating point multiplier that solves the problem by means of zero counting.

[0004]

SUMMARY OF THE INVENTION A floating-point multiplier according to the present invention performs high-speed floating-point multiplication by generating sticky bits in parallel with a multiplication operation of a mantissa of floating-point data. In FIG.
The mantissa parts M0 and M1 of the floating-point data are the multiplication array 1
At the same time as the input to the zero counting means 4-1 and 4-2. In the zero counting means 4-1 and 4-2, the mantissa M0
, And the number of zeros from the least significant bit of the M1 to the appearance of a 1 is counted, and the adder 5 adds the zero count results of the mantissa parts M0 and M1. The comparison circuit 6 compares the addition result of the adder 5 with the constant. If the constant is larger than the addition result of the adder 5, 1 is output as a sticky bit. If they are smaller or equal, 0 is output as a sticky bit. As a result, the sticky bit can be generated without using the result passed through the multiplication array 1 and the mantissa adder 2, so that the result of the floating-point multiplication can be obtained at high speed. The floating-point multiplier according to claim 1 performs a rounding digit matching process by directly generating sticky bits from the mantissa data in parallel with the multiplication operation of the mantissa data of the floating-point data, The sticky bit generating means receives the multiplicand mantissa data and the multiplier mantissa data and counts the number of zeros from the least significant bit to the appearance of one. An adder for adding the zero counts of the zero counting means, and comparing the addition result of the adder with a constant, and outputting a sticky bit = 1 when the constant is larger than the addition result of the adder;
A comparison circuit that outputs a sticky bit = 0 if the constant is smaller than or equal to the addition result of the adder. According to a second aspect of the present invention, in the floating-point multiplier according to the first aspect, when the number of digits of the multiplicand mantissa data is set to m and the number of digits of the multiplicand mantissa data is set to m, the comparison circuit Is set to m-1. According to a third aspect of the present invention, there is provided a method in which the least significant bit of each of the multiplicand mantissa data and the multiplier mantissa data is changed from the least significant bit until 1 appears.
Two zero counting means for counting the number of zeros, an adder for adding the zero counts of the two zero counting means, and comparing the addition result of the adder with a constant. A sticky bit generating means having a sticky bit = 1 if the value is larger, a comparing circuit outputting a sticky bit = 0 if the constant is smaller than or equal to the addition result of the adder, and a multiplicand mantissa. A multiplication array that inputs partial data and multiplier mantissa data, calculates a partial product by multiplying the two, adds a plurality of partial products, and outputs a two-output partial product, and adds the two-output partial product A sticky bit generator comprising: a mantissa adder for outputting a result of the mantissa addition; and an OR circuit for calculating a total OR of the lower bits to be truncated among the outputs of the mantissa adder. It is characterized by having a check circuit for comparing the sticky bits generated by both means.

[0005]

FIG. 1 is a block diagram showing a configuration example of a floating-point multiplier according to an embodiment of the present invention. The multiplication array 1 is connected to the mantissa adder 2 and performs multiplication by using the mantissas M0 and M1 of m (positive integer) bits of the floating-point data cut out in the preprocessing stage as inputs, and performs two partial products. A and B are obtained. The sum of the two partial products A and B output from the multiplication array 1 is the result of multiplication of the mantissa. The mantissa adder 2 is connected to the multiplier array 1 and the rounding / digit matching circuit 7 and performs an addition using the two partial products A and B, which are the outputs of the multiplier array 1, as an input. Top m
The bit C is output to the rounding digit matching circuit 7. The exponent part adder 3 is connected to the rounding and digit matching circuit 7, adds the exponent parts E0 and E1 of the floating-point data cut out in the preprocessing stage, and outputs the exponent part addition result D to the rounding and digit matching circuit 7. . The zero counting means 4-1 and 4-2 are connected to the adder 5, count the number of zeros from the least significant bit of the mantissa parts M0 and M1 to the appearance of one, and add the count results F and G to the adder. Output to 5 The adder 5 is connected to the zero counting means 4-1 and 4-2 and the comparison circuit 6, adds the outputs F and G of the zero counting means 4-1 and 4-2, and outputs the addition result H to the comparison circuit 6. Output. The comparison circuit 6 is connected to the adder 5 and the rounding digit matching circuit 7, and the addition result H of the adder 5
And a constant (m-1) obtained by subtracting 1 from the significant digit m of the mantissa, and outputs the result to the rounding digit matching circuit 7 as a sticky bit S. The rounding / digit matching circuit 7 is connected to the mantissa adder 2, the exponent adder 3, and the comparison circuit 6, and uses the sticky bit S output from the comparison circuit 6 as a control signal to output the output D of the exponent adder 3. And mantissa adder 2
Outputs the multiplication result I of the floating-point multiplier from the upper m bits C of the output.

FIG. 4 shows an embodiment of the present invention where m = 52.
FIG. 4 is a detailed configuration diagram of the zero counting means 4-1 and 4-2 at the time of FIG. The zero counting means 4 includes three stages of the zero counting circuit 20 shown in FIG. The zero counting means 4 inputs the least significant bit of the 52-bit mantissa data to M0 [00] and the most significant bit to M0 [51] to the zero counting circuit 20 four bits at a time from the least significant bit. The zero counting circuit 20 outputs the number of 0s from the least significant bit to a 4-bit input as a 3-bit binary number. At the time of output, only the most significant bit of the three bits is inverted. Of the output of the first stage zero counting circuit 20, the most significant bit becomes an input to the next stage zero counting circuit 20, and the lower two bits become an input to the selector 21. The selector 21 is connected to the zero counting circuit 20 and the selector 22, and the zero counting circuit 2
The four low-order 2 bits of the output of 0 are input, and the low-order 2 bits of the output of the second stage zero counting circuit 20 are used as a control signal.
One of the sets is selected and output to the selector 22. The selector 22 is connected to the selector 21 and the zero-counting circuit 20, and receives as input a 4-bit, 4-bit combination of the lower two bits of the output of the second-stage zero-counting circuit 20 and the output 2 bits of the selector 21, and the third-stage One of four sets is selected and output using the lower 2 bits of the output of the zero counting circuit 20 as a control signal. The lower 2 bits of the output of the third stage zero counting circuit 20;
The 6-bit result obtained by adding the 4 bits of the output of the selector 22 becomes the output F of the zero counting means 4-1. An output H obtained by inputting the output F of the zero counting means 4-1 thus output and the output G of the zero counting means 4-2 similarly output to the adder 5, a constant m-1 and To obtain a sticky bit S. FIG. 6 shows the value of the sticky bit S corresponding to the output H (the determination of the sticky bit by the comparison circuit 6 will be described in the following operation of the multiplier).

FIG. 7 shows an embodiment of the present invention in which m = 52.
9 is a detailed circuit diagram of the comparison circuit 6 at the time of FIG. When m = 52, the comparison circuit 6 outputs the 7-bit output H [6:
[0] is input, a comparison is made with a constant (m-1 = 51), and when the constant (m-1) is larger than H, 1 is output.

Next, the operation of the multiplier of FIG. 1 will be described with reference to the drawings. The floating-point data is composed of a sign bit of 1 bit, an exponent E of n (positive integer) bits, and a mantissa M of m (positive integer) bits, and is cut out by a preprocessing circuit. In the multiplication of floating-point data, a result can be obtained by performing addition of an exponent part and multiplication of a mantissa part, and then performing rounding and digit alignment. First, the exponent parts E0 and E1 of the floating-point data cut out in the preprocessing stage are
The result is added by the exponent part adder 3, and the obtained exponent part addition result D is output to the rounding and digit matching circuit 7. The m-bit mantissa parts M0 and M1 of the floating-point data cut out in the preprocessing stage are used as the multiplication array 1 and the zero counting means 4-1 and 4-2.
Is input to With reference to FIG. 8, the multiplication array 1 arranges the input mantissa M0 as a multiplicand and M1 as a multiplier, and multiplies each bit of the multiplier by a multiplicand (called a partial product) in a binary arithmetic form. The product is obtained by adding these. The addition of each partial product is performed by using an adder circuit composed of a full adder as shown in FIG. 9 so that m partial products are added up to two, and two finally obtained products are obtained. The partial products A and B are output to the mantissa adder 2. The mantissa adder 2 adds the two outputs A and B of the multiplication array 1 and obtains (2m-1) as a multiplication result of the m-bit mantissas M1 and M2.
Get the product of bits. Among these products, the higher-order m bits C, which are significant digits of the mantissa, are output to the rounding / digit matching circuit 7. Generally, the total OR of the lower (m-1) bits to be truncated is used as a sticky bit for rounding. If all the lower (m-1) bits to be discarded are 0, the sticky bit is 0. Referring to FIG. 8, the number of zeros until the 1 appears from the lower bits of the product of the mantissa parts M0 and M1 is the number F of the zeros until the 1 appears from the lower bits of each of the mantissas M0 and M1. And G are equal to the sum H. Therefore, the sum H of the numbers F and G of 0s until the 1 appears from the lower bits of the mantissa parts M0 and M1 is calculated, and this value is compared with the number of bits to be truncated (m-1). The number of bits (m−m−m) that is the sum of the number H of 0 and the sum H of G until a 1 appears from the lower bit of M1
1) If greater or equal, there is no 1 in the bits to be truncated, so the sticky bit is 0, and if the number of bits to be truncated (m-1) is larger, then 1 in the bits to be truncated. It will be present and the sticky bit will be 1. Referring to FIG. 1, the zero counting means 4-1 and 4-2 count the number of zeros from the least significant bit of the mantissa parts M0 and M1 until 1 appears, and add the count results F and G, respectively. Input to the container 5. Referring to the configuration diagram of the zero counting means 4 when m = 52 shown in FIG. 4, inside the zero counting means 4, the mantissa part M0 sets the least significant bit to M0 [00] and sets 4 bits from the least significant bit. Are input to the zero counting circuit 20. The first-stage zero counting circuit 20 counts the number of zeros from the lower bits of the four bits, and
Output as a binary number of bits (however, the most significant bit is inverted and output). The most significant bit becomes an input to the next stage zero counting circuit 20, and the lower two bits become an input to the selector 21. The second-stage zero counting circuit 20 receives the most significant bit of the output of the first-stage zero counting circuit 20 as an input, counts the number of zeros, and outputs it as a 3-bit binary number. Selector 2
Reference numeral 1 designates one of the four sets of the lower two bits of the output of the first stage zero counting circuit 20 as a control signal and the lower two bits of the output of the second stage zero counting circuit 20 as a control signal. , To the selector 22. The third-stage zero counting circuit 20 counts the number of zeros by using the most significant bit of the output of the second-stage zero counting circuit 20 as an input, and outputs it as a 3-bit binary number. Of the 3-bit output, the most significant bit is not used (m is 64 or less), and the lower 2 bits F [5] F
[4] is a mantissa M representing 32 and 16 in decimal respectively
The count value becomes 0. The selector 22 receives four 4-bit combinations of the lower two bits of the output of the second stage zero counting circuit 20 and the two bits of the output of the selector 21, and receives the lower two bits of the output of the third stage zero counting circuit 20. Is used as a control signal to select and output one of the four sets. 4 of selector 22
The bit outputs F [3] to F [0] are the count values of the mantissa M0 representing 8, 4, 2, and 1 in decimal, respectively.
The 6-bit output of F [5] to F [0] is the count value of 0 from the least significant bit of the mantissa part 52 bits. In addition,
Referring to FIG. 4, the number of logical stages required by the zero counting means 4 is a maximum of seven stages. The adder 5 adds the count results F and G, and sends the addition result H to the comparison circuit 6. The comparison circuit 6 compares the addition result H with a constant (m-1), and outputs 0 as the sticky bit S when the addition result H is larger than or equal to the constant (m-1), and outputs a constant ( m-
If 1) is larger, S = 1 is output. When m = 52, the addition result H is represented by 7-bit binary numbers, and the truth table of S, which is the result of comparison with (m-1 = 51), is shown in FIG. FIG. 7 is a circuit diagram of the comparison circuit 6 based on FIG. 6, which is realized with a maximum of five logic stages. The rounding / digit matching circuit 7 outputs an exponent part addition result D output from the exponent part adder 3, a mantissa addition result C output from the mantissa part adder 2, and a sticky bit S output from the comparison circuit 6. And the output I of the multiplication result is output from the exponent addition result D and the mantissa addition result C using the sticky bit S as a control signal.

As described above, the zero counting means 4 having the input of the mantissa part, the adder 5 having the input of the output of the zero counting means 4 as an input, and the output of the adder 5 being an input being compared with a constant to be sticky. By providing the comparison circuit 6 for generating the bits, the step required for generating the sticky bit when the significant digit m of the mantissa is 52 bits is zero counting means 4 (the number of logic stages is 7).
Stage) + adder 5 (6-bit adder) + comparator circuit 6 (5 logical stages), which is multiplication array 1 (1 logical product + full adder 2 * 5 stages) + mantissa adder 2 Sticky bit generation can be realized at higher speed than in the configuration of (103-bit adder) + OR circuit 8 (4 logical stages).

Another embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 10, a logical sum circuit 8 having an input of an output J of the mantissa adder 2 and a logical sum circuit 8
And a check circuit 9 which receives the output S ′ of the comparator circuit 6 and the output S of the comparison circuit 6 as inputs. The lower (m-1) bits J of the addition result of the mantissa adder 2 which are truncated are added to the OR circuit 8
And the OR circuit 8 obtains the total OR S 'of J.
Since S 'is a sticky bit obtained by the conventional method, the check circuit 9 compares this S' with the sticky bit S output from the comparison circuit 6 to obtain the sticky bit S obtained from the mantissa. Is consistent with the sticky bit S ′ obtained from the result of the mantissa multiplication that has passed through the multiplication array and the mantissa adder. This embodiment has a new effect that a sticky bit can be checked with a small amount of hardware without duplicating circuits having a large amount of hardware such as a multiplication array and a mantissa adder.

[0011]

As described above, according to the present invention, the following effects can be expected. That is, the greatest effect is that the operation speed of the whole floating-point multiplier can be increased. The reason is that, apart from a multiplication array and a mantissa adder which receives two outputs of the multiplication array as inputs, a zero counting means having a mantissa as an input, an adder having an output of the zero counting means as an input, By providing a comparison circuit that generates a sticky bit by comparing an output of the adder with a constant and generating a sticky bit, a sticky bit can be obtained without obtaining the total OR of the lower bits of the truncated mantissa multiplication result Because.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a floating-point multiplier according to the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of a conventional floating point multiplier.

FIG. 3 is a block diagram showing a configuration of one embodiment of a conventional sticky bit generation unit.

FIG. 4 is a block diagram showing a configuration of zero counting means of the floating-point multiplier of the present invention (the number of bits of the mantissa part of the floating-point data is 52).

FIG. 5 is a circuit diagram of a zero counting circuit constituting the zero counting means of the present invention.

FIG. 6 is a truth table of the sticky bit S;

FIG. 7 is a circuit diagram of a comparison circuit based on a truth table of sticky bits S;

FIG. 8 is a diagram in which multiplications of a 5-digit multiplicand and a 5-digit multiplier are arranged in a handwriting format.

FIG. 9 is a block diagram of an adder circuit including a full adder for a multiplication array.

FIG. 10 is a block diagram showing a configuration of another embodiment of the floating-point multiplier of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 multiplication array 2 mantissa adder 3 exponent adder 4 zero counting means 5 adder 6 comparison circuit 7 rounding digit matching circuit 8 OR circuit 100 multiplication array 101
Adder 102 ... Shifter 103 ...
Zero counting means 104 ... Calculation means 105 ...
OR circuit 20 ... Zero counting circuit 21 ... Selector 22 ... Selector 9 ... Check circuit

Claims (3)

[Claims] 1. A floating-point multiplier for performing rounding and digit matching processing by directly generating sticky bits from mantissa data in parallel with an operation of multiplying mantissa data of floating-point data. The generating means inputs the multiplicand mantissa data and the multiplier mantissa data,
Two zero counting means for counting the number of zeros from each least significant bit until a 1 appears, an adder for adding the zero counts of the two zero counting means, an addition result of the adder and a constant And if the constant is larger than the addition result of the adder, the sticky bit = 1
And a comparing circuit that outputs a sticky bit = 0 if the constant is smaller than or equal to the addition result of the adder. 2. The method according to claim 1, wherein when the number of digits of the multiplicand mantissa data is set to m and the number of digits of the multiplicand mantissa data is set to m, a constant compared by the comparison circuit is m-1. The floating point multiplier according to claim 1. 3. From the least significant bit of each of the multiplicand mantissa data and the multiplier mantissa data, 0 is used until 1 appears.
Two zero counting means for counting the number of zeros; an adder for adding the zero counts of the two zero counting means; comparing the addition result of the adder with a constant; Is larger, sticky bit = 1
And a comparison circuit that outputs a sticky bit = 0 if the constant is smaller than or equal to the addition result of the adder; and a sticky bit generation means comprising: and multiplicative mantissa data and multiplier mantissa data. Enter
A multiplication array that calculates a partial product by multiplication of the two, adds a plurality of partial products and outputs a two-output partial product, and a mantissa adder that adds the two output partial products and outputs a mantissa addition result And an OR circuit for calculating the total OR of the lower bits to be truncated among the outputs of the mantissa adder, and a check circuit for comparing the sticky bits generated by both of the sticky bit generation means, comprising: A floating point multiplier comprising: