JP2000253316A - Cmos image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output both of an absolute value and a difference from a front frame by providing sample and hold circuits respectively holding the signal potential of the former frame of a selected pixel sensor, a reset potential after resetting a detection node and the signal potential of a present frame. SOLUTION: In a reading circuit 20, a signal potential Vc including the noise of the present frame is kept to have a capacity CC by turning on a switch SHC; a signal potential Vp including the noise of the former frame is kept to have a capacity CP by turning on a switch SHP; a reset potential Vr including noise is kept to have a capacity CR by turning on a switch SHR. Then, an absolute value (Vc-Vr) or reduced noise components is measured by turning on a switch SWR and a difference (Vc-Vp) from the former frame of reduced noise component is measured by turning on a switch SWP. However, since an hourly distance is generated, the reset noise of the pixel sensor 10 and the white noise of the circuit 20 cannot be reduced perfectly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS image sensor and, more particularly, to a CMOS image sensor which is suitable for use in a digital still camera capable of picking up moving images and a digital video camera requiring motion detection for camera shake correction. The present invention relates to a CMOS image sensor capable of outputting both an absolute value and a difference from a previous frame.

[0002]

2. Description of the Related Art Attention has been focused on a CMOS image sensor as an image pickup device replacing a CCD image sensor. Since this CMOS image sensor has much noise, it is necessary to take some measures against noise.

For example, “CMOS Active Pixel Image
Sensors for Highly Integrated Imaging Systems ”S
unetra K. Mendis and others, Journal of Solid-State Circu
its, Vol.32, No.2, Feb.1997, P187-197 (hereinafter referred to as English literature) has a transfer gate TX as shown in FIG. 1 (circuit diagram) and FIG. 2 (timing chart).
Diffusion, F separated by
A photogate PG having an output FD is also disclosed. The pixel sensor further includes a reset transistor MR and a source follower MI in the pixel.
N and a column select transistor MX.

A common readout circuit for pixels in the same row is a load transistor MLN of the first source follower.
And two sample-and-hold circuits for storing the signal potential and the reset potential. To reduce random noise and fixed pattern noise in the pixel sensor and readout circuit, sample the reset potential containing noise and the signal potential containing the same noise in a short period of time, in which the magnitude of the noise has a strong temporal correlation. Correlation double sampling, which subtracts the reset potential from the signal potential, is effective, and can suppress reset noise, 1 / f noise, and threshold fluctuation from the source follower in the pixel from the floating diffusion node of the pixel.

Each sample-and-hold circuit includes sample-and-hold switches MSHS and MSHR, capacitors CS and CR, and row source followers MP1 and MP2 for buffering a capacitor potential and reading a high-capacity horizontal bus at high speed. It includes transistors MY1 and MY2. The load transistors MLP1 and MLP2 of the row source follower
Common for all arrays of pixels. To compensate for a change in signal potential due to an N-channel source follower in a pixel, a P-channel source follower is used in the row circuit.

Furthermore, each row output circuit has a circuit for selectively short-circuiting two sample-and-hold capacitors CS and CR.
A crowbar switch CB and two row selection switches MS1 and MS2 are provided.

The operation of this CMOS image sensor is as shown in FIG. That is, first, the power supply voltage VDD
And VSS are set to 5V and 0V, respectively, and the transfer gate TX is biased to 2.5V. The load transistors MLN, MLP1, and MLP2 of the intra-pixel source follower and the row source follower are each 1.5 V
And 2.5V DC bias.

In the signal accumulation period shown in FIG.
The electrons generated by the light are collected on the surface channel photogate PG biased at 5V. Here, the reset transistor MR is biased to 2.5V and acts as a lateral antiblooming drain so that excess signal charge flows to the reset drain. The column select transistor MX is biased to 0V. After signal accumulation, all columns of pixels are read out simultaneously.

Specifically, first, the pixels in the column to be read are addressed by turning on the column selection switch MX. Next, as shown in FIG. 3B, the floating diffusion output node FD of the pixel is connected to the reset gate M
This is reset by temporarily setting R at 5 V (see FIG. 3B). Thereby, the floating diffusion output FD
Is reset to about 3.5V.

When the output of the first source follower turns on the sample hold switch MSHR,
It is sampled on the bottom row capacitor CR. Next, as shown in FIG. 3C, the bottom of the potential well of the PG is temporarily lifted, and the accumulated charge due to the photocurrent is transferred to the FD. Next, as shown in FIG. 3D, by turning on the sample hold switch MSHS, the signal potential of the FD is held in the capacitor CS of the reading circuit.

The held reset potential and signal potential are:
The data is sequentially read through the second set of source followers by the row selection switches MY1 and MY2.

The capacitances CS and CR thus held are
Is obtained. Next, Clover switch C
With B turned on, the selected two sample-hold capacitors CS and CR are temporarily short-circuited, and the potential difference Δ2 is obtained again.

In this way, the absolute value of the signal potential excluding the offset of the readout circuit is obtained from (Δ1−Δ2) (referred to as delta difference sampling DDS).

Finally, the FD reset signal R and the transfer signal TX are temporarily turned on, the PG is reset, and light is taken in again.

"Image compression CMOS image sensor based on analog two-dimensional DCT (discrete cosine transform) circuit and precision adaptive A / D converter" Shoji Kawahito et al., Journal of the Institute of Image Information and Television Engineers, Vol. 52, no. 2, pp 206-213
(1998) discloses a CMOS image sensor in which an analog two-dimensional DCT circuit is integrated to perform image compression on the sensor, as shown in FIG.
It is described that a switched capacitor circuit SCC is used as O, and two-stage amplifiers A1 and A2 for capacitive feedback and clocks φ1 and φ2 that do not overlap each other are used.

Specifically, first, the feedback capacitance Cf1 of the first-stage amplifier A1 is reset by setting φ2 = 1.

Next, assuming that φ1 = 1, the signal charge from the photodiode PD is transferred to the feedback capacitor Cf1 of the first-stage amplifier A1.

Next, assuming that φ2 = 1, the sampled signal component is transferred to the feedback capacitor Cf2 of the amplifier A2 in the next stage and output. As a result, the offset of the first-stage amplifier A1 of the read circuit is removed.

The signal output for one column of one block obtained in this way is processed by a one-dimensional DCT circuit.

In FIG. 4, ISA is an image sensor array, Vs is a vertical (block) scanner, Vh is a horizontal scanner, and Tc is a coupling transistor group.

[0021]

The output signal in the former prior art is digitally converted by an A / D converter and stored in a frame memory, and the difference between the output signal and the data in the frame memory storing the previous frame is obtained. Although it is calculated and used for motion detection and the like, it requires a plurality of large frame memories and a large amount of arithmetic processing, and has a problem that power consumption is large.

On the other hand, in the latter conventional technique, the pixel sensor is composed of only a photodiode and two CMOSs, and the structure is simple, so that the pixel sensor can be made small. Cannot remove noise. Also, analog 2
In some cases, the frame memory can be deleted by the dimensional DCT circuit, but the difference between frames cannot be obtained, so that the MPEG standard, which is a general standard for moving image compression, cannot be used. There was a problem that there were many.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a CMOS image sensor capable of selectively outputting either an absolute value or a difference from a previous frame.

[0024]

According to the present invention, in a CMOS image sensor, a pixel sensor capable of holding a signal charge of a previous frame, a signal potential Vp of a previous frame of the selected pixel sensor, and a detection node are reset. And a means for outputting a difference between frames by (Vc-Vp) and an absolute value by (Vc-Vr). Is solved.

Also, in the pixel sensor for the CMOS image sensor, a light receiving section for taking in light of the current frame and storing signal charges corresponding to the light amount, and a light shielding section for holding signal charges of the previous frame are provided. Means for transferring the signal charges accumulated in the light receiving section to the light shielding section, and means for resetting the signal charges held in the light shielding section.

In the signal readout circuit of the pixel sensor for the CMOS image sensor, a current frame potential storage for storing a signal potential Vc of a signal charge corresponding to the amount of light of the current frame stored in the light receiving section of the pixel sensor. Means, a previous frame potential storing means for storing a signal potential Vp due to a signal charge of a previous frame transferred to the light shielding unit, and a signal potential V of the light shielding unit after the reset.
reset potential storage means for storing r, and a difference (Vc-Vp) between the storage value Vc of the current frame potential storage means and the storage value Vp of the previous frame potential storage means, or the storage value Vc, depending on selection. Means for outputting a difference (Vc-Vr) of the storage value Vr of said reset potential storage means.

In a digital still camera capable of capturing a moving image, the CMOS image sensor and the first frame and the periodic frame for capturing a moving image are transmitted to the CMO.
Means for creating the absolute value of the S image sensor output;
Means for creating an intermediate frame based on the inter-frame difference.

In a digital video camera requiring motion detection, the CMOS image sensor and the CMO
A motion detecting means for calculating a motion vector in the screen based on the inter-frame difference of the S image sensor output.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In circuit design and layout design, general conditions required for a pixel sensor as a unit of an area sensor are as follows. (1) To increase the quantum efficiency and the aperture ratio which is an important factor thereof. (2) Random noise, which is particularly problematic in CMOS, can be reduced. (3) Since a large number are arranged in a two-dimensional array, the size is reduced as much as possible. (4) Therefore, a single well and a single transistor type are used. (5) Minimize the number of extra elements such as transistors. (6) The number of wirings to the pixel sensor is reduced as much as possible. (7) Since the irregular arrangement causes spatial distortion, the light receiving units of each pixel sensor are arranged in a layout structure in which the light receiving units of each pixel sensor are arranged at equal intervals in the upper, lower, left, and right directions except for the periphery of the array.

The conditions required for the pixel sensor to output the difference from the previous frame are as follows. (8) The signal charge of the previous frame is held. (9) The signal charge of the pixel sensor not selected by reading or the like is securely held until selected, so that it is not affected by an address selection signal, a reset signal, or the like. (10) In an application such as a digital camera that performs high-speed continuous shooting (continuous shooting) using a shutter, the charges in the light receiving units (photogates and photodiodes) can be reset all at once.

FIG. 5 shows a configuration and a potential image of the photodiode type pixel sensor 10 according to the first embodiment of the present invention satisfying the above conditions.

In the present embodiment, in addition to the conventional light receiving section 12 for taking in the light of the previous frame and accumulating the signal charge corresponding to the amount of light, for example, a metal for holding the signal charge of the previous frame is used. It is characterized by having a light-shielding portion 14 which is shielded by a light-shielding body 16 realized by a wiring layer, an optical light-shielding film or the like.

In the figure, B is the base charge, C is the current charge, and P is the remaining transfer charge proportional to the previous charge.

FIG. 6 shows a pixel sensor according to a second embodiment of the present invention which is applied to a pixel sensor of the same photogate type as that of the conventional example shown in FIG. 1. The transfer signal TX includes a ground GND and a power supply. It is kept at an appropriate potential between the voltage VDD.

In each of the embodiments shown in FIGS. 5 and 6, the pixel sensor is constituted by an NMOS transistor using a P well, but similarly, the pixel sensor can be constituted by a PMOS transistor using an N well. Is also self-evident.

Hereinafter, a specific description will be given taking the case of the photodiode type pixel sensor shown in FIGS. 5 and 6 as an example.

First, the peripheral circuit supplies a control signal (photodiode (PD) reset signal PDR,
Photogate (PG) reset signal PGR, PG control signal PG, transfer signal TX, FD reset signal FD
R, a pixel sensor selection signal X, etc.) and a read circuit 20 as shown in FIG. 7 for reading the signal potential of the pixel sensor output PO.
FD (T
There are (n +) reset noise between X and FDR, 1 / f noise of the transistor MIN that outputs the signal potential of the signal detection node by the source follower, and dark current. The random noise of the read circuit 20 includes reset noise of the capacitors CC, CP, and CR of the sample and hold circuit, and the amplifier A
There are C, AP, AR white noise and 1 / f noise. The fixed pattern noise is caused by variations between columns due to parallel output for each column, and is mainly caused by offset variations of the amplifier of the readout circuit.

In order to reduce random noise and fixed pattern noise of the pixel sensor and the readout circuit, correlated double sampling described in the above-mentioned English literature is effective.

Therefore, in the read circuit of FIG. 7, the switch SHC is turned on, the signal potential Vc including noise of the current frame is set to the capacitor CC, the switch SHP is turned on, and the signal potential Vp including noise of the previous frame is set to The switch SHR is turned on in the capacitor CP, and the reset potential Vr including noise is held in the capacitor CR. Then, the switch SWR is turned on, and the absolute value (V
c−Vr), the switch SWP is turned on, and the difference (Vc−Vp) from the previous frame in which the noise component is reduced is measured.
However, in the case of the difference from the previous frame, there is a time lag, so that the reset noise and 1 / f noise of the pixel sensor and the white noise and 1 / f noise of the readout circuit cannot be completely reduced.

Hereinafter, a method of measuring a difference from a previous frame and an absolute value when light is captured using a shutter in the photodiode system will be described step by step.

(1) Light Capture The shutter (not shown) disposed above the sensor is temporarily opened to capture light as shown in FIG. 5 and accumulate the current charge C. (2) Selection of Pixel Sensor The pixel selection signal X is set to “H”. (3) Reading out the signal potential of the previous frame The switch SHP is temporarily turned on, and the signal potential is stored in the capacitor CP. (4) Reset of FD As shown in FIG. 8, the FD reset signal FDR is temporarily set to “H”, the current charge P remaining in the FD is released to the power supply, and reset. (5) Reading of reset potential The switch SHR is temporarily turned on, and the signal potential is stored in the capacitor CR. (6) Movement of Signal Potential As shown in FIG. 9, the transfer signal TX is temporarily set to “H”, and the signal charge C of the photodiode is moved to the FD. (7) Reading the signal potential of the current frame The switch SHC is temporarily turned on, and the signal potential of the current frame is stored in the capacitor CC. (8) Measurement of Absolute Value and Difference from Previous Frame The absolute value measures the output VO (= Vc−Vr) of the readout circuit 20 when only the switch SWR is temporarily turned on.
On the other hand, the difference from the previous frame is determined by the output VO (= V) of the readout circuit 20 when only the switch SWP is temporarily turned on.
c-Vp) is measured. (9) Photodiode Reset As shown in FIG. 10, the PD reset signal PDR is temporarily set to “H” to reset the photodiode. (10) Non-selection of pixel sensor The pixel sensor selection signal X is set to “L”, and another pixel sensor is selected.

Here, the order of the procedures (8), (9) and (10) is not important, and can be interchanged for the convenience of the whole system.

As described as a delta difference sampling DDS in the above-mentioned English document, a switch STX is provided between the capacitors CC and CR as shown by a broken line in FIG. 7 to reduce the reset noise (offset) of the capacitors. It is also possible to reduce the absolute value so that the absolute value can be measured more accurately. Also, a switch is provided between the capacitors CC and CP,
It is also possible to reduce the capacitance offset. These procedures can be performed between (2) and (3).

When the shutter is not used, light is always taken in, so that the procedure (1) is unnecessary. In the case where a shutter is used, it is preferable that the reset for removing the effect of the dark current of the photodiode in step (9) be performed on all the pixel sensors at the same time immediately before the shutter is opened.

When the difference from the previous frame is not required, the procedure (3) can be skipped. In this case, part of the procedure (8) becomes unnecessary.

If the absolute value is not required, step (5) can be skipped. Also in this case, part of the procedure (8) becomes unnecessary.

In the case of a photogate type pixel sensor, measurement can be performed in substantially the same procedure, but the procedure (6) is different.

That is, in the case of the photogate system, when the signal charge is moved in the procedure (6), as shown in FIG.
The PG control signal PG is temporarily set to “L”, and the signal charge of the photogate is moved to the FD.

In the case of the photogate method, the procedure (9)
Resets the photogate PG, but the signal charge is F
Since it moves to D, as shown in FIG. 12, a transistor using PGR as a gate signal can be omitted.

Next, the peripheral control circuit will be described with reference to FIG.

The pixel sensor 10 has a large number (for example, 352 columns × 288 rows, 1280 columns × 96) in a two-dimensional array.
0 rows, etc.). Around the readout circuit 20,
A peripheral control circuit for driving a control signal of the pixel sensor 10 is provided. In the raster scan, pixels are sequentially selected and read from the pixel array in the upper row. Normally, one readout circuit 20 is arranged for each column, the output VO of the readout circuit is selected in the horizontal direction, and the programmable gain amplifier PGA24 corrects the difference between the gains for each pixel and the overall gain. The digital signal is converted by the D converter 26.

There are a variety of modifications of the configuration. For example, a block readout for every 8 bits in which a switch is provided for the output of the pixel sensor, a configuration in which the PGA 24 has an adder in front of the output VO of the readout circuit, Horizontal selector 22
, Or a method using a single-slope column parallel AD conversion array.

FIG. 13 shows an example of a configuration according to the present invention in which m rows × n columns of pixel sensors are arranged. This is a configuration example of the photodiode system, but the same applies to the photogate system.

In this example, the output of the row decoder 30 selects one row of pixel sensors and becomes a pixel selection signal X. Pixel sensor control signals PDR, TX,
The FDR is ANDed with the output of the row decoder 30. However, in the case of the photogate method, of the control signal of the pixel sensor, the logical product of the PG and the output of the row decoder is negated.

The row decoder 30 and the column decoder 32 may decode a counter output or may be a shift register that circulates one bit.

The timing / control circuit 34 controls the entire system.

Normally, the digital data subjected to A / D conversion is processed by color interpolation, color correction and the like, and then temporarily stored in a frame memory, while being used for motion detection using the frame memory of the previous frame. Alternatively, data is compressed and transferred based on the JPEG standard, which is a general standard for still image compression, and the MPEG standard, which is a general standard for moving image compression. For example, data of 8 rows × 8 columns is subjected to DCT, quantization, variable length coding, and packing, and is stored in a memory card or transmitted to another electronic device.

Next, a digital still camera according to a third embodiment of the present invention, which can capture moving images, will be described in detail.

In such a digital still camera, since a still image is mainly handled, data compression is usually performed according to the JPEG standard. In the case of an application that stores a short-time moving image and treats some of the scenes as still images, if all the moving images of 30 frames / second are data-compressed according to the JPEG standard, the amount of data becomes enormous, which is practical. Not. On the other hand, with the MPEG standard suitable for moving images, the quality of still images cannot be tolerated, and the circuit scale becomes large.
Power consumption also increases.

On the other hand, according to the present invention, a moving image can be captured only by JPEG without using a frame memory. In addition, it is possible to output some scenes of a moving image with still image quality. Furthermore, the data volume can be reduced,
You can record video for a longer time. In addition, for a block with a small amount of motion, a two-dimensional DCT operation is performed on the difference, so that the amount of data finally stored / transferred can be reduced. Also, JPEG and MPEG can be used in combination.

Specifically, the following is performed. (1) The first frame of a moving image and the periodic frame are data-compressed according to the JPEG standard and transferred (referred to as intra-frame compressed data). (2) In the middle frame, the difference from the previous frame is JPE
The data is compressed according to the G standard and transferred (referred to as differential compressed data). (3) On the reproduction side, the in-frame compressed data is decompressed, and based on the decompressed data, the subsequent differentially compressed data is decompressed and added. This operation is continued until the next intra-frame compressed data appears. (4) When some scenes of a moving image are used with still image quality, intra-frame compressed data is used.

FIG. 14 shows a configuration example of the present embodiment. In the figure, 40 is a CMOS image sensor according to the present invention, 42 is a signal processing / control unit, 44 is a mechanical system including a lens motor (not shown) for driving the lens 38,
46 is a liquid crystal display (LCD), 48 is JPE
An encoding / decoding unit according to the G standard, 50 is a memory card /
It is a data input / output unit.

In the present embodiment, a frame memory is required on the reproduction side, but since it is a personal computer or a printing machine, the circuit scale and power consumption do not matter as much as a battery-driven digital still camera.

Next, a digital video camera according to a fourth embodiment of the present invention will be described in detail.

In the digital video camera, since recording is performed for a long time, data compression according to the MPEG standard is performed. This M
In the PEG standard, motion detection is a bottleneck in circuit scale, power consumption, and operation speed. Normally, a difference from the previous frame is calculated, a motion vector in the screen is calculated, and if the whole is moving, camera shake is corrected.

When the present invention is applied, since the CMOS image sensor itself directly outputs the difference from the previous frame, a frame memory for motion detection is not required, the amount of calculation is small, and the circuit scale is small. In addition, since the signal potential of the previous frame remains held in each pixel sensor at the time of measurement in the previous frame, an increase in power consumption is small.

FIG. 15 shows a configuration example of this embodiment. In the figure, 52 is a baseband signal processing unit, 54 is a control unit, 56 is an encoding / decoding unit according to the MPEG standard including two working memories 57A and 57B, and 58 is
A frame memory used for predictive encoding / decoding by MPEG, an RF signal processing unit 60, and a video cassette 62.

The system operation and elements common to the above embodiment are as follows. (1) Switching and control of outputting an absolute value from the pixel sensor, outputting a difference from the previous frame, or outputting an absolute value after the difference are performed. (2) When a shutter is used, the light receiving unit is reset. (3) Instead of the frame memory of the previous frame and the current frame, a working memory for performing a two-dimensional DCT operation of an absolute value or a difference between the previous frame and the like is provided. In the case of raster scanning, usually two sets of eight lines are provided. While one working memory is used for the DCT operation, the data of the pixel being read is stored in the other working memory and used alternately.

[0070]

According to the present invention, since the difference from the previous frame can be directly output, the data amount can be reduced without lowering the image quality. Also, a plurality of large-capacity frame memories can be eliminated except when the frame memory is used for the MPEG standard.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a conventional example of a CMOS image sensor and its readout circuit.

FIG. 2 is a timing chart showing the operation of the conventional example.

FIG. 3 is a diagram showing a potential image for explaining the operation of the conventional example.

FIG. 4 is a circuit diagram showing a configuration of another conventional sensor unit and a readout circuit of a CMOS image sensor.

FIG. 5 is a diagram showing a photodiode type pixel sensor according to the first embodiment of the present invention;

FIG. 6 is a diagram showing a photogate type pixel sensor according to a second embodiment of the present invention;

FIG. 7 is a circuit diagram showing an example of a read circuit according to the first embodiment;

FIG. 8 is a diagram showing a potential image in an FD reset state in the first embodiment.

FIG. 9 is a diagram showing a potential image in a signal charge transfer state.

FIG. 10 is a diagram showing a potential image in a photodiode reset state.

FIG. 11 is a diagram showing a potential image in a signal charge transfer state in the second embodiment.

FIG. 12 is a diagram showing a potential image in a photogate reset state.

FIG. 13 is a block diagram showing an example of a pixel sensor array and peripheral circuits when the first embodiment is used.

FIG. 14 is a block diagram showing an overall configuration of a digital still camera capable of capturing a moving image according to a third embodiment of the present invention.

FIG. 15 is a block diagram showing an overall configuration of a digital video camera according to a fourth embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Pixel sensor 12 ... Light receiving part 14 ... Light shielding part 16 ... Light shielding body 20 ... Readout circuit 40 ... CMOS image sensor

Claims (5)

[Claims] 1. A pixel sensor capable of holding a signal charge of a previous frame, and a signal potential V of a previous frame of a selected pixel sensor.
p, a sample-and-hold circuit for holding the reset potential Vr after resetting the detection node, and the signal potential Vc of the current frame, and a means for outputting an inter-frame difference by (Vc-Vp) and an absolute value by (Vc-Vr) And a CMOS image sensor comprising: 2. A light receiving section for receiving light of a current frame and storing signal charges corresponding to the amount of light, a light shielding section for holding signal charges of a previous frame, and a signal charge stored in the light receiving section. A pixel sensor for a CMOS image sensor, comprising: means for transferring a signal charge to the light-shielding portion; and means for resetting signal charges held in the light-shielding portion. 3. A current frame potential storage means for storing a signal potential Vc of a signal charge corresponding to a light amount of a current frame, stored in the light receiving section of the pixel sensor according to claim 2, and transferred to the light shielding section. A previous frame potential storing means for storing the signal potential Vp by the signal charges of the previous frame, a reset potential storing means for storing the signal potential Vr of the light-shielding section after the reset, and a current frame potential storing means by selection. Or the difference (Vc−Vp) between the storage value Vc of the previous frame and the storage value Vp of the previous frame potential storage means, or the storage value Vc
And the difference (Vc−
Vr) outputting means for outputting a pixel signal for a CMOS image sensor. 4. A digital still camera capable of capturing a moving image, wherein the CMOS image sensor according to claim 1 and a first frame and a periodic frame for capturing a moving image are created based on an absolute value of the output of the CMOS image sensor. A digital still camera using a CMOS image sensor, comprising: means for generating an intermediate frame based on the difference between the frames. 5. A digital video camera requiring motion detection, wherein: the CMOS image sensor according to claim 1; and a motion detecting means for calculating a motion vector in a screen based on an inter-frame difference of an output of the CMOS image sensor. A digital video camera using a CMOS image sensor, comprising: