JP2000243834A - Semiconductor device, its manufacture and electrooptic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the increase in the film thickness of an insulating film, to lessen the discharge of an injurious material at the time of the manufacture of a semiconductor device and to make it possible to reduce a power consumption by a method wherein after an aperture is formed in a polysilazane film formed on a wiring layer, this polysilazane film is formed into the insulating film containing a silicon oxide film as its main component. SOLUTION: The formation of an insulating film using a polysilazane film and an aperture formed in the insulating film is applied to the formation of a first interlayer film 22, a drain electrode aperture 40 and a source electrode aperture 50 and is applied to the formation of a second layer insulating film 33 and a pixel electrode aperture 30. In the forming process of the insulating film and the aperture, first, the photosensitive polysilazane film is applied on a wiring layer by a spin method and after the polysilazane film is prebaked, the aperture is exposed on the polysilazane film and thereafter, the polysilazane film is dipped into an alkaline solution to open the polysilazane film. Then, the polysilazane film is annealed for three minutes at 350 deg.C in a steam-containing atmosphere, whereby the polysilazane film is denatured to obtain the insulating film containing a silicon oxide film as its main component and the aperture. Thereby, the increase in the film thickness of the insulating film is easy, the insulating film is excellent in flatness, the discharge of an injurious material at the time of the manufacture of a semiconductor device is little, a power consumption is reduced and the effect to the environment is lessened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more specifically, to a semiconductor device including a plurality of wiring layers and insulating layers and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Generally, when a semiconductor device is formed by laminating a plurality of wiring layers, an insulating layer is formed between the plurality of overlapping wiring layers so as to prevent a short circuit between the wiring layers. In many cases, an opening is formed by a process such as etching in order to obtain electrical conduction.

As an example of a case where a plurality of wirings and a plurality of insulating layers are stacked on a semiconductor device and an opening is formed in the insulating layer, a thin-film transistor type active matrix having a staggered structure formed on an insulating substrate is described. An example at the time of manufacturing a substrate or the like will be described below.

First, as a first step, a semiconductor layer to be a source region, a channel region and a drain region of a TFT is formed on a substrate, and a gate insulating film is formed thereon.

Next, as a second step, a gate electrode is laminated with a metal above the channel region on the gate insulating film.

Further, as a third step, T
A first interlayer insulating layer is laminated on the FT region, and contact holes are formed by opening portions of the first interlayer insulating layer and the gate insulating film corresponding to the source region and the drain region. A source electrode and a drain electrode are formed on the first interlayer insulating layer so as to be connected.

[0007] Then, as a fourth step, a second insulating layer is formed on the entire substrate including the open short-circuit line and the source and drain electrodes.

Next, as a fifth step, an opening is formed in the second interlayer insulating layer on the drain electrode by photolithography and etching.

Then, as a sixth step, a pixel electrode is formed on the second interlayer insulating layer so as to be connected to the opening on the drain electrode, thereby completing the TFT.

As described above, one semiconductor layer, three wirings, and three interlayer insulating films are formed on the active matrix substrate, and openings are respectively formed in the interlayer insulating films.

The characteristics required in common for the above-mentioned plurality of interlayer insulating films include excellent insulating properties, step coverage with respect to the steps of the lower wiring layer, and processability with which the opening can be accurately formed when the opening is formed. And heat resistance that can withstand a rise in temperature during manufacturing, and chemical resistance that is not affected by the chemicals used in wiring the upper layer.

As a method of forming an insulating film satisfying these requirements, a method of forming a silicon oxide film or a silicon nitride film by a CVD (Chemical Vapor Deposition) method is generally used. Specifically, for example, TEOS (Tetra Ethyl Ort
hoSilicate) is used as a raw material, and a 5000-Å-thick silicon oxide film is deposited by a plasma CVD method.

In order to open the insulating film thus obtained, a resist pattern is formed on the insulating film by a photolithography technique, and the resist pattern is removed with a stripper after opening by wet etching or dry etching. It is necessary to perform such a step.

[0014]

However, especially in the first and second interlayer insulating films, there is a demand to increase the thickness of the lower wiring layer in order to reduce the bus line resistance. When a semiconductor device is used as a liquid crystal device, there is a demand to flatten a step caused by a lower wiring with an insulating film so that the alignment of the liquid crystal is not disturbed by the step.

In recent years, there has been a strong demand for reducing the capacitance between wirings in order to reduce the power consumption of semiconductor devices. For this purpose, it is necessary to lower the dielectric constant and increase the thickness of the interlayer insulating film.
In many cases, it is inconsistent with workability, etc.Thickening increases the processing time when forming a film by the CVD method, not only increases the manufacturing cost, but also makes it difficult to etch at the time of opening,
Contradicts workability.

Further, a large amount of a material such as TEOS or silane gas as a raw material, a material such as hydrofluoric acid or freon gas at the time of etching, and a material such as monoethanolamine at the time of peeling is consumed in the formation of the film by the CVD method and the opening thereof.
Not only must safety be fully considered, but damage to the environment due to waste liquids and exhaust gas must also be significant. In addition, since a CVD device needs to generate a reaction at high temperature or plasma, a large amount of power is consumed especially when forming a film on an active matrix substrate using a large-sized glass substrate, and from this aspect, the environment is also reduced. The negative effect of is large.

As one solution to this problem, for example, an organic acrylic resin having photosensitivity is applied by a spin method or the like,
A method of opening by photolithography has also been devised. The organic film formed in this way has high flattening properties and has the advantage that it can be formed into a relatively thick film (up to 1 μm), but its chemical resistance, heat resistance, and processability are low.
Since it is inferior to the inorganic film formed by the method, it is currently applied only to the second interlayer insulating film. In the future, as higher definition and lower power consumption progress, the workability etc. It is expected to be limited in terms of aspects.

Another method is disclosed in Japanese Patent Application Laid-Open No. 7-456.
05 discloses a method using a silicon oxide film in which polysilazane is modified as an interlayer insulating film. In this method, polysilazane is applied by a spin method or the like, and the obtained polysilazane is heat-treated, subsequently immersed in hot water, and then heat-treated at a higher temperature to transform into a silicon oxide film. Although this method has an advantage that a relatively thick film having excellent chemical resistance and heat resistance and excellent in flatness can be easily obtained, there is a problem in workability at the time of thickening the film and an environment due to etching and peeling. From the viewpoint of the influence, it has the same problem as the film obtained by the CVD method.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object the problem of being excellent in insulating properties, chemical resistance, and workability, yet being easy to make a thick film, excellent in flatness, and Providing an insulating film formation method and an opening method with minimal impact on the environment in order to reduce the amount of harmful substances emitted during production and reduce power consumption, resulting in low power consumption, good yield, and low production cost. An object of the present invention is to provide a method for manufacturing a semiconductor device, a semiconductor device manufactured by the method, and a liquid crystal display device using the semiconductor device.

[0020]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device having a plurality of insulating films and a plurality of wiring layers on a substrate. Forming a polysilazane film on a first wiring layer of the plurality of wiring layers, providing an opening in the polysilazane film, and forming a silicon oxide film on the polysilazane film in which the opening is formed. At least a step of forming an insulating film as a main component.
The polysilazane here is a general term for a substance indicating perhydropolysilazane or a composition containing the same. As described above, by directly opening the polysilazane film, which is easier to process than silicon oxide, it is possible to achieve the above-described problem of workability and a reduction in etching and stripping liquid.

In the method of manufacturing a semiconductor device according to the present invention, the opening may be formed by exposing a portion corresponding to the opening of the polysilazane film, and then removing the exposed portion using a chemical solution. It is characterized by. More specifically, polysilazane to which a component that cuts off a part of the bond of perhydropolysilazane by light irradiation is added (hereinafter, such polysilazane is referred to as photosensitive polysilazane) is applied. After exposing the photosensitive polysilazane to a pattern by a photolithography technique, the polysilazane film is exposed at an alkali solution such as a TMAH solution to remove the polysilazane film at the site where the bond of the perhydropolysilazane has been cut off. Is performed. This can provide a method for easily processing the polysilazane film. In addition, the present method does not require the use of a photoresist, so that the use of a photoresist and a stripping solution can be eliminated as compared with a case where an insulating film formed by a CVD method is opened. Impact on the environment can be reduced. Further, since the process of etching is omitted as compared with the case of performing two-stage processing of resist patterning and etching, there is also an effect that processing accuracy is improved accordingly.

Further, in the method of manufacturing a semiconductor device according to the present invention,
In the method for forming a polysilazane film, a spin coating method is used. This is a method of applying a polysilazane film uniformly by centrifugal force by spinning the substrate after dropping polysilazane on the substrate, and then applying the polysilazane film as a relatively thick film and flattening the lower step. enable. Since such a flattened shape does not change even after the polysilazane modification, a film mainly containing a flattened silicon oxide film is obtained as a result.

Further, in the method of manufacturing a semiconductor device according to the present invention,
The substrate on which the polysilazane film is formed is placed in an atmosphere containing water vapor, and the polysilazane film is an insulating film containing the silicon oxide film as a main component. In particular, in the method for forming a polysilazane film, a method of forming a polysilazane film in a water vapor atmosphere is preferable.
It is characterized by exposing at a temperature of 0 ° C. or more for about 1 hour or more. Thus, the opened polysilazane film can be easily modified into a film containing silicon oxide as a main component. In general, it is essential that water is interposed in the modification of polysilazane, but this method has a merit that it requires only one treatment as compared with a treatment method in which heat treatment is performed after immersion in hot water, for example.
It also has the advantage that watermarking when immersed in boiling water can be prevented.

Further, in the method of manufacturing a semiconductor device according to the present invention,
Forming the first wiring layer and one of the wiring layers formed above an insulating film mainly composed of the silicon oxide film formed on the first wiring layer in the opening; And electrically connected through. Accordingly, a complicated circuit such as a bus line drive signal circuit on an active matrix substrate, which is an example of a semiconductor device, can be wired in a multilayer manner. In addition, since the insulating film obtained by this method has silicon oxide as a main component and has excellent chemical resistance and heat resistance, there are few restrictions on the material of the upper layer, the forming method, and the etching method at the time of patterning. It has the advantage that.

Further, in the method of manufacturing a semiconductor device according to the present invention,
The first wiring layer is a wiring mainly composed of aluminum, or a multilayer wiring including a layer mainly composed of aluminum,
For example, 5000 Å of Al is formed, and then T
It is characterized by using a film in which i is formed to 500 angstroms. Accordingly, in addition to the low specific resistance, which is an advantage of the aluminum main component material, the interlayer insulating film has a flattening property, so that it can be made thicker without adversely affecting the upper wiring. The following can be realized. Also,
Because the polysilazane-modified film has extremely excellent step coverage properties, hillocks from aluminum
Can be effectively prevented from being caused by an interlayer short circuit. This is effective not only for normal aluminum hillocks in the upward direction but also for side hillocks in the horizontal direction which cannot be prevented by providing a cap layer on the wiring. Further, the formation and modification of the polysilazane film do not use a chemical solution that invades aluminum, such as a strong acid, and does not require high heat equal to or higher than the melting point of aluminum. Therefore, there is no fear that the lower aluminum layer is eroded or melted.

Further, in the method for manufacturing a semiconductor device according to the present invention,
Forming at least a step of forming a gate bus line connected to the thin film transistor, a step of forming a source bus line and a drain electrode connected to the thin film transistor, and a step of forming a polysilazane film on the gate bus line. Features. Accordingly, the active matrix substrate has low power consumption because the short-circuit failure between the source bus line and the gate bus line is small, the disconnection due to the step of the source line is small, and the capacity between the source bus line and the gate bus line is small. Can be manufactured.

The method may further include a step of forming a semiconductor thin film to be a channel layer of the thin film transistor in a step prior to the step of forming the first wiring layer, wherein the semiconductor thin film is formed before the step of forming the first wiring layer. A step of forming a gate insulating film of the thin film transistor after the step of forming the semiconductor thin film.

Further, in the method of manufacturing a semiconductor device according to the present invention,
A step of providing an opening in the gate insulating film, wherein the opening is opened before forming the polysilazane film. Since the gate insulating film is generally thinner than the interlayer insulating film, the opening is relatively easy and the processing accuracy is high. As described above, since the processing accuracy of the polysilazane film opening is higher than that of the opening to the interlayer insulating film manufactured by the CVD method, the accuracy of the contact hole to the semiconductor layer of the source bus line or the drain electrode is high in this method. Has the advantage of becoming

Further, in the method of manufacturing a semiconductor device according to the present invention,
A part of the first wiring layer is electrically connected to the semiconductor layer through the opening formed in the gate insulating film. This makes it possible to perform wiring of a complicated circuit such as a C-MOS circuit in multiple layers. Further, in the method for manufacturing a semiconductor device of the present invention, the lower wiring in that case is a wiring having a layer containing any one of Ti, Cr, Mo, and Ta as a main component in the lowermost layer. I do. Thereby, it is possible to prevent a defect such as disconnection due to a void from occurring at the time of contact with the semiconductor layer.

Further, in the method for manufacturing a semiconductor device according to the present invention,
Forming an opening in the gate insulating film, wherein the opening is formed after the step of forming the polysilazane film into an insulating film containing silicon oxide as a main component and forming a wiring formed above the insulating film. It is characterized in that it is formed before the step of performing. Further, in the method for manufacturing a semiconductor device of the present invention, the opening of the gate insulating film is etched using a film containing silicon oxide as a main component obtained by modifying the polysilazane film as a mask. . Thus, the opening of the gate insulating film can be formed in a self-aligned manner with respect to the opening of the film mainly composed of the silicon oxide film obtained by modifying the polysilazane film. In general, even when the gate insulating film and the film containing a silicon oxide film as a main component obtained by modifying the polysilazane film have the same components or a sufficient etching rate ratio cannot be obtained, the gate insulating film is generally used. Is 500 to 1500 angstroms, and the interlayer insulating film is 5000 angstroms or more. Further, in the method of manufacturing a semiconductor device of the present invention, the upper wiring in that case is a wiring having a layer containing any one of Ti, Cr, Mo, and Ta as a main component in the lowermost layer. I do. Thereby, it is possible to prevent a defect such as disconnection due to a void from occurring at the time of contact between the upper wiring and the semiconductor layer.

Further, in the method of manufacturing a semiconductor device according to the present invention,
The semiconductor device includes a thin film transistor, and a wiring including a pixel electrode is formed when the upper wiring is formed. As a result, the unevenness of the pixel electrode portion due to the step of the bus line is flattened and reduced, and therefore, when a liquid crystal display device is manufactured using a semiconductor device manufactured by the manufacturing method of the present invention, alignment defects of the liquid crystal are reduced. You. Further, since the electric capacity of the source bus line is small, a semiconductor device which is an active matrix substrate device with low power consumption can be manufactured.

Further, since the semiconductor device of the present invention is formed by the above-described method of manufacturing a semiconductor device, the semiconductor device has a feature of low power consumption, a low manufacturing cost, and an influence on an environment at the time of manufacturing. Is reduced.

Further, since the liquid crystal display device of the present invention is formed by the above-described method for manufacturing a semiconductor device, it consumes low power and therefore has a long battery driving time when mounted on a portable information terminal, for example. It has the advantage that it has the advantage of being time consuming, has low manufacturing costs, and has a reduced impact on the environment during manufacturing.

[0034]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. The embodiment described below is an active matrix type liquid crystal display device as an active matrix substrate or the like on which a staggered thin film transistor is formed.

The configuration of an electro-optical device using the thin film transistor manufactured according to the present invention will be described below.

First, an overall configuration of a liquid crystal display device as an electro-optical device will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view of the liquid crystal display device of the embodiment, and FIG. 2 is a schematic plan view of an active matrix substrate.

As shown in FIG. 1, the liquid crystal display device 1 has an active matrix substrate 100 formed on an insulating substrate 10 made of a non-alkali glass substrate, a quartz glass substrate or the like.
And the counter substrate 101 also formed on the insulating substrate 110
Are adhered to each other with an appropriate gap by a sealing resin 111, and the liquid crystal layer 102 is injected between the substrates.
On the opposite substrate 101, a pigment dispersion resist 108 for color display, a black matrix 109 made of Cr for preventing light leakage, an electrode 112 formed on the opposite substrate made of ITO (Indium Tin Oxcide), and the like are arranged. .
Further, the active matrix substrate 100 and the opposing substrate 10
1, a polarizing plate and a retardation plate may be attached according to the mode of the liquid crystal layer 102 and combined with a backlight device according to the application, so that the display device can be used as a display device.

As shown in FIGS. 1 and 2, on the active matrix substrate 100, a plurality of pixel electrodes 90 and an active element 107 composed of a thin film transistor for switching the plurality of pixel electrodes are arranged in a matrix. Further, a plurality of gate bus lines 105 and a plurality of source bus lines 106 are arranged so as to be orthogonal to each other, and are connected to thin film transistors (hereinafter, referred to as TFTs) 107, respectively. Further, a scanning line driving circuit 103 is connected to the gate bus line 105, and a data driving circuit 104 is connected to the source bus line 106, so that a driving signal is input to each of them. In this drive circuit, an integrated circuit may be separately connected to the active matrix substrate 100 on a glass substrate through an anisotropic conductive paste or TAB tape, or the drive circuit may be formed directly on the glass substrate.

Next, the TFT formed in the pixel portion with reference to FIG.
107 will be described. FIG. 3 is an enlarged plan view of one of the TFTs 107 and the pixel electrodes 90 arranged in a matrix in FIG. The thin film transistor 107 includes a semiconductor layer 80, a gate electrode 60 connected to the gate bus line 105, and a drain electrode 70 connected to the semiconductor layer 80 through the contact hole 40. The source bus line 106 is connected to the semiconductor layer 80 through the contact hole 50, and the pixel electrode 90 is connected to the drain electrode 70 through the contact hole 30.

Next, an embodiment of a manufacturing method according to the present invention for manufacturing the active matrix substrate 100 will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view taken along line AA ′ in FIG. 3 during each manufacturing process.

In manufacturing an active matrix substrate 100 as an example of a semiconductor device, first, FIG.
As shown in (a), for example, a CVD (Chemical Vapor) is formed on an insulating substrate 10 such as a non-alkali glass or quartz substrate.
A base film 20 is formed to a thickness of about 500 to 5,000 angstroms by a por deposition method, and 300 to 1500 is formed on the base film 20 by a low pressure CVD method, a normal pressure CVD method, a plasma CVD method, a sputtering method or the like.
A silicon film is formed to a thickness of about angstrom.
Further, for example, when the peripheral circuits are formed simultaneously on the substrate 10 and the mobility of the semiconductor layer is necessary,
The formed silicon film is crystallized by annealing or laser light irradiation in an atmosphere of 0 to 1200 ° C. to form a crystalline silicon layer.

Next, the formed silicon semiconductor layer is patterned using a photolithography process to form a semiconductor layer 80 for forming a TFT in a pixel portion in an island shape. Further, after patterning with a heat resistant resist on the semiconductor layer 80, 10 ^{14 to} 10 ¹⁶ ion / m ²
The semiconductor layer 80 is divided into the source / drain regions 82 and the channel regions 82 by removing the resist pattern after implanting ions such as B (boron) with a moderate dose. Further, SiN, SiO ₂ , T
The gate insulating film 21 of a ₂ 0 100 to formed of ₅ or the like of 2000 Å thick is formed by a plasma CVD method. This is shown in FIG.

Although the source / drain regions 81 are formed using a resist mask here, the source / drain regions may be formed by implanting in a self-aligned manner after the formation of the gate electrode. Alternatively, an n-type semiconductor region serving as a source / drain region may be directly formed and patterned. In some cases, a low-concentration impurity region may be formed between the source / drain portion 81 and the channel portion 82 to form a so-called LDD (Lightly Doped Drain) structure. Further, in the case of the drive circuit built-in type, if it is necessary to provide a p-channel thin film transistor to form a C-MOS circuit, additional 10 ¹⁴ to 10 10
A step of implanting ions such as P (phosphorus) at a dose of about ¹⁶ ions / m ² to form the p ⁺ region 27 may be provided.

Next, as shown in FIG. 4B, an opening is provided in the gate insulating film, and a gate electrode 60 and the like are formed. First, a resist is patterned on the formed gate insulating film 21 by a photolithography technique, and is then peeled off after etching with, for example, an HF solution to provide an opening in the gate insulating film 21. After that, Ti is added to 500 by a sputtering method or the like.
Angstrom, and a 4000 Angstrom film of Al thereon. This two-layer conductive film is patterned into a predetermined shape by photolithography, and each TFT
A gate electrode 60, a source lower electrode 61, a drain lower electrode 62, and a scanning line 105 are formed. here,
The reason why Ti is used in the lower layer as the wiring is to prevent contact failure with the source / drain portion 81, and the reason that Al is used in the upper layer is to lower the resistance of the gate bus line 105. Here, a high-melting metal film such as Ti may be further laminated on the gate electrode 60, the source lower electrode 61, the drain lower electrode 62, and the scanning line 105 to prevent hillocks. The upper Al may be patterned into a separate shape. Note that a structure in which a metal film containing Al as a main component is sandwiched between Ti metal films may be employed.

Next, as shown in FIG. 4C, the first interlayer film 22 and the drain electrode openings 40 on the first interlayer film are formed.
A source electrode opening 50 is formed. First, an appropriate amount of photosensitive polysilazane is dropped on the active matrix substrate 100, and the active matrix substrate 100 is
flattened by spinning at rpm, on average 500
A photosensitive polysilazane film of about 0 to 15000 angstroms is obtained. Further, this photosensitive polysilazane was added to 100
After pre-baking at about ° C to evaporate the solvent, the openings 40 and 50 are exposed by photolithography. Next, when the active matrix substrate 100 is immersed in an alkaline solution, for example, a 2% TMAH solution, only the polysilazane film in which the perhydropolysilazane bonds in the exposed openings 40 and 50 are broken is dissolved. Finally, after rinsing and drying, if annealing is performed at 350 ° C. for 3 hours in an atmosphere containing water vapor, the polysilazane film undergoes a hydrolysis reaction and is transformed into a film containing silicon oxide as a main component. At the same time, the source / drain section 81 is also activated.

Next, as shown in FIG. 4D, the source bus line 106, the drain electrode 70, the second interlayer insulating film 2
A pixel electrode opening 30 is formed on the third and second interlayer insulating films 23. First, a conductive film having a thickness of about 1000 to 10000 angstroms, for example, A
The source bus line 106 and the drain electrode 70 are formed by forming 1 and patterning it into a predetermined shape using a photolithography process. Next, FIG.
In the same manner as shown in (c), a photosensitive polysilazane is applied by a spin method, prebaked, exposed to an opening, immersed in an alkali solution to form an opening, and heated to 350 ° C. in an atmosphere containing water vapor at 350 ° C. Polysilazane is denatured by annealing for 2 hours to form second interlayer insulating film 2 containing silicon oxide as a main component.
The pixel electrode openings 30 on the third and second interlayer insulating films 23 are obtained.

Finally, as shown in FIG. 4E, a pixel electrode 90 is formed. That is, ITO (Indium Tin Oxi
After a transparent conductive film such as de) is formed to a thickness of about 1000 to 3000 angstroms by a sputter method or the like, a resist pattern is provided by a photolithography technique, and the resist pattern is peeled off after being immersed in, for example, an HCl solution using this as a mask. The active matrix substrate 100 is finally completed by patterning the pixel electrode 90 by using.

A polyimide film is applied to the active matrix substrate 100 thus obtained, and the orientation is adjusted by a rubbing method. Similarly, the counter substrate 101 on which the polyimide film is applied and oriented is bonded with a seal resin 111 while keeping a proper gap. In addition, the liquid crystal display device 1 is completed by injecting and sealing the liquid crystal layer 102.

In this embodiment, the source / drain lower electrodes are formed during the processing of the gate electrode. However, the gate insulating film is not opened before the processing of the gate electrode, and the gate insulating film is opened before the formation of the source bus line. No problem. in this case,
The opening of the gate insulating film can be formed by, for example, an HF solution without photolithography using the first interlayer film obtained by transforming photosensitive polysilazane as a mask. The first interlayer film is also etched by substantially the same amount as the gate insulating film, but originally the first interlayer film has a thickness of 5,000 Å or more and the gate insulating film has a thickness of 2,000 Å or less, and the first interlayer film remains at least 3,000 Å. Therefore, it does not matter. In addition, since the source bus line is in direct contact with the semiconductor layer, it is desirable to stack Ti or the like in the lower layer from the viewpoint of preventing void generation.

The liquid crystal display device as the electro-optical device as shown in FIG. 1 is formed by the above process.
FIG. 5 shows an electronic apparatus equipped with this liquid crystal display device.
This will be described with reference to FIG.

FIG. 5 is an external view showing an example of electronic equipment using the electro-optical device of the present invention.

FIG. 5A is a perspective view showing a mobile phone. 1000 denotes a mobile phone body, of which 100
Reference numeral 1 denotes a liquid crystal display unit using the electro-optical device of the present invention.

FIG. 5B is a diagram showing a wristwatch-type electronic device. 1100 is a perspective view showing the watch main body. 11
Reference numeral 01 denotes a liquid crystal display unit using the electro-optical device of the present invention. Since this liquid crystal panel has higher definition pixels than a conventional clock display unit, it can also display television images, and can realize a wristwatch type television.

FIG. 5C is a diagram showing a portable information processing device such as a word processor or a personal computer. 1200 denotes an information processing apparatus, 1202 denotes an input unit such as a keyboard, 120
Reference numeral 6 denotes a display unit using the electro-optical device of the present invention, and 1204 denotes an information processing apparatus main body. Since each electronic device is a battery-driven electronic device, the use of a reflective liquid crystal panel without a light source lamp can extend the battery life. Further, as in the present invention, since the peripheral circuit can be built into the panel substrate, the number of parts is greatly reduced, and the weight and weight are reduced.
Can be downsized.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a configuration of a liquid crystal display device.

FIG. 2 is a schematic plan view showing an active matrix substrate device.

FIG. 3 is a plan view of a thin film transistor and a pixel electrode forming one pixel in the active matrix substrate device.

FIG. 4 is a schematic cross-sectional view taken along line AA ′ in FIG. 3 showing an embodiment in each manufacturing process of the active matrix substrate.

FIG. 5 is a diagram illustrating an example of an electronic apparatus equipped with the electro-optical device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device 10 ... Insulating substrate 20 ... Base film 21 ... Gate insulating film 22 ... First interlayer insulating film 23 ... Second interlayer insulating film 30 ... Pixel electrode opening 40 ... Drain electrode opening 50 ... Source electrode opening Reference Signs List 60 gate electrode 61 source lower electrode 62 drain lower electrode 70 drain electrode 80 semiconductor layer 81 source / drain part 82 channel part 90 pixel electrode 100 active matrix substrate 101 counter substrate 102 liquid crystal layer 103 … Scanning line driving circuit 104… data line driving circuit 105… gate bus line 106… source bus line 107… thin film transistor 108… pigment dispersion resist 109… black matrix 110… insulating substrate 111… seal resin 112… counter substrate electrode

Continued on the front page F-term (reference) 2H090 HA04 HA05 HA08 HB03X HB12X HC05 HC09 HC10 HD03 LA01 LA04 2H092 JA25 JA40 JA44 JA46 JA47 JB24 JB58 KA12 KA24 KB04 KB22 KB25 MA05 MA07 MA15 MA25 NA19 NA28 PA12 5F033 HH07H20H01H21H JJ08 JJ18 JJ20 JJ21 JJ38 KK08 KK18 MM05 NN03 PP15 QQ09 QQ20 QQ37 QQ74 QQ76 RR27 SS22 SS27 VV04 VV06 VV15 XX33 5F058 AA05 AA06 AC03 AC07 AF04 AG01 AG10 AH01 AH02 FF03 FF02 FF03 FF02 FF03 GG24 GG44 GG45 GG47 HJ01 HJ04 HJ13 HJ23 HL03 HL04 HL11 HL23 NN02 NN04 NN23 NN27 NN36 NN40 PP03 PP10 QQ05 QQ10

Claims (20)

[Claims] In a method of manufacturing a semiconductor device having a plurality of insulating films and a plurality of wiring layers on a substrate, a polysilazane film is formed on a first wiring layer of the plurality of wiring layers. A process for providing an opening in the polysilazane film; and a step of converting the polysilazane film in which the opening is formed into an insulating film containing a silicon oxide film as a main component. Method. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the opening is formed by exposing a portion corresponding to the opening of the polysilazane film, and then removing the exposed portion using a chemical solution. A method for manufacturing a semiconductor device, comprising: 3. The method for manufacturing a semiconductor device according to claim 1, wherein said polysilazane is dropped on said substrate, and said substrate is spun. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate on which the polysilazane film is formed is disposed in an atmosphere containing water vapor, and the polysilazane film is formed on the silicon oxide film. A method for manufacturing a semiconductor device, comprising: forming an insulating film mainly composed of: 5. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is disposed in the atmosphere containing water vapor at a temperature of about 200 ° C. or more for about 1 hour or more. . 6. The method for manufacturing a semiconductor device according to claim 1, wherein said first wiring layer and said silicon oxide film formed on said first wiring layer are main components. A method of manufacturing a semiconductor device, comprising: electrically connecting one of the wiring layers formed above an insulating film to be formed through the opening. 7. The method of manufacturing a semiconductor device according to claim 1, wherein said first wiring layer is made of a metal containing aluminum as a main component. 8. The method of manufacturing a semiconductor device according to claim 1, wherein said first wiring layer is formed of a multilayer metal film containing at least one metal mainly composed of aluminum. Manufacturing method of a semiconductor device. 9. The method of manufacturing a semiconductor device according to claim 1, wherein a thin film transistor is formed on the substrate. 10. The method of manufacturing a semiconductor device according to claim 9, wherein a step of forming a gate bus line connected to the thin film transistor; a step of forming a source bus line and a drain electrode connected to the thin film transistor; Forming a polysilazane film on a gate bus line. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of forming a semiconductor thin film to be a channel layer of the thin film transistor in a step before the step of forming the first wiring layer, Forming a gate insulating film of the thin film transistor before the step of forming the first wiring layer and after the step of forming the semiconductor thin film. 12. The method for manufacturing a semiconductor device according to claim 11, further comprising a step of providing an opening in said gate insulating film, wherein said opening is opened before said polysilazane film is formed. Semiconductor device manufacturing method. 13. The method of manufacturing a semiconductor device according to claim 9, wherein a part of the first wiring layer is formed through the opening formed in the gate insulating film. A method for manufacturing a semiconductor device, wherein the semiconductor device is electrically connected to a layer. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the first wiring layer is a wiring mainly containing any of Ti, Cr, Mo, and Ta, A method of manufacturing a semiconductor device, characterized in that the wiring is a multilayer wiring in which a layer mainly containing either Mo or Ta is used as a lowermost layer. 15. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of providing an opening in said gate insulating film, wherein said opening is formed by insulating said polysilazane film containing silicon oxide as a main component. A method for manufacturing a semiconductor device, wherein the method is performed after the step of forming a film and before the step of forming a wiring formed above the insulating film. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the opening is mainly composed of the gate insulating film and the silicon oxide using an insulating film mainly composed of the silicon oxide as a mask. A method of manufacturing a semiconductor device, wherein an insulating film is etched by being simultaneously exposed to a liquid or a gas as an etchant. 17. The method for manufacturing a semiconductor device according to claim 15, wherein the wiring formed above the insulating film containing silicon oxide as a main component is any of Ti, Cr, Mo, and Ta. A method of manufacturing a semiconductor device, characterized in that the wiring is a wiring mainly containing Ti or a multilayer wiring in which a layer mainly containing any of Ti, Cr, Mo, and Ta is a lowermost layer. 18. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of forming a pixel electrode connected to the thin film transistor above the insulating film containing silicon oxide as a main component. A method for manufacturing a semiconductor device, comprising: 19. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1. Description: 20. An electro-optical device using a semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 9.