JP2000134040A - Fm demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a large demodulation output even when the frequency shift is small. SOLUTION: An FM demodulator has a delay means 4 that delays a received signal by a prescribed time, a multiplication means 5 that multiplies the received signal by a signal from the delay means 4, a filter that extracts a demodulation output from an output of the multiplication means 5, and a frequency detection means 3 that provides an output of a signal in accordance with the frequency of the received signal. The delay time of the delay means 4 is controlled with a signal from the frequency detection means 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an FM or FS
The present invention relates to an FM demodulator for demodulating a K-modulated signal.

[0002]

2. Description of the Related Art Quadrature detection and pulse count detection are often used in FM demodulators. FIG.
1 shows a configuration of a conventional FM demodulator. In FIG. 5, 1
Is an antenna, 2 is a receiver, 4 is delay means, 5 is multiplication means, and 6 is a low-pass filter. In the radio wave received by the antenna 1, only the desired signal is selectively amplified by the receiver 2. The receiver 2 converts the signal received by the antenna 1 into an intermediate frequency, and then removes and amplifies the interfering signal with a filter. The receiver 2 outputs a reception signal converted to the intermediate frequency. The intermediate frequency is, for example, 50 kHz. The received signal of the intermediate frequency output to the receiver 2 is delayed by the delay means 4 by a time corresponding to (×) × n periods of the intermediate frequency. Here, n is an odd number. Therefore, the received signal input to the multiplication means 5 and the signal from the delay means are orthogonal at the intermediate frequency. That is, the delay means 4 and the multiplication means 5 constitute a quadrature detection circuit. Then, an FM demodulated signal is generated at the output of the multiplying means 5. The low-pass filter 6 removes an intermediate frequency component and extracts only a demodulated signal.

[0003]

However, in the above-mentioned conventional FM demodulator, when n is small in the delay means 4, the demodulation level generated at the output of the multiplication means 5 has a very small value. Conversely, increasing n means increasing the delay time of the delay means 4, and it has been difficult to simply construct. Therefore, there is a problem that the demodulation level cannot be increased.

[0004]

In order to solve the above-mentioned problems, the present invention provides a delay means for delaying a reception signal for a predetermined time, a multiplication means for multiplying the reception signal by a signal from the delay means, and a multiplication means. A filter for extracting a demodulated output from the output of the means, and frequency detecting means for outputting a signal corresponding to the frequency of the received signal, wherein the signal from the frequency detecting means controls the delay time of the delay means. It is composed. The demodulation level can be increased by changing the delay time according to the frequency change.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a delay means for delaying a reception signal by a predetermined time, a multiplication means for multiplying the reception signal by a signal from the delay means, and a filter for extracting a demodulated output from an output of the multiplication means. And a frequency detecting means for outputting a signal corresponding to the frequency of the received signal, wherein the delay time of the delay means is controlled by a signal from the frequency detecting means. The demodulation level can be increased by changing the delay time according to the frequency change.

Further, an edge detecting means for detecting a rising or falling edge of the received signal, and a pulse signal generating means for generating a pulse signal having a predetermined pulse width in synchronization with the edge detected by the edge detecting means. A filter for extracting a demodulated output from the pulse signal, and frequency detecting means for outputting a signal corresponding to the frequency of the received signal, and a pulse generated by the pulse signal generating means with a signal from the frequency detecting means. It is configured to control the width. The demodulation level can be increased by changing the pulse width according to the frequency change.

Further, the pulse signal generating means includes an RS flip-flop using an edge of the received signal as a set signal, an integrating means for integrating an output of the RS flip-flop, and an output of the integrating means having a predetermined threshold value. A comparator for generating a reset signal for resetting the RS flip-flop when the above is reached, wherein the time constant of the integrating means is controlled by a signal from the frequency detecting means. Then, by controlling the time constant of the integrating means according to the frequency change, the pulse width can be changed and the demodulation level can be increased.

The integrating means comprises a capacitor and a constant current source for charging the capacitor, wherein the time constant is controlled by controlling the current value of the constant current source with a signal from the frequency detecting means. And Then, by controlling the current value of the constant current source according to the frequency change, the pulse width can be changed and the demodulation level can be increased.

The pulse signal generating means includes an RS flip-flop using an edge of the received signal as a set signal, an integrating means for integrating an output of the RS flip-flop, and an output of the integrating means having a predetermined threshold value. And a comparator for generating a reset signal for resetting the RS flip-flop when the above occurs. The comparator is configured to control a threshold value at which the comparator generates a reset signal by a signal from frequency detection means. By controlling the threshold value of the comparator according to the frequency change, the pulse width can be changed, and the demodulation level can be increased.

The frequency detecting means is configured to convert a frequency change into a voltage change. The frequency detecting means can be configured with a simple configuration.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows an F of Embodiment 1 of the present invention.
It is a block diagram of M demodulation device.

In FIG. 1, the same functional blocks as in FIG. 5 are given the same numbers. 1 is an antenna, 2 is a receiver, 3 is frequency detection means, 4 is delay means, 5 is multiplication means, and 6 is a low-pass filter. An FM demodulator is constituted by the frequency detecting means 3, the delaying means 4, the multiplying means 5, and the low-pass filter 6 for removing the intermediate frequency component. The frequency detecting means 3 has the same configuration as that of the conventional FM demodulating apparatus including the delay means 4, the multiplying means 5 and the low-pass filter 6 shown in FIG. That is, a voltage change corresponding to the frequency change of the intermediate frequency signal occurs in the output of the frequency detecting means 3. The output of the frequency detecting means 3 controls the delay time of the delay means 4. If the signal S1 output from the receiver 2 is S1 = Acos (ω + Δω) t, where ω: the central angular frequency of the intermediate frequency signal Δω: angular frequency shift, the output S2 of the delay means 4 is S2 = Acos (ω + Δω) ( t + τ) where τ is a delay time. S1 in the multiplication means 5
And S2 are multiplied. The output of the multiplying means 5 is filtered by a low-pass filter 6 to remove high-frequency components higher than the intermediate frequency component, and the output S3 of the low-pass filter 6 is given by S3 = S1.
^{× S2 = (A 2/2} ) × cos (ω + Δω) τ is output.

Here, the delay time τ is set so that ωτ = 90 °.
Is set. Therefore ^{S3 = - (A 2/2} ) × sin
Δωτ.

When Δωτ << 1, S3 ≒ − (A ² /
2) A demodulated output of × Δωτ can be obtained. In the conventional example, the delay time τ is always constant regardless of the value of Δω. In this embodiment, for example, the delay time τ is controlled so as to change in proportion to Δω. That is, τ = τ0 (1
+ Α × Δω).

Here, α is a coefficient indicating the magnitude of change of the delay time τ. Thus demodulated output ^{S3 ≒ - (A 2/2} )
× (Δω + α × Δω ² ) × τ0. That is, a demodulated output (1 + α × Δω) times larger than that of the conventional example can be obtained. The term α × Δω ² × τ0 in the demodulated output includes a distortion component, but does not pose a problem in the case of data communication.

(Embodiment 2) FIG.
It is a block diagram of M demodulation device.

In FIG. 2, the same numbers are assigned to the same functional blocks as in FIG. The difference from FIG. 1 is that an edge detecting means 7 and a pulse signal generating means 8 are used instead of the delay means 4 and the multiplying means 5. The demodulation method including the edge detection means 7 and the pulse signal generation means 8 is called a so-called pulse count method. The rising or falling edge of the intermediate frequency signal is detected by the edge detecting means 7 and notified to the pulse signal generating means 8. The pulse signal generation means 8 outputs a pulse signal having a predetermined width T when a signal is received from the edge detection means 7. Accordingly, a dense and sparse pulse train having a constant pulse width is generated at the output of the pulse signal generating means 8 in accordance with the sparse and dense of the frequency of the intermediate frequency signal. By removing the high-frequency component by the low-pass filter 6, the output is low in the dense part of the pulse train and low in the sparse part of the pulse train. That is, S3 = A × (ω + Δω) × T = A × ω × T + A × Δω ×
T where A: coefficient ω: central angular frequency of the intermediate frequency signal Δω: angular frequency shift T: pulse width occurs. If T is constant in the above equation, the first term is constant regardless of the frequency shift and is a bias component.

Therefore, the demodulated output is S3 = A × Δω × T. In the conventional pulse counting method, the pulse width T was a constant value T0. In this embodiment, the pulse width T is controlled and changed by a signal from the frequency detecting means 3.

For example, T = (1 + α × Δω) × T0 is controlled. Therefore, the demodulated output S3 = A × (ω + ω × α ×
Δω × + Δω + α × Δω ² ) × T0. Since the first term in the above equation is a bias component, removing it from the demodulated output gives S3 = A × ((1 + α × ω) × Δω + α × Δω ²⁾ × T0. Therefore, ((1 + α × ω) + α ×
Δω) times larger demodulation output can be obtained. The term α × Δω ² × T0 in the demodulated output includes a distortion component, but does not pose a problem in the case of data communication.

(Embodiment 3) FIG. 3 is a block diagram showing a configuration of the pulse signal generating means 8 in Embodiment 3 of the present invention.

In FIG. 3, 9 is an RS flip-flop, 10 is an electronic switch, 11 is a constant current source, 12 is a capacitor, 13 is a control signal from the frequency detecting means 2 in FIG. 2, 14 is a power supply, and 15 is a comparator. , 16 are power supplies, 1
A set terminal 7 receives a signal from the edge detecting means 7 shown in FIG. Reference numeral 18 denotes a reset terminal, and 19 denotes an output of the pulse signal generating means 8. The output of the RS flip-flop 9 becomes LOW when a signal is input to the set terminal 17, and the output becomes HI when a signal is input to the reset terminal 18.
Become GH. When the output of the RS flip-flop 9 is set to LOW, the electronic switch 10 turns off. The electronic switch 10 can be composed of a transistor. When the electronic switch 10 is turned off, the current from the constant current source 11 flows into the capacitor 12 to charge the capacitor 12. When the capacitor 12 is charged and the voltage of the capacitor 12 rises above a predetermined voltage level applied to the power supply 16, the output of the comparator 15 becomes HIGH. Since the output of the comparator 15 is connected to the reset terminal 18 of the RS flip-flop 9, the output of the comparator 15
When the signal goes high, the output of the RS flip-flop 9 is reset to high. Then, the electronic switch 10 is turned on, the capacitor 12 is discharged instantaneously, and the output of the comparator 15 becomes LO.
W. The circuit shown in FIG. 3 operates as a monostable multivibrator. Therefore, a pulse signal having a predetermined pulse width is generated at the output 19 every time there is a signal from the edge detecting means 7. There are two factors that determine the pulse width: (1) the voltage level applied to the power supply terminal 16 that determines the threshold value of the comparator 15 (2) the time constant determined by the capacitance value of the capacitor 12 and the current value of the constant current source 11. . In the present embodiment, the constant current source 11 is controlled by the control voltage input to the control terminal 13 so that the current value for charging the capacitor 12 is made variable. That is, when the frequency detected by the frequency detecting means 3 increases, the voltage of the control terminal 13 increases, and the charging current for charging the capacitor 12 from the constant current source 11 decreases. Therefore output 19
The pulse width generated at the time is widened.

(Embodiment 4) FIG. 4 is a block diagram showing another configuration of the pulse signal generating means 8 in Embodiment 4 of the present invention.

In FIG. 4, the same functional blocks as in FIG. 3 are given the same numbers. 13 is different from FIG. 13 in that the control terminal 13 is provided in the comparator 15 instead of the constant current source 11. That is, the pulse width is made variable by controlling the threshold value of the comparator 15 with a signal from the frequency detection means 3. When the frequency detected by the frequency detecting means 3 increases, the voltage of the control terminal 13 increases, and the threshold value of the comparator 15 increases. Accordingly, the time required for the comparator 15 to change from LOW to HIGH becomes longer, and the pulse width generated at the output 19 becomes wider. Other operations are the same as those of the circuit of FIG.

In each of the above embodiments, the independent frequency detecting means 3 is provided in each case, and its output is used as the control signal. However, the output of the low-pass filter 6 may be used as the output of the frequency detecting means. In this case, since positive feedback is applied to the level, it is necessary to perform an operation such as reducing the control amount so that the level does not diverge.

[0026]

As described above, according to the present invention, delay means for delaying a reception signal by a predetermined time, multiplication means for multiplying the reception signal by a signal from the delay means, and demodulation from the output of the multiplication means It has a filter for extracting an output, and frequency detecting means for outputting a signal corresponding to the frequency of the received signal, and the delay time of the delay means is controlled by a signal from the frequency detecting means. ,
A large demodulation output can be obtained.

Further, an edge detecting means for detecting a rising or falling edge of the received signal, and a pulse signal generating means for generating a pulse signal having a predetermined pulse width in synchronization with the edge detected by the edge detecting means. A filter for extracting a demodulated output from the pulse signal, and frequency detecting means for outputting a signal corresponding to the frequency of the received signal, and a pulse generated by the pulse signal generating means with a signal from the frequency detecting means. Since the width is controlled, a large demodulated output can be obtained even when the pulse count demodulation method is used.

Further, the pulse signal generating means includes an RS flip-flop using an edge of the received signal as a set signal, an integrating means for integrating an output of the RS flip-flop, and an output of the integrating means for setting a predetermined threshold value. A comparator for generating a reset signal for resetting the RS flip-flop when the above is reached, and controlling the time constant of the integrating means by a signal from the frequency detecting means. Thus, the circuit can be formed easily and the structure can be easily made into an IC.

The integrating means comprises a capacitor and a constant current source for charging the capacitor, and controls the current value of the constant current source by a signal from the frequency detecting means to control the time constant. , A stable time constant is selected, and a circuit configuration suitable for IC integration is obtained.

The pulse signal generating means includes an RS flip-flop using an edge of the received signal as a set signal, an integrating means for integrating an output of the RS flip-flop, and an output of the integrating means for setting a predetermined threshold value. And a comparator for generating a reset signal for resetting the RS flip-flop when the above has occurred, and the comparator is configured to control a threshold for generating a reset signal by a signal from frequency detection means. Becomes extremely simple.

Since the frequency detecting means is configured to convert a frequency change into a voltage change, a conventional simple FM
This can be realized using a demodulation circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of an FM demodulator according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an FM demodulator according to a second embodiment of the present invention;

FIG. 3 is a block diagram of a pulse signal generator in an FM demodulator according to a third embodiment of the present invention;

FIG. 4 is another block diagram of a pulse signal generation unit in the FM demodulation device according to the fourth embodiment of the present invention.

FIG. 5 is a block diagram of a conventional FM demodulator;

[Explanation of symbols]

 2 Receiver 3 Frequency detection means 4 Delay means 5 Multiplication means 6 Low-pass filter 7 Edge detection means 8 Pulse signal generation means 9 RS flip-flop 10 Electronic switch 11 Constant current source 12 Capacitor 13 Control terminal 15 Comparator

Claims (6)

[Claims] A delay means for delaying a reception signal by a predetermined time; a multiplication means for multiplying the reception signal by a signal from the delay means; a filter for extracting a demodulated output from an output of the multiplication means; Frequency detecting means for outputting a signal corresponding to the frequency, wherein the signal from the frequency detecting means controls the delay time of the delay means.
M demodulator. 2. An edge detecting means for detecting a rising or falling edge of a received signal, and a pulse signal generating means for generating a pulse signal having a predetermined pulse width in synchronization with the edge detected by the edge detecting means. A filter for extracting a demodulated output from the pulse signal, and frequency detecting means for outputting a signal corresponding to the frequency of the received signal, and a pulse generated by the pulse signal generating means with a signal from the frequency detecting means. FM demodulator that controls the width. 3. A pulse signal generating means, comprising: an RS flip-flop using an edge of a received signal as a set signal;
Integrating means for integrating the output of the S flip-flop; and R-output when the output of the integrating means exceeds a predetermined threshold value.
3. The FM according to claim 2, further comprising a comparator for generating a reset signal for resetting the S flip-flop, wherein the time constant of the integration means is controlled by a signal from a frequency detection means.
Demodulator. 4. An integrating means comprising a capacitor and a constant current source for charging the capacitor, wherein a time constant is controlled by controlling a current value of the constant current source with a signal from a frequency detecting means. Item 3. An FM demodulator according to Item 3. 5. A pulse signal generating means, comprising: an RS flip-flop for setting an edge of a received signal as a set signal;
Integrating means for integrating the output of the S flip-flop; and R-output when the output of the integrating means exceeds a predetermined threshold value.
3. The FM demodulator according to claim 2, further comprising a comparator for generating a reset signal for resetting the S flip-flop, wherein the comparator controls a threshold value for generating the reset signal by a signal from a frequency detection unit. 6. The FM demodulator according to claim 1, wherein the frequency detecting means converts a frequency change into a voltage change.