JP2000113690A - Semiconductor nonvolatile memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable effective writing even if the write characteristic is changed to reduce the write time by determining whether the threshold value of an electrical programmable nonvolatile memory cell is identical to the reference potential or not and then controlling the write voltage depending on the result of determination. SOLUTION: A high voltage VPP is input to a voltage boosting circuit 104. Depending on the data DL which has been initialized in a determination circuit 2 and read to a selecting circuit 6, the lowest write voltage WV5 is selected from the write voltages WV 1 to 5 and it is then impressed to a control gate of memory cell 3 for the purpose of data writing. A determination reference voltage VV is applied to the control gate of the memory cell 3 and a current across the drain and source is converted to the data DL via the current - voltage converting circuit 9 and A/D converter 8. When the data DL is read and the threshold value of memory cell 3 has not reached the write determination reference voltage VV, the higher write voltage WV 1 to 4 is selected and this selection is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory device, and more particularly to a data write circuit thereof.

[0002]

2. Description of the Related Art As a conventional semiconductor nonvolatile memory device, there is one disclosed in Japanese Patent Application Laid-Open No. Hei 4-139699.
In this semiconductor nonvolatile memory device, as shown in the sectional view of FIG. 10, a field oxide film 101 is formed on a P-type substrate 100, and a source region 102 and a drain of an N + diffusion layer are provided between the field oxide films 101. An area 103 is formed. A non-volatile memory cell 104 including a floating gate 111 and a control gate 112 is provided above the source region 102 and the drain region 103 via a gate oxide film 110, and a P-type diffusion layer is formed on the P-type substrate 100. A back gate layer 105 is formed, and a back gate voltage supply for applying a back gate voltage VBG lower than the low voltage side common power supply VSS to the nonvolatile memory cell 104 in synchronization with data writing to the non-volatile memory cell 104 is formed on the back gate layer 105. The circuit 106 is connected.

As shown in FIG. 11, the circuit configuration of the semiconductor nonvolatile memory device includes bit lines BL1 to BL1.
Non-volatile memory cells M11 to Mnn are connected between BLn and the word lines WL1 and WL1 to WLn to form a cell array SA. Each memory cell is connected to a back gate voltage supply circuit 106.

The back gate voltage supply circuit 106 supplies a negative potential VB supplied from the back gate voltage supply circuit 106 to the back gate of the nonvolatile memory cell 104 via the P-type substrate 100 and the back gate layer 105.
By applying G, the potential of the control gate 112 is relatively increased, the amount of charge injected into the floating gate 111 of the memory cell 104 is increased, and the writing time is reduced.

[0005]

The above-mentioned conventional semiconductor nonvolatile memory device has the following problems. The first point is a decrease in the reliability or productivity of the write data, and the second point is an increase in the production cost or a decrease in the production yield.

First, as a first problem, in the writing of the above-described conventional semiconductor nonvolatile memory device, the negative potential VBG is applied to cells other than the memory cell to be written, that is, the back gate of the non-selected cell. As a result, the data in the already written memory cell is lost, and the reliability of the data is reduced. To prevent this, the P-type substrate 1
00 needs to be separated, the layout area increases,
This has led to a drop in productivity.

Next, the second problem will be described. First, the write characteristics of a memory cell including a MOS transistor having a floating gate will be described with reference to FIG.

FIG. 9 is a graph showing the write characteristics of a flash ROM of a 0.6 μm process, wherein the horizontal axis is the logarithm of the write time tp, and the vertical axis is the threshold value Vt of the memory cell.
h. Two curves A and B in the figure show the respective write characteristics when the control gate voltage is set to two conditions, that is, when the control gate voltage is high and when the control gate voltage is low. As can be seen from the characteristic graph of FIG. 9, in the initial stage of the write operation in which the write time tp is short, the lower the control gate voltage, the higher the threshold value Vth of the memory cell.
In the latter half of the write operation when the write time tp is long,
The higher the control gate voltage, the higher the threshold value Vth of the memory cell. Due to a difference in impurity implantation amount between individual memory cells and manufacturing lots, a difference in thickness of a gate oxide film between a floating gate and a substrate, or a difference in memory cell dimensions due to a difference in a manufacturing process, two of FIG. The curves A and B change back and forth or up and down. In the initial stage of the write operation, the lower the control gate voltage, the later the write operation,
The higher the control gate voltage, the better the writing characteristics. This is because, in the initial stage of the write operation, when the control gate voltage is high, the formation of the channel between the drain and the source is promoted. Carriers do not have high energy and are less likely to be hot electrons. If the amount of generated hot electrons is small, the amount of carriers accumulated in the floating gate is also small, so that the writing characteristics are deteriorated. Thereafter, as time passes, an electric field is generated due to carrier movement between the drain and the source, a depletion layer is formed, and hot electrons are generated and started to be injected into the floating gate.

At this point, the higher the control gate voltage, the easier the hot electrons can jump over the barrier of the gate oxide film, the larger the amount of charge injected into the floating gate, and the better the write characteristics. Note that a state in which charges are accumulated in the floating gate of the memory cell is referred to as ““ 1 ”level data is written”, and a state in which charges in the floating gate are depleted is referred to as “0” level data. Has been written. "
Further, the write determination reference potential which is a reference potential for determining the writing of the memory cell is near the intersection of the two curves in FIG.

In FIG. 9, the write determination reference potential does not have a fixed value and is shown in a certain range. However, if the write determination reference voltage is increased, the potential of the floating gate after the completion of writing is increased. Is higher, the reliability of the write data is improved, but if the write determination reference potential is set higher than necessary, the write time will increase,
In addition, the stress applied to the memory cell increases accordingly. For example, the write determination reference potential in FIG.
Considering the case of increasing to V, 100 per byte
The write time increases by μs, and in a 256-Kbyte memory, the write time increases by 25.6 s. This is because it depends on the reliability of the product, that is, the guaranteed years of the write data, the operation guarantee range, and the like.

As shown in FIG. 9, if the write characteristics of all memory cells, manufacturing lots, and manufacturing processes are exactly the same and the write determination reference potential is high, the control gate voltage is increased. The write time can be shortened, but when the write determination reference potential is low, the write time is shortened by lowering the control gate voltage, that is, the write voltage is generally increased by the product or manufacturing variation. In this case, it is not always possible to shorten the time for writing to the write determination reference voltage. Further, it is practically impossible to make the write characteristics of all memory cells and production lots the same.

Since the carriers accumulated in the floating gate in the memory cell are released due to disturbance, thermal stress, etc., the threshold value of the memory cell gradually decreases. Therefore, in order to guarantee data retention, it is necessary to secure the deterioration amount as a margin for the write determination reference potential. In general, a voltage several volts higher than the read voltage at the time of memory reading is set. In addition, whether or not data is written is determined by whether or not the potential of the floating gate has reached the write determination reference potential. In conventional devices and methods,
In order to write to the write determination reference potential, the write time needs to be set extra than the originally required write time, so that the write time increases and the production cost increases. Further, when the writing time is limited to a certain time in order to reduce the production cost, there is a disadvantage that the manufacturing yield is reduced.

An object of the present invention is to frequently perform an operation of judging a write state so that individual memory cells, manufacturing lots,
Another object of the present invention is to provide a semiconductor non-volatile memory device that can achieve the most efficient writing even if the writing characteristics fluctuate due to a manufacturing process and can realize a reduction in the writing time.

[0014]

According to the present invention, there is provided a semiconductor nonvolatile memory device comprising: a nonvolatile memory cell whose storage contents can be electrically rewritten; a means for writing data to the memory cell; and a means for reading the data. A determination circuit for determining whether a threshold value of a memory cell in which data of “1” level is written is a reference potential and outputting a determination result; A control gate voltage supply circuit for controlling a write voltage to the memory cell.

The control gate voltage supply circuit includes a booster circuit for generating a boosted voltage by boosting a high voltage supplied from outside the device, a plurality of write voltages by dividing the boosted voltage by a resistor, and a write determination circuit. A resistor circuit that generates a reference voltage and data output from the determination circuit are read, and a write signal is enabled for a period of time.
Any one of the plurality of write voltages is selected as the write determination reference voltage when the determination signal is enabled, and the power supply voltage is selected during the read signal is enabled, and is output to the control gate of the memory cell via a word line. A selection circuit, wherein the determination circuit includes a transistor switch circuit that outputs a power supply voltage to a drain terminal of a memory cell via a bit line during a period in which the write signal is enabled; A current-voltage conversion circuit that reads a current value between the drain terminal and the source terminal of the cell via a bit line and outputs a voltage corresponding to the current value; and converts the voltage of the current-voltage conversion circuit into a digital signal. An A / D converter for generating data; a control gate voltage supply circuit for latching the data; A latch circuit that outputs to a device external terminal, and a sense amplifier that reads a current between a drain-source terminal of the memory cell via a bit line and outputs read data during a period in which the read signal is enabled. .

Also, the resistance circuit of the control gate voltage supply circuit receives the data output from the determination circuit and reduces the boosted voltage to generate a write determination reference voltage, and changes the resistance value. A variable resistance circuit that generates a write voltage by using a first resistor that charges a capacitor between a drain terminal and a source terminal of a memory cell during a period in which the determination signal is enabled.
A switch circuit that outputs a power supply voltage to a drain terminal of a memory cell via a bit line during a period in which the write signal is enabled; and a transistor that outputs a voltage value of the capacitor as data to the variable resistance circuit. And a sense amplifier circuit that reads a current between the drain and source terminals of the memory cell via a bit line and outputs read data during a period in which the read signal is enabled.

The control gate voltage supply circuit may include a booster circuit for boosting a high voltage supplied from outside the device to generate a boosted voltage, a plurality of write voltages by dividing the boosted voltage by a resistor, and a plurality of write voltages. A resistor circuit for generating a write determination reference voltage, a first switching circuit for inputting data output from the determination circuit and selecting from among a plurality of write voltages, and a predetermined count value output from the counter circuit; A second switching circuit for inputting and selecting from among the plurality of write determination reference voltages, and a third switching circuit for switching between the write voltage and the write determination reference voltage and outputting to the control gate of the memory cell via the word line. The determination circuit includes verification data input from outside the device and sense amplifiers. The read circuit receives the count value from the counter circuit of the determination circuit, and outputs the determination result from the comparison circuit. When the read data and the verify data match, a latch circuit that latches the count value at that time, a power supply voltage at the time of memory read, and a voltage slightly higher than the ground level at the time of write determination are applied to the sense amplifier, A drain voltage supply circuit for applying a power supply voltage to a drain terminal of the memory cell via a bit line at the time of writing; and a memory for reading a current between a drain and a source of the memory cell at the time of memory reading and at the time of writing judgment, and outputting read data. And a sense amplifier.

Further, the memory cell is a flash ROM.
In the case of an electrically erasable storage element such as the one described above, a source voltage supply for outputting a ground level voltage to the source terminal of the memory cell at the time of writing, judging, and reading operations and a high voltage at the time of erasing operation. Circuit.

Further, the resistance circuit is a polycide resistor.

[0020]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 2 is a detailed block diagram of FIG. This embodiment includes a control gate voltage supply circuit 1, a determination circuit 2, and a memory cell 3.

The control gate voltage supply circuit 1 selects a write voltage according to the data of the determination circuit 2 based on the read result of the memory cell 3. The high voltage VPP is supplied to the control gate voltage supply circuit 1 from outside the device. The write signal WE is supplied to the control gate voltage supply circuit 1 and the determination circuit 2 from outside the device, and the determination signal V
E is a control gate voltage supply circuit 1 from outside the device,
The data DL is supplied to the determination circuit 2, and the data DL is generated by the determination circuit 2 and supplied to the control gate voltage supply circuit 1 and the determination circuit 2. Word line WL is connected to memory cell 3 and control gate voltage supply circuit 1, and bit line BL
Connects the memory cell 3 and the determination circuit 2.

The control gate voltage supply circuit 1 is shown in FIG.
As shown in FIG. 5, a booster circuit 4 for boosting a high voltage VPP supplied from outside the device to generate a boosted voltage VPH, and a plurality of write voltages W
V1 to WV5, a resistance circuit 5 for generating a write determination reference voltage VV, and data D output from the determination circuit 2.
L, and while the write signal WE is enabled, one of the plurality of write voltages WV1 to WV5 is
A selection circuit 6 that selects the write determination reference voltage VV during the period in which the determination signal VE is enabled, and selects the power supply voltage VDD during the period in which the read signal READ is enabled, and outputs the selected voltage to the control gate of the memory cell 3 via the word line WL.
It is composed of

As shown in the circuit diagram of FIG. 3, the selection circuit 6 is a switching circuit composed of MOS transistors 13 to 24, and uses the write voltages WV1 to WV5, the write determination reference voltage VV and the power supply voltage VDD as input voltages. , Read signal READ, determination signal VE, data D
Using L and the write signal WE as selection signals, one of the input voltages is selected and output to the word line WL.

The determination circuit 2 outputs the power supply voltage VDD to the drain terminal of the memory cell 3 via the bit line BL during the period when the write signal WE is enabled, and the transistor switch circuit 12 during the period when the determination signal VE is enabled. A current value between the drain terminal and the source terminal of the memory cell 3 is read via the bit line BL, and a current-voltage conversion circuit 9 that outputs a voltage corresponding to the current value, and generates data based on the output voltage. The A / D converter 8, the latch circuit 7 for latching data and outputting to the control gate voltage supply circuit 1 and the external terminal of the device, and the drain-source terminal of the memory cell 3 during the period when the read signal READ is enabled A sense amplifier 10 that reads a current through a bit line BL and outputs read data
And a source voltage supply circuit 11 for supplying a source voltage of the memory cell 3.

Here, the high voltage VPP is supplied to the booster circuit 4 from outside the device. The read signal READ is supplied from outside the device to the sense amplifier 10 and the selection circuit 6, and the write signal WE is supplied from outside the device to the selection circuit 6 and the transistor switch circuit 12. The determination signal VE is supplied from outside the device to a latch circuit 7, an A / D converter 8, a current-voltage conversion circuit 9, and a selection circuit 6. The data DL is generated by the determination circuit 2 and output to the selection circuit and the outside of the device,
The output of the selection circuit 6 is applied to the memory cell 3 via the word line WL.
Is connected to the gate terminal. The drain terminal of the memory cell 3 is connected to the transistor switch circuit 1 via the bit line BL.
2, connected to the current-voltage conversion circuit 9 and the sense amplifier 10. The reset signal RST is supplied from the outside of the device to the latch circuit 7.
Supplied to

The power supply voltage VDD is supplied to the selection circuit 6 from outside the device.
Is supplied to the transistor switch circuit 12. The write voltages WV <b> 1 to WV <b> 5 and the write determination reference voltage VV generated by dividing the voltage VPH by the resistance circuit 5 are supplied to the selection circuit 6. The voltage output from the current-voltage conversion circuit 9 is input to the A / D converter 8 and the data D
The data DL is converted to L and the data DL is latched by the latch circuit 7. The sense amplifier 10 outputs read data ReadDATA to outside the device. A predetermined voltage is supplied from a source voltage supply circuit 11 to a source terminal in the memory cell 3.

FIG. 4 is a flowchart showing the operation of the circuit of FIG. First, a programming mode is started from outside the device. Generally, after setting the mode register, the high voltage VPP
At a certain timing, the mode shifts to the programming mode. In response to the start of the programming mode, a reset signal RST is input from outside the device, and the latch circuit 7 in the determination circuit 2 initializes the data DL (step 42). In this case, "1" is appropriate as the initial value. In the initialization of the data DL, in the selection of the write voltage in step 46, which will be described later, it is determined that writing is performed for the first time in the selection circuit in the control gate voltage supply circuit 1. 6.

Next, at step 43, the judgment signal VE is disabled. This judgment signal VE is controlled from outside the apparatus. Next, at step 44, the write signal WE is enabled to start the write operation 40. This write signal WE is also controlled from outside the device. The data DL set in the aforementioned step 42 is read into the selection circuit 6 in a step 45. Based on the data DL read in step 45, a write voltage is selected in the selection circuit 6 in step 46. This write voltage is applied to the voltage VP by the resistance circuit 5.
Write voltages WV1 to WV generated by dividing resistance of H
Select from 5 At this point, the data DL
Is the initial value "1", the MOS transistor 15 is turned on, and the lowest write voltage WV5 is selected. The write voltage selected in Step 46 is output to the control gate of the memory cell 3 via the word line WL (Step 47).

Next, at step 48, a write voltage is applied to the control gate of the memory cell 3, a ground level voltage is applied to the source from the source voltage supply circuit 11, and a power supply voltage VDD is applied to the drain of the memory cell 3, and the write is executed. The execution time of this writing is set to the minimum time required for hot carriers to be generated in the memory cell 3 and accumulated in the floating gate. This time is 10-1
00 μs is most appropriate. After the predetermined write time set in step 48 has elapsed, the write signal WE is disabled in step 49, and in response to the write signal WE being disabled in step 50, the selection circuit 6 and the MOS transistor 12 are disabled. Is the memory cell 3
, And the write operation 40 is completed.

Next, at step 51, the decision signal VE is enabled to start the decision operation 41.
E is also controlled from outside the device. In response to the determination signal VE being enabled, the selection circuit 6 determines in step 52
Outputs the write determination reference voltage VV to the word line WL. A write determination reference voltage VV is applied to the control gate of the memory cell 3, and a ground level voltage is applied to the source from the source voltage supply circuit 11. Is read into the current-voltage conversion circuit 9 via the. If the potential of the floating gate is higher than the write judgment reference voltage,
No current flows between the drain and the source, but a low current flows. Next, at step 54, the current-voltage conversion circuit 9
Then, a voltage corresponding to the value of the read current is generated. The voltage output from the current-voltage conversion circuit 9 is input to the A / D converter 8 and converted into data DL in step 55. Next, at step 56, the data DL is latched by the latch circuit 7. The determination signal VE is disabled, the selection circuit 6 and the MOS transistor 12 stop outputting the voltage to the memory cell 3, and the determination operation 41 is completed (step 57).

The operator or ROM writer
The data DL output from the determination circuit 2 is read, and it is determined whether the threshold value of the memory cell 3 has been written to the write determination reference voltage VV (step 58). If the threshold value of the memory cell 3 has not reached the write determination reference voltage VV, the steps from step 44 to step 58 are repeated again. In step 46, the lowest write voltage WV5 is selected in the first write operation. However, from the second time onward, gradually higher write voltages WV4 to WV1 are sequentially selected according to the data DL. In this embodiment, the case where the write voltage is divided into five is described.
There is no limit on the number of divisions.

FIG. 5 is a block diagram of a circuit showing a second embodiment of the present invention. In this embodiment, in addition to the first embodiment, a variable resistor circuit is used for generating a write voltage, and a capacitor is used for data conversion. The resistance circuit 5 of the control gate voltage supply circuit 1 lowers the boosted voltage VPH to generate the write determination reference voltage VV.
And a variable resistance circuit 25 that receives the data DL output from the determination circuit 2 and varies the resistance value to generate the write voltage WV. The determination circuit 2
During a period in which E is enabled, the first current for charging the capacitor 30 with the current between the drain terminal and the source terminal of the memory cell 3
During the period when the write signal WE is enabled, the transistor switch circuit 12 that outputs the power supply voltage VDD to the drain terminal of the memory cell 3 via the bit line BL, and the variable resistor using the voltage value of the capacitor as data The second switch circuit 31 that outputs to the circuit 25 and the memory cell 3
And a source voltage supply circuit 11 for reading a current between the drain and source terminals of the memory cell 3 via the bit line BL and outputting read data, and supplying a source voltage of the memory cell 3.

The high voltage VPP is supplied to the booster circuit 4 from outside the device. The read signal READ is supplied to the transistor switch circuit 28 and the sense amplifier 10 from outside the device. The write signal WE is supplied from outside the device to the selection circuit 6, the transistor switch circuit 12, and the transistor switch circuit 26, and the determination signal VE is supplied from outside the device to the transistor switch circuit 27 and the switch circuit 31. The data DL is generated by the decision circuit 2 and the variable resistance circuit 2
5 and output outside the device. The reset signal RST is supplied from outside the device and supplied to the capacitor. The gate terminal of the memory cell 3 is connected to the transistor switch circuits 26, 27, and 28 via the word line WL, and the drain terminal of the memory cell 3 is connected to the sense amplifier 10, the switch circuit 31, and the transistor switch circuit via the bit line BL. 12 is connected. The power supply voltage VDD is supplied to the transistor switch circuits 12 and 28 from outside the device. A predetermined voltage is supplied from a source voltage supply circuit 11 to a source terminal in the memory cell 3.

The boost voltage VPH generated by the boost circuit 4 is supplied to the resistance circuit 5 and the variable resistance circuit 25, and the write voltage WV generated by the variable resistance circuit 25 is supplied to the transistor switch circuit 26 and generated by the resistance circuit 5. The written write determination reference voltage VV is applied to the transistor switch circuit 27.
Supplied to The sense amplifier 10 reads the read data Rea
dDATA is output to the outside of the device. The current between the drain and the source of the memory cell 3 is connected to the bit line BL and the switch circuit 3
1 to charge the capacitive element 30.

FIG. 6 is a flowchart showing the operation of the circuit of FIG. First, a programming mode is started from outside the apparatus. In response to the start of the programming mode, step 43
To disable the determination signal VE, and the determination signal VE
Is controlled from outside the device. Next, in step 42, the reset signal RST is input from outside the device, the capacitor 30 in the determination circuit 2 is charged, and the data DL is initialized. Next, at step 44, the write signal WE is enabled to start the write operation 40. This write signal WE is controlled from outside the device. Next, the data DL set in step 42 described above is read into the variable resistance circuit 25 in step 45. Data D read in step 45
The resistance value of the variable resistance circuit 25 is changed based on L, and the step-up voltage VPH is changed to generate the write voltage WV in step 60. At this point, since the data DL is the initial value, it is set to be the lowest write voltage. The write voltage WV generated in step 60 is output to the control gate of the memory cell 3 via the word line WL in step 47. Next, at step 48, the write voltage WV is applied to the control gate of the memory cell 3.
The source is supplied with a voltage of the ground level from the source voltage supply circuit 11 and the drain is applied with the power supply voltage VDD to execute writing. The write execution time is set to a minimum time required for hot carriers to be generated and stored in the floating gate in the memory cell 3. This time is most suitably from 10 to 100 μs.

After the fixed write time set in step 48 has elapsed, the write signal WE is disabled in step 49. In response to the disable of the write signal WE, the MOS transistors 12 and 26 stop outputting the voltage to the memory cell 3, and the write operation 40 is completed (step 50). Next, in step 51, the judgment signal VE is enabled to make a judgment operation 41.
Is started, and the capacitive element 30 is discharged. This determination signal V
E is controlled from outside the device. In response to the judgment signal VE being enabled, in step 52, the MOS transistor 27 outputs the write judgment reference voltage VV to the word line WL. A write determination reference voltage VV is applied to the control gate of the memory cell 3 and a ground level voltage is applied to the source from the source voltage supply circuit 11 to open the switch circuit 31. The current charges the capacitive element 30 via the bit line BL. The determination signal VE is disabled, the MOS transistors 12 and 27 terminate voltage output to the memory cell 3, and the determination operation 41 is completed (step 5).
7).

The data DL output from the determination circuit 2 is read to determine whether the threshold value of the memory cell 3 has been written up to the write determination reference voltage VV (step 5).
8). If the threshold value of the memory cell 3 has not reached the write determination reference voltage VV, the write operation 40 and the determination operation 41 are repeated.
The write voltage WV is output by changing the resistance value of the variable resistance circuit 25 based on the voltage value of L, and the resistance value of the variable resistance circuit 25 is changed by the voltage value of the data DL to gradually increase the write voltage. Output.

In the second embodiment of the present invention, in addition to the effects of the first embodiment, since a variable resistance circuit is used for generating a write voltage and a capacitance element is used for data conversion, the linearity is secured. The obtained write voltage and converted data can be obtained.

FIG. 7 is a block diagram showing a third embodiment of the present invention. In this embodiment, in addition to the effects of the first and second embodiments, it is possible to select a write determination reference voltage that is gradually lower than the write determination reference voltage. The control gate voltage supply circuit 1 includes a high voltage VP supplied from outside the device.
Boost circuit 4 for boosting P to generate boosted voltage VPH
A resistance circuit 5 that divides the boosted voltage VPH by resistance to generate a plurality of write voltages WV and a plurality of write determination reference voltages VV; and data DL output from the determination circuit 2.
And a first switching circuit 32 for selecting from among a plurality of write voltages WV and a predetermined count value output from a counter circuit 34 for selecting from among a plurality of write determination reference voltages VV. 2 switching circuit 33 and a third switching circuit 35 that switches between the write voltage WV and the write determination reference voltage VV and outputs the control voltage to the control gate of the memory cell 3 via the word line WL. The verifying data VerifyDATA input from the outside of the device is compared with the read data input from the sense amplifier, and the determination result is output from the latch circuit 37, the counter circuit 34, the comparison circuit 36 which outputs to the outside of the device, and the counter circuit 34. The count value is read, and the judgment result is read from the comparison circuit 36, When the read data and the verify data match, a latch circuit 37 for latching the count value at that time is supplied to the sense amplifier 38 with a power supply voltage at the time of memory read, a voltage slightly higher than the ground level at the time of write determination, and a power supply voltage at the time of write. Voltage supply circuit 39 for supplying a current to the drain terminal of the memory cell 3 via the bit line, a sense amplifier 38 for reading the current between the drain and source of the memory cell 3 at the time of memory read and write determination, and outputting read data. Source voltage supply circuit 1 for supplying the source voltage of memory cell 3
1

The high voltage VPP is supplied to the booster circuit 4 from outside the device. The read signal READ is supplied from outside the device to the switching circuit 35, the sense amplifier 38, and the drain voltage supply circuit 39, and the write signal WE is supplied from outside the device to the switching circuit 35 and the drain voltage supply circuit 39. The determination signal VE is supplied from outside the device to the drain voltage supply circuit 39, the comparison circuit 36, the counter circuit 34, the switching circuit 35, and the sense amplifier 38. The reset signal RST is supplied from outside the device to the latch circuit 37, and the data DL is generated by the latch circuit 37 and output to the switching circuit 32 and the outside of the device. The verify data VerifyDATA is supplied to the comparison circuit 36 from outside the device.

The gate terminal of the memory cell 3 is connected to the word line WL
And the drain terminal of the memory cell 3 is connected to the drain voltage supply circuit 39 and the sense amplifier 38 via the bit line BL. A predetermined voltage is supplied from a source voltage supply circuit 11 to a source terminal in the memory cell 3. The output write voltage WV of the switching circuit 32 and the output write determination reference voltage VV of the switching circuit 33 are supplied to the switching circuit 35.

The boosted voltage VPH generated by the booster circuit 4 is supplied to the resistor circuit 5, and the write voltages WV1 to WV4 generated by the resistor circuit 5 and the write determination reference voltages VV1 to VV1 are output.
VV4 is supplied to a switching circuit 32 and a switching circuit 33, respectively.

The output of the comparison circuit 36 is the counter circuit 34,
The data is supplied to the latch circuit 37 and is output to the outside of the device as a determination result CMP. The output of the latch circuit 37 is supplied to the switching circuit 32. The sense amplifier 38 outputs the read data ReadDATA to the comparison circuit 36 and the outside of the device. The drain voltage supply circuit 39 outputs a voltage to the memory cell 3.

FIG. 8 is a flowchart showing the operation of the circuit of FIG. First, a programming mode is started from outside the apparatus. Generally, after setting the mode register, the high voltage VP
By inputting P at a certain timing, the mode shifts to the programming mode. In response to the start of the programming mode, the reset signal RST is input from outside the device, and the latch circuit 37 in the determination circuit 2 initializes the data DL (step 42). This data DL is to indicate to the switching circuit 32 in the control gate voltage supply circuit 1 that the writing is to be performed for the first time in the selection of the writing voltage in step 46 described later. In step 43, the determination signal VE is disabled. This determination signal VE is controlled from outside the device. In step 44, the write signal WE is enabled to start the write operation 40. This write signal WE is also controlled from outside the device. Data D set in step 42
L is read into the switching circuit 32 at step 45.
Based on the data DL read in step 45, a write voltage WV is selected in the switching circuit 32 in step 46. The write voltage WV is selected from among the voltages WV1 to WV4 generated by dividing the voltage VPH by the resistance circuit 5. At this point, since the data DL is the initial value, the lowest voltage WV4 is selected.

While the write signal WE is enabled, the switching circuit 35 outputs the write voltage WV to the control gate of the memory cell 3 via the word line WL (step 47). The write voltage WV is applied to the control gate of the memory cell 3, the ground level voltage is applied to the source from the source voltage supply circuit 11, and the power supply voltage VDD is applied to the drain from the drain voltage supply circuit 39, and writing is performed (step 48). ). The write execution time is set to a minimum time required for hot carriers to be generated in the memory cell 3 and accumulated in the floating gate. This time is 10-100μ
s is most appropriate. After the fixed write time set in step 48 elapses, the write signal WE is disabled in step 49. When the write signal WE is disabled, the switching circuit 3
5, and the drain voltage supply circuit 39 terminates the voltage output to the memory cell 3, and the write operation 40 is completed (step 50). The determination signal VE is enabled, and the count value of the counter circuit 34 is reset in step 51. This determination signal VE is controlled from outside the device. In response to the determination signal VE being enabled, the counter circuit 34 counts once, and outputs the count value to the switching circuit 33 in step 81. The count value is read from the counter circuit 34, and the write judgment reference voltage VV is selected in step 82 from the voltages VV1 to VV4 divided by the resistance from the resistance circuit 5. At this time, since the count value is the first time, the highest write determination reference voltage VV1 is selected. The switching circuit 35 outputs the write determination reference voltage VV to the word line WL (step 83).

Next, at step 84, a write determination reference voltage VV is applied to the control gate of the memory cell 3, and a ground level voltage is applied to the source from the source voltage supply circuit 11, so that the current between the drain and source of the memory cell 3 is increased. The data is read into the sense amplifier 38 via the bit line BL, and read data ReadDATA is output. The comparing circuit 36 verifies verify data VerifyD input from outside the device.
The ATA and the read data ReadDATA input from the sense amplifier 38 are collated to determine whether or not they match, and in a step 85, the determination result CMP is stored in the latch circuit 37.
If the verify data VerifyDATA and the read data ReadDATA do not match in step 85 for outputting to the counter circuit 34 and the outside of the device, steps 81 to 86 are repeated (step 86). However, every time step 81 is executed, the counter circuit 34
Counting is performed each time, and in step 82, the writing determination reference voltage is gradually selected from VV1 to VV4 based on the count value, and the writing determination reference voltage is sequentially selected.

If the verify data VerifyDATA and the read data ReadDATA match, the counter value is latched by the latch circuit 37 (step 5).
6). The determination signal VE is disabled, the switching circuit 35 and the drain voltage supply circuit 39 stop outputting the voltage to the memory cell 3, and the determination operation 41 is completed (step 57). The data DL output from the determination circuit 2 is read, and it is determined whether the threshold value of the memory cell 3 has been written to the write determination reference voltage VV (step 58). If the threshold value of the memory cell 3 has not reached the write determination reference voltage VV, the write operation 4
0 and the determination operation 41 are repeated. In the operation of selecting the write voltage in step 46, the lowest write voltage WV4 is selected in the first write operation. WV3 to WV1 are sequentially selected. In this embodiment, the case where the write voltage and the write determination reference voltage are divided into four is described, but the number of divisions is not limited.

In the third embodiment of the present invention, in addition to the effects of the first and second embodiments, the write judgment reference voltage is VV
From 1 to VV4, a gradually lower write determination reference voltage can be sequentially selected, and a fine write determination can be made.

In the above embodiment, since the source voltage supply circuit 11 performs only the write, determination, and read operations, the source voltage supply circuit 11 can be realized by a constant voltage power supply that outputs a ground level voltage. In the case where 3 is an electrically erasable storage element such as a flash ROM, a voltage of the ground level is output to the source terminal of the memory cell 3 during the writing, determination, and reading operations, and a high voltage VPP is output during the erasing operation. Circuit.

It is desirable that the resistor circuit has a structure insulated from a diffusion layer such as a polycide resistor.

Further, it is conceivable that an increase in the number of times of the judging operation may require extra time for the judging. However, for one writing time of 10 to 100 μs, the time required for one judging is a MOS transistor. Is turned on,
And 10 which is the time required for the discharge time of the sense amplifier.
0 n to 1 μs, and the determination time does not pose a problem because it is much shorter than the one-time writing time.

[0052]

As described above, the present invention has the following effects. First, the reliability of write data is improved without lowering productivity. Second, the production cost can be reduced without lowering the production yield.

First, as a first effect, it is possible to improve the reliability of write data without reducing productivity.
Conventionally, at the time of writing, since a negative potential is supplied to the back gate of an unselected cell, retention loss of already written data is caused. To prevent this, it is necessary to divide the P substrate for each memory cell. Increases the layout area, which causes a decrease in productivity. On the other hand, according to the present invention, the same ground level potential may be supplied to the back gate of the memory cell 3 regardless of the selected or unselected cell. Thus, there is an effect that high reliability can be realized.

Next, as a second effect, the production cost can be reduced without lowering the production yield. In a conventional circuit, a function of determining whether a threshold value of a memory cell has reached a write determination reference voltage and outputting a determination result,
At least it does not have the function of determining frequently and does not have the function of controlling the write voltage based on the result of the determination, so the write time needs to be extra than the originally required time. This has led to increased costs. Alternatively, if the write time is limited to a certain level in order to reduce the production cost, the production yield of individual memory cells, production lots, and production processes has been reduced. On the other hand, in the circuit according to the present invention, the write time per operation is shortened, the judgment operation is performed frequently, and the necessary minimum write time is required. Since writing can be started and the writing voltage can be increased in the second half of the writing operation, a high writing level can be realized in a shorter writing time, so that even if the writing characteristics vary depending on individual memory cells, manufacturing lots and manufacturing processes, There is an effect that the most efficient writing can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing the first embodiment.

FIG. 3 is a circuit diagram illustrating a switching circuit according to the first embodiment.

FIG. 4 is a flowchart in the first embodiment.

FIG. 5 is a block diagram showing a second embodiment.

FIG. 6 is a flowchart in the second embodiment.

FIG. 7 is a block diagram showing a third embodiment.

FIG. 8 is a flowchart in the third embodiment.

FIG. 9 is a write characteristic graph of a ROM.

FIG. 10 is a cross-sectional view of one conventional embodiment.

FIG. 11 is a circuit diagram in a conventional one embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control gate voltage supply circuit 2 Judgment circuit 3 Memory cell 4 Booster circuit 5 Resistance circuit 6 Selection circuit 7 Latch circuit 8 A / D converter 9 Current-voltage conversion circuit 10 Sense amplifier 11 Source voltage supply circuit 12 Transistor switch circuit 13 to 24 MOS transistors 26 to 28 Transistor switch circuit 25 Variable resistance circuit 29, 31 Switch circuit 30 Capacitance element 32, 33, 35 Switching circuit 34 Counter circuit 36 Comparison circuit 37 Latch circuit 38 Sense amplifier 39 Drain voltage supply circuit 100 Substrate 101 Field oxide film Reference Signs List 102 Source region 103 Drain region 104 Memory cell 105 Back gate layer 106 Back gate voltage supply circuit 110 Gate oxide film 111 Floating gate 112 Control gate G BL bit line BL1 to BLn bit line CMP determination result DL data M11 to Mnn memory cell READ read signal ReadDATA read data RST reset signal SA cell array VBG back gate voltage VDD power supply voltage VE determination signal VerifyDATA verify data VPH boost voltage VPP high voltage VV Write judgment reference voltage VV1 to VV4 Write judgment reference voltage WE Write signal WL Word line WL1 to WLn Word line WV1 to WV5 Write voltage

Claims (6)

[Claims] 1. A semiconductor nonvolatile memory device comprising: a nonvolatile memory cell whose storage contents can be electrically rewritten; a unit for writing data to the memory cell; and a unit for reading the data. A determination circuit that determines whether the threshold value of the memory cell in which the data is written is the reference potential and outputs a determination result, and a control gate voltage supply circuit that controls a write voltage for the memory cell based on the determination result. A nonvolatile semiconductor memory device comprising: 2. The control gate voltage supply circuit according to claim 1, wherein the control gate voltage supply circuit boosts a high voltage supplied from the outside of the device to generate a boosted voltage; A resistor circuit that generates a reference voltage and data output from the determination circuit are read, and one of the plurality of write voltages is used during a period in which a write signal is enabled, and the write determination reference is made during a period in which the determination signal is enabled. A selection circuit for selecting a power supply voltage during a period in which the read signal is enabled, and outputting the selected voltage to a control gate of a memory cell via a word line. A transistor switch circuit for outputting a voltage to a drain terminal of the memory cell via a bit line; While the judgment signal is enabled,
A current-voltage conversion circuit that reads a current value between a drain terminal and a source terminal of the memory cell via a bit line and outputs a voltage corresponding to the current value, and digitally outputs the output voltage of the current-voltage conversion circuit. An A / D converter that converts and outputs conversion data, latches the conversion data,
A latch circuit that outputs the control gate voltage to the control gate voltage supply circuit and an external terminal of the device; and, while the read signal is enabled, reads a current between a drain and a source terminal of the memory cell via a bit line and outputs read data. 2. The semiconductor nonvolatile memory device according to claim 1, comprising a sense amplifier. 3. A resistance circuit of the control gate voltage supply circuit receives a data output from the determination circuit and reduces a boosted voltage to generate a write determination reference voltage, and varies a resistance value. A variable resistor circuit that generates a write voltage by using a first switch circuit that charges a capacitor with a current between a drain terminal and a source terminal of a memory cell during a period in which the determination signal is enabled; A transistor switch circuit that outputs a power supply voltage to a drain terminal of a memory cell via a bit line during a period in which the write signal is enabled; and a second circuit that outputs a voltage value of the capacitor as data to the variable resistance circuit. During a period in which the read signal is enabled, a current between a drain and a source terminal of the memory cell is supplied to the switch circuit through a bit line. 2. The semiconductor nonvolatile memory device according to claim 1, further comprising: a sense amplifier circuit that reads the data and outputs read data. 4. The control gate voltage supply circuit includes: a booster circuit that boosts a high voltage supplied from outside the device to generate a boosted voltage; a plurality of write voltages by dividing the boosted voltage by resistance; A resistance circuit that generates a write determination reference voltage; a first switching circuit that inputs data output from the determination circuit and selects from among a plurality of write voltages; and a predetermined output that is output from a counter circuit of the determination circuit. And a second switching circuit for inputting the count value and selecting from among the plurality of write determination reference voltages, a write voltage, and a write determination reference voltage, which are switched to the control gate of the memory cell via the word line. And a third switching circuit for outputting the verifying data. The read data input from the sense amplifier is compared, the determination result is output to the counter circuit, and a comparison circuit that outputs the determination result to the outside of the device, a count value is read from the counter circuit, and the determination result is read from the comparison circuit. When the read data and the verify data match, a latch circuit that latches the count value at that time, a power supply voltage during memory read, a voltage slightly higher than the ground level during write determination to the sense amplifier, and a write during write, A drain voltage supply circuit for supplying a power supply voltage to a drain terminal of the memory cell via a bit line; and a sense amplifier for reading a drain-source current of the memory cell and outputting read data at the time of memory read and write determination 2. The nonvolatile semiconductor device according to claim 1, comprising: Sex storage device. 5. When the memory cell is an electrically erasable storage element such as a flash ROM, a voltage of a ground level is applied at the time of writing, judging, and reading operations, and a high voltage is applied at the time of erasing operation. 5. The semiconductor nonvolatile memory device according to claim 1, further comprising a source voltage supply circuit that outputs a signal to a source terminal of the memory cell. 6. The semiconductor nonvolatile memory device according to claim 2, wherein said resistance circuit is a polycide resistor.