JP2000101928A - Optical sensor circuit and image sensor using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical sensor circuit which has small parasitic capacity and satisfactory sensitivity. SOLUTION: This optical sensor circuit consists of a converting MOS transistor TR Q1, which converts the sensor current converted by a photo-gate type optical sensor PS that converts an optical signal into a sensor current into the detection voltage having the logarithmic characteristic in a weakly inverted state, a capacitor C which is connected to the detection terminal of the TR Q1 and a gate voltage VG, which applies the resetting voltage to the gate voltage of the TR Q1 and controls the charging or discharging of the capacitor C. Then a photo-gate voltage VPG is added to apply the voltage of a prescribed level to the photo gate Gp of the sensor PS together with a linear response area which detects a detection voltage proportional to the charging or discharging current of the capacitor C, when the sensor current is lower than a prescribed level and a logarithmic response area which detects the detection voltage having the logarithmic characteristic, corresponding to the load characteristic of the TR Q1, when the sensor current exceeds a prescribed level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical sensor circuit for detecting a sensor output corresponding to illuminance and an image sensor using the same.
The present invention relates to an optical sensor circuit having high sensitivity and a large S / N ratio, and an image sensor using the same.

[0002]

2. Description of the Related Art A MOS or CCD image sensor in which photosensor circuits are combined in a matrix is already well known. In these image sensors, electric charges generated in the optical sensor circuit by irradiation light (incident light) are used as optical signals. For example, in a CCD image sensor, electric charges mainly generated by an optical signal are accumulated in each optical sensor circuit and used as an optical signal, and in a MOS image sensor, electric charges are previously stored in a junction capacitance of a photodiode constituting an optical sensor circuit. The light signal is detected by detecting the amount of charge discharged by the irradiation light at the time of recharging.

In order to expand the dynamic range when detecting an optical signal by such an optical sensor circuit, an FET (field effect transistor, for example, an enhancement type n-channel MOS transistor) or the like is used as a photodiode (light receiving element) for the purpose of expanding the dynamic range. Some have been developed that are connected in series and have the function of logarithmically compressing the output voltage. This utilizes the fact that when the current flowing through the FET is small, the resistance change shows a logarithmic characteristic.

FIG. 7 shows a configuration example of such an optical sensor circuit. The optical sensor circuit 100 has a gate connected to a photodiode PD, an enhancement type n-channel MOS transistor Q1 connected in series to the photodiode PD, and a connection point P (sensor detection terminal) between the photodiode PD and the enhancement type n-channel MOS transistor Q1. The enhancement type n-channel MOS transistor Q2 and the enhancement type n-channel MOS transistor Q2.
It comprises an enhancement type n-channel MOS transistor Q3 connected in series with the S transistor Q2. Further, at the connection point P, a photodiode PD, an enhancement type n-channel MOS transistor Q1,
A parasitic capacitance capacitor C composed of Q2 and a combined value of stray capacitances generated by wirings and the like interconnecting them is connected.

[0005] The photodiode PD detects the optical signal Ls and converts it into a sensor current Id proportional to the illuminance of the optical signal Ls. The enhancement type n-channel MOS transistor Q1 forms a load of the photodiode PD, converts a sensor current Id detected by the photodiode PD into a voltage, and generates a detection voltage Vd at a sensor detection terminal P.

Also, an enhancement type n-channel M
The OS transistor Q1 forms a MOS transistor load having a logarithmic characteristic in a weak inversion state where the sensor current Id is small, and converts the sensor current Id detected by the photodiode PD into a detection voltage Vd having a logarithmic characteristic. For this reason, even if the optical signal Ls greatly changes and the sensor current Id greatly changes (a large change such as a different number of digits),
The conversion having the logarithmic characteristic is performed as described above, and the detection voltage V
The change in d is suppressed and does not saturate, and the dynamic range of the output with respect to the input can be widened.

The n-channel MOS transistor Q2 forms an output transistor, and performs voltage-current conversion for extracting the detection voltage Vd to the outside of the optical sensor circuit 10 as a sensor current signal. The n-channel MOS transistor Q3 forms a switch for connecting or disconnecting the sensor current signal converted by the n-channel MOS transistor Q2 to an external circuit.

The operation of the conventional optical sensor circuit configured as described above will be described. Enhancement type n-channel M
The drain D and the gate G of the OS transistor Q1 are connected to a common power supply VD (for example, 5 V). In a state where the optical signal Ls is not detected (the photodiode PD is in a non-operating state), the enhancement type n-channel is supplied from the power supply VD. Charging current Ij via MOS transistor Q1
Flows into the capacitor C, and the capacitor C is charged. Therefore, the detection voltage Vd of the sensor detection terminal P rises to a value close to the voltage of the power supply VD, and this voltage value is a value indicating an initial state in which the photodiode PD has not detected the optical signal Ls.

The value of the detection voltage Vd in the initial state (initial value) increases as the detection voltage Vd at the sensor detection terminal P rises and approaches the voltage of the power supply VD as the capacitor C is charged. The voltage V (GS) between the gate G and the source S of the transistor Q1 (same as the voltage V (SD) between the drain D and the source S) decreases,
Since the impedance between the drain D and the source S sharply increases, the charging current Ij decreases, and is set to a value smaller than the power supply VD (for example, 4.5 V).

When the photodiode PD detects the optical signal Ls from the initial state of the optical sensor circuit 100, a sensor current Id flows through the photodiode PD, and the sensor detection terminal P
The detection voltage Vd decreases in accordance with the increase of the optical signal Ls in a logarithmic characteristic corresponding to the impedance between the drain D and the source S of the enhancement type n-channel MOS transistor Q1, and falls below the initial value. This detection voltage Vd
The optical signal Ls can be detected by detecting the absolute value of. The sensor current Id of the photodiode PD is proportional to the optical signal Ls, while the sensor detection terminal P
Is a value obtained by multiplying the sensor current Id by the impedance between the drain D and the source S having a logarithmic characteristic, so that the optical signal Ls can be detected with a logarithmic characteristic.

FIG. 8 shows a characteristic diagram of the sensor current Id-detection voltage Vd in the optical sensor circuit 100. As can be seen from this figure, the detection voltage V when the optical sensor circuit 100 is close to the initial state (sensor current Id = 10 ⁻¹² A).
The value of d (initial value) is, for example, 4.5 V. When the sensor current increases by 5 digits (when the sensor current Id = 10 ⁻⁷ A), the detection voltage Vd becomes 4.2 V. As described above, when the optical sensor circuit 100 is used, a change of the optical signal at a 5-digit level (100,000 times) can be detected by the detection voltage Vd of 0.3V.
Therefore, an optical sensor circuit having a wide dynamic range with respect to the input of the optical signal Ls can be configured.

However, in the case of the optical sensor circuit 100 having the above-described configuration, since the sensor current Id is converted into the detection voltage Vd by a logarithmic characteristic in the entire range of the optical signal, the optical signal Ls is small and the sensor voltage is small. Current is in a very small range (Id
= 10 ⁻¹² to 10 ⁻¹¹ A), there is a problem that the change in the detection voltage Vd is too small and the sensor sensitivity is not very good.

In the optical sensor circuit 100, when the photodiode PD no longer detects the optical signal Ls, the photodiode PD is shut off, the charging current Ij flows through the capacitor C, and the detection voltage of the sensor detection terminal P is detected. V
Although d increases, as described above, the impedance between the drain D and the source S of the enhancement type n-channel MOS transistor Q1 rapidly increases and does not increase beyond a predetermined value (4.5 V). The time lapse characteristic when the detection voltage Vd increases in this manner is shown by a dashed line L (100) in FIG. 9, and as can be seen from the characteristic shown in FIG.
Since the rate of increase decreases as the value approaches a predetermined value after D is cut off, it takes time to reach the predetermined value (4.5 V).

Therefore, when the photosensor circuits 100 are arranged in a matrix and applied to an image sensor, the response time until reaching the initial value (4.5 V) when resetting the detection voltage Vd is slow, The image sensor has a problem that the image is displayed as a long afterimage.

In the optical sensor circuit 100, the enhancement type n-channel MOS transistor Q1 and the capacitor C form a peak hold circuit for noise, and erroneously detect a noise level having a large amplitude as an optical signal Ls. There is also a problem that the N ratio decreases and the lower limit of detectable illuminance increases, resulting in a decrease in sensitivity.

In view of the above, the present applicant has devised an optical sensor circuit which can detect a minute optical signal with high accuracy, hardly causes an afterimage phenomenon, and has a high S / N ratio ( This has already been filed separately). This optical sensor circuit 200 is shown in FIG. 10, and the above-described optical sensor circuit 100 is an enhancement type n-channel MO.
The difference is that a constant voltage power supply (for example, 5 V) VD is connected to the drain D of the S transistor Q1, and a gate voltage power supply VG capable of applying two kinds of high and low gate voltages is connected to the gate G.

In the case of the optical sensor circuit 200 having such a configuration, at a timing shown in FIG. 11, a high voltage VH sufficiently higher than the drain voltage VD (= 5 V) and a high voltage VH equal to or lower than the drain voltage VD. The low voltage VL is applied to the gate voltage VG. First, when the high voltage VH is set as the gate voltage VG, the enhancement type n
The impedance between the drain D and the source S of the channel MOS transistor Q1 is in a low resistance state, and the capacitor C is, as shown by a solid line L (200) in FIG.
The battery is rapidly charged, and the detection voltage Vd of the sensor detection terminal P is substantially equal to the drain voltage VD (= 5 V) (for example,
4.95V). Therefore, the optical sensor circuit 2
When 00 is arranged in a matrix and applied to an image sensor, the responsiveness until reaching the initial value (4.95 V) when resetting the detection voltage Vd is improved, and the problem of afterimage of the image sensor can be prevented. .

Next, the gate voltage VG is set as a detectable period.
Is set to the low voltage VL, the enhancement type n-channel MOS transistor Q1 enters a weak inversion state.
When the photodiode PD is irradiated with light, the electric charge stored in the capacitor C is discharged. Here, when the light incident on the photodiode PD is weak, the sensor current Id hardly flows, so that the enhancement type n-channel MOS transistor Q1 is in a high impedance state, and mainly the charge charged in the capacitor C is used. . Therefore, the change of the output voltage becomes linear. On the other hand, when the light incident on the photodiode PD becomes stronger, the characteristic of the detection voltage Vd changes as shown by an arrow in FIG. 11, the electric charge stored in the capacitor C is rapidly consumed, and the sensor current flowing through the photodiode PD is changed. Id becomes a current passing through the enhancement type n-channel MOS transistor Q1, and the change of the output voltage Vd becomes logarithmic.

FIG. 12 shows this relationship. When the light is weak and the sensor current Id is 10 ^-12 to 10 ^-11 , the charge of the capacitor C is discharged and the detection voltage Vd changes linearly. In a region where the light is strong and the sensor current exceeds 10 ^-11 , the detection voltage Vd changes logarithmically. That is, in the case of the light sensor circuit 200, when the light is weak (when the sensor current Id is small), a linear output characteristic equivalent to that of a normal MOS element is obtained, and when the light becomes strong (the sensor current The output characteristics equivalent to those of a logarithmic element can be obtained. Accordingly, when the sensor current is small, high sensitivity can be realized by utilizing the accumulation effect, and S / S when the incident light which is a problem in the logarithmic element is small is small.
The problem of N ratio can also be improved.

Each of the photosensor circuits 200 forms one pixel, and the photosensor circuits 200 are arranged in a matrix to form an image sensor. In this photosensor circuit 200, the voltage V0 of the drain D of the enhancement type n-channel MOS transistor Q3 becomes the output voltage of each pixel. The relationship between this voltage V0 and the detection current of the photodiode PD is as shown in FIG. become.

Here, the light sensor circuit 2 constituting each pixel
Reference numeral 00 denotes a MOS transistor Q1 for charging / discharging the charge of the photodiode PD, the parasitic capacitance C of the photodiode, a MOS transistor Q2 for amplifying the detected voltage and converting the current, and a MOS for extracting the converted current to the outside. The transistor Q3 and the like are incorporated in one pixel area. When configuring an image sensor, there is a demand to increase the number of pixels to improve the resolution of the image sensor. To this end, it is necessary to reduce the pixel area as much as possible.

[0022]

However, when the size of the pixel is reduced, the size of the photodiode is inevitably reduced. When various elements are combined to read a signal as in the photosensor circuit 200, the size of the photodiode can be reduced. Since the charge is small, there is a problem that the S / N ratio is reduced and the sensitivity of the image sensor is reduced. Furthermore, the parasitic capacitance of the photodiode affects sensitivity, and the sensitivity decreases as the parasitic capacitance increases. Therefore, when various elements are combined as in the optical sensor circuit 200, the parasitic capacitance occurs due to the wiring and the like, and There is a problem that the parasitic capacitance of the diode is substantially increased and the sensitivity is reduced.

The present invention has been made in view of the above problems, and has as its object to provide an optical sensor circuit having small parasitic capacitance and good sensitivity, and an image sensor using the same.

[0024]

In order to achieve the above object, according to the present invention, there is provided an optical-electrical conversion means for converting an optical signal into a sensor current, and a weak inversion of the sensor current converted by the optical-electrical conversion means. A MOS transistor for conversion (for example, an enhancement type n-channel MOS transistor Q1 and a depletion type n-channel MOS transistor QD1 in the embodiment) for converting into a detection voltage having a logarithmic characteristic in a state and a detection terminal of the conversion MOS transistor And an initial capacitor for controlling the charge or discharge of the capacitor by applying a reset voltage to the gate voltage of the conversion MOS transistor to reduce the drain-source impedance when detecting the optical signal. Setting means (for example, a gate voltage VG in the embodiment) An optical sensor circuit is configured, and in this optical sensor circuit, the light-to-electric conversion unit is formed of a photogate type optical sensor, and a photogate voltage applying unit (for example, a photogate voltage applying unit that applies a predetermined voltage to the photogate of the photogate type optical sensor) , The photogate application voltage VPG in the embodiment). And this optical sensor circuit has a light-
When the sensor current converted by the electric conversion means is a current equal to or less than a predetermined current, a linear response region for detecting a detection voltage proportional to a charging current or a discharging current of the capacitor is provided.
When the sensor current converted by the photoelectric conversion means is a current exceeding a predetermined current, a logarithmic response region for detecting a detection voltage having a logarithmic characteristic corresponding to a load characteristic of the conversion MOS transistor is provided.

An amplification MOS transistor for amplifying and detecting the voltage signal at the detection terminal of the conversion MOS transistor to which the capacitor is connected (for example, the enhancement type n-channel MOS transistor in the embodiment)
It is preferable to provide a transistor Q2), and a selection MOS transistor (for example, an enhancement type n-channel MOS in the embodiment) for setting a timing for detecting a voltage signal of a detection terminal of the conversion MOS transistor to which the capacitor is connected. Transistor Q
Preferably, 3) is provided.

In the optical sensor circuit according to the present invention having the above-described structure, the photoelectric conversion means is constituted by a photogate type optical sensor, and a photogate for applying a predetermined voltage to the photogate of the photogate type optical sensor. Since the voltage applying means is provided, the magnitude of the parasitic capacitance of the photogate-type photosensor can be adjusted by adjusting the voltage applied to the photogate by the photogate voltage applying means. Therefore, the parasitic capacitance can be reduced by reducing the voltage applied to the photogate, and the sensitivity of the optical sensor circuit can be improved.

The image sensor according to the present invention is configured by arranging the photosensor circuits having the above-described configuration in a one-dimensional or two-dimensional array. Since the sensitivity of the optical sensor circuit can be increased, an image sensor with high sensitivity can be obtained using the optical sensor circuit.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first configuration example of the optical sensor circuit 10 according to the present invention. The optical sensor circuit 10 includes a photogate type optical sensor (optical-electrical conversion means) PS and an enhancement type n-channel MOS transistor (conversion MOS
Transistor) Q1, photogate type optical sensor PS and enhancement type n-channel MOS transistor Q1
An n-channel MOS transistor (amplification MOS transistor) Q2 having a gate connected to a connection point P (sensor detection terminal) of the N-channel MOS transistor Q2, and an n-channel MOS transistor (amplification type) connected in series with the n-channel MOS transistor Q2 (A selection MOS transistor) Q3. The connection point P has a photogate type optical sensor P
S, a parasitic capacitance capacitor C which is a combined value of stray capacitances generated by an enhancement type n-channel MOS transistor Q1, an enhancement type n-channel MOS transistor Q2, and a wiring connecting these components;
Is connected.

The photogate type optical sensor PS generates an optical signal Ls
And a sensor current Id proportional to the illuminance of the optical signal Ls
Convert to The enhancement type n-channel MOS transistor Q1 forms a load on the photogate type photosensor PS, converts the sensor current Id detected and converted by the photogate type photosensor PS into a voltage, and generates a detection voltage Vd at the sensor detection terminal P. .

In the photogate type photosensor PS, the photogate Gp is applied to the photogate applied voltage VPG.
, A predetermined photogate voltage is applied. By applying the photogate voltage, a charge well is formed in the sensor PS, and the depth of the charge well changes according to the applied photogate voltage. The depth of the charge well corresponds to the parasitic capacitance of the photogate-type optical sensor PS.
By adjusting the magnitude of the applied voltage, the parasitic capacitance can be adjusted.

Further, the enhancement type n-channel M
The OS transistor Q1 forms a MOS transistor load having a logarithmic characteristic in a weak inversion state in a range where the sensor current Id is small, and converts the sensor current Id detected by the photogate type optical sensor PS into a detection voltage Vd having a logarithmic characteristic. . For this reason, even if the optical signal Ls largely changes and the sensor current Id changes greatly (a large change such that the number of digits differs), the conversion having the logarithmic characteristic is performed and the change in the detection voltage Vd is suppressed. This does not saturate, and the dynamic range of the output with respect to the input can be widened.

The enhancement type n-channel MOS transistor Q2 forms an output transistor, and performs an operation of amplifying and converting the detection voltage Vd into a current signal and extracting it as an amplified voltage signal V0 outside the optical sensor circuit 10. Further, the enhancement type n-channel MOS transistor Q3 is
A switch for connecting or disconnecting the voltage signal amplified by the S transistor Q2 to an external circuit is formed.

In the optical sensor circuit 10 having such a configuration, at the timing shown in FIG.
(= 5V) High voltage VH and drain voltage VD sufficiently higher than
Is applied as the gate voltage VG. The high voltage VH acts only for a short time t1 as a signal voltage for circuit reset, and when the high voltage VH is set as the gate voltage VG,
Enhancement type n-channel MOS transistor Q
9, the impedance between the drain D and the source S is in a low resistance state, and the capacitor C is indicated by a solid line L (2
As shown by (00), the battery is rapidly charged, and the detection voltage Vd of the sensor detection terminal P rapidly rises to a value substantially equal to the drain voltage VD (= 5V) (for example, 4.95V).
For this reason, as described later (FIG. 6), the optical sensor circuit 10
Is applied to an image sensor having a matrix arrangement, when the detection voltage Vd is reset, the response until the detection voltage Vd reaches the initial value (4.95 V) is improved, and occurrence of an afterimage of the image sensor can be prevented.

Next, the gate voltage VG is set to the low voltage VL only during the detectable period t2. In this state, enhancement type n-channel MOS transistor Q1 is in a weakly inverted state. Then, the photogate type optical sensor P
When light is applied to S, first, the charge stored in the capacitor C is discharged. Here, the photogate type optical sensor PS
When the light incident on is weak, the sensor current Id hardly flows, so that the enhancement type n-channel MOS transistor Q1 is in a high impedance state, and mainly the electric charge charged in the capacitor C is used. For this reason,
The output voltage Vd corresponds to the amount of discharge from the capacitor C, and its change becomes linear (linear). The detection of the output voltage Vd at this time is for detecting the accumulated discharge amount within the detectable time t2, and is not affected by peak noise, and detection with a high S / N ratio is performed. Will be

On the other hand, when the light incident on the photogate type optical sensor PS becomes strong, the characteristic of the detection voltage Vd changes as shown by the arrow in FIG. 11, and the charge stored in the capacitor C is rapidly consumed, Gate type optical sensor PS
Is a current passing through the enhancement type n-channel MOS transistor Q1, and the change of the output voltage Vd is logarithmic.

This relationship is as shown in FIG.
The same characteristics as those of the optical sensor circuit 200 shown in FIG. That is, according to the optical sensor circuit 10, when the light is weak and the sensor current Id is 10 ⁻¹² to 10 ⁻¹¹ , the charge of the capacitor C is discharged and the detection voltage Vd changes linearly. In a region where the sensor current strongly exceeds 10 ^-11 , the detection voltage Vd changes logarithmically. That is, in the case of the optical sensor circuit 10, when the light is weak (when the sensor current Id is small), a linear output characteristic equivalent to that of a normal MOS element is obtained, and when the light becomes strong (the sensor current The output characteristics equivalent to those of a logarithmic element can be obtained. Thereby, when the sensor current is small, high sensitivity can be realized by utilizing the accumulation effect, and the S / N when the incident light which is a problem in the logarithmic element is small.
The problem of the ratio drop can also be improved.

The output voltage Vd thus obtained is
Enhancement type n-channel MOS transistor Q
2 and is extracted from the line 11 to the outside as a detection voltage V0 at a switch timing set by the enhancement type n-channel MOS transistor Q3. The relationship between the detection voltage V0 and the sensor current is as shown in FIG.

The optical sensor circuit 10 configured as described above
In the above, the photogate voltage VPG applied to the photogate Gp of the photogate type optical sensor PS is generally set to a low voltage so that the parasitic capacitance is reduced. For this reason, the capacity of the capacitor C decreases,
The sensitivity of the optical sensor circuit 10 is improved.

FIG. 2 shows a second configuration example of the optical sensor circuit according to the present invention. This optical sensor circuit 10 'is configured as shown in FIG.
1 has a configuration in which an enhancement-type n-channel MOS transistor Q3 constituting a switch is removed from the optical sensor circuit 10. Although this circuit does not provide a switch function, detection of an optical signal having characteristics similar to those in FIG. It can be performed.

FIG. 3 shows a third configuration example of the optical sensor circuit according to the present invention. This optical sensor circuit 10 ″ is configured as shown in FIG.
Has a configuration in which an enhancement type n-channel MOS transistor Q2 serving as a signal amplifying means is removed from the optical sensor circuit 10 described above.
Optical signals having the same characteristics as those in the case of FIG. 1 can be detected.

Further, instead of the enhancement type n-channel MOS transistor Q1 in the above configuration, a light sensor circuit may be configured using a depression type n-channel MOS transistor. In FIG. 4, the characteristics of the depletion type n-channel MOS transistor QD1 are indicated by solid lines, and the characteristics of the enhancement type n-channel MOS transistors Q1, Q2, Q3 are indicated by chain lines. As can be seen from this characteristic, the enhancement type n
When the gate voltage VG = 0, the channel MOS transistors Q1, Q2, and Q3 do not output the detection current Id.
Although it is always in the OFF state, in the case of the depletion-type n-channel MOS transistor QD1, the weak inversion state can be achieved with the gate voltage VG = 0.

Specifically, when the gate voltage VG of the depletion type n-channel MOS transistor QD1 is VG = 0, the low voltage VL is applied to the gate of the enhancement type n-channel MOS transistor Q1 in the optical sensor circuit 10 shown in FIG. It becomes the same state as the state that was done. Further, if the gate voltage VG of the depletion type n-channel MOS transistor QD1 is VG = VS, the drain D
A low resistance state between the sources S can be achieved. Therefore, at the timing shown in FIG. 5, the gate voltage VG of the depletion type n-channel MOS transistor QD1 is VG = VS.
11 in the optical sensor circuit 10 of FIG.
The same detection as in the case where the high voltage VH and the low voltage VL are applied at the timing described above can be performed. Therefore, the number of power supplies can be reduced.

Although the above-described optical sensor circuits all use n-channel MOS transistors, p-channel MOS transistors can also be used.

Next, an image sensor 50 in which the photosensor circuits 10 according to the present invention having the above-described configuration are arranged in a matrix will be described with reference to FIG. The image sensor 50 is formed in a rectangular or square shape by arranging photosensor circuits (pixels) 10 in an array on a plane, and here, the constant voltage power supplies VD and VDD are omitted.

In order to perform image detection by the image sensor 50, the detection voltage V0 of each pixel 10 located in a column at a time is taken out from the detection line 55, and the column detection is performed by sequentially scanning each column. . Note that the detection line 55 corresponds to the output line 11 shown in FIG.
The extraction of the detection voltage V0 is performed by applying the switch power supply VC at a predetermined timing. Each time the detection is completed, the gate voltage VG = VS is applied to the gate of the enhancement type n-channel MOS transistor Q1 for each column. And reset this.

The application terminal of the switch power supply VC for extracting the detection voltage V0 is indicated by SEL in each pixel 10, and the gate voltage application terminal for reset is indicated by RST. As shown in FIG. 4, a takeout signal line 5 is connected to each takeout application terminal SEL of a column of pixels.
2 are connected, and a reset signal line 53 is connected to each reset application terminal RST. Further, each extraction signal line 52 is connected to a reset signal line 53 which is connected to a terminal RST of a pixel in the column on the left in the figure.

When the image sensor 50 having the above configuration is used, a take-out signal (switch power supply voltage VC) is applied (scanned) to the take-out signal line 52 sequentially from the vertical pixel row on the left end side to the right. And the detection voltage V0
Take out. Thus, image detection is performed by scanning each vertical pixel row from left to right. Here, the extraction of the detection voltage V0 of the leftmost vertical pixel column is completed, and then the extraction signal is applied to the extraction signal line 52 of the second vertical pixel column from the left to extract the detection signal from this vertical pixel column. When performing, the take-out signal line 52 is connected to the reset signal line 53 of the leftmost vertical pixel column, so a reset signal is applied to this reset signal line 53, all the leftmost vertical pixel columns are reset, and the next light detection Is performed. Hereinafter, when the detection signal is extracted in the same manner, the vertical pixel row on the left is reset at the same time.

With this configuration, the detection signal can be extracted and reset with a single signal, and the control is simplified. The extraction and reset of the detection signal are performed at the end of time t2 in FIG. 5 or FIG.

[0049]

As described above, in the optical sensor circuit according to the present invention, the light-to-electricity conversion means is composed of a photogate type optical sensor, and a photogate for applying a predetermined voltage to the photogate of the photogate type optical sensor. Since the gate voltage applying means is provided, the magnitude of the parasitic capacitance of the photogate type photosensor can be adjusted by adjusting the voltage applied to the photogate by the photogate voltage applying means. Therefore, the parasitic capacitance can be reduced by reducing the voltage applied to the photogate, and the sensitivity of the optical sensor circuit can be improved.

The image sensor according to the present invention is configured by arranging the optical sensor circuits having the above-described configuration in a one-dimensional or two-dimensional array. Since the sensitivity of the optical sensor circuit can be increased, an image sensor with high sensitivity can be obtained using the optical sensor circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first configuration example of an optical sensor circuit according to the present invention.

FIG. 2 is a circuit diagram showing a second configuration example of the optical sensor circuit according to the present invention.

FIG. 3 is a circuit diagram showing a third configuration example of the optical sensor circuit according to the present invention.

FIG. 4 shows a depletion type and an enhancement type n
4 is a graph showing characteristics of a channel MOS transistor.

FIG. 5 is a graph showing a temporal change of a gate voltage VG (a takeout signal) and a detection voltage Vd in an optical sensor circuit using a depletion-type n-channel MOS transistor.

FIG. 6 is a schematic diagram showing a configuration of an image sensor according to the present invention.

FIG. 7 is a circuit diagram showing a conventional optical sensor circuit.

FIG. 8 is a graph showing a characteristic of a sensor current Id-a detection voltage Vd of a conventional optical sensor circuit.

FIG. 9 shows a detection voltage V of the optical sensor circuit of the related art and the present invention.
It is a graph which shows the time change of d.

FIG. 10 is a circuit diagram showing a configuration of a conventional optical sensor circuit.

FIG. 11 is a graph showing a temporal change of a gate voltage VG (a takeout signal) and a detection voltage Vd in the optical sensor circuits of the related art and the present invention.

FIG. 12 is a graph showing characteristics of a sensor current Id and a detection voltage Vd of the optical sensor circuits of the related art and the present invention.

FIG. 13 is a graph showing characteristics of a sensor current Id and an output voltage V0 of the optical sensor circuits of the related art and the present invention.

[Explanation of symbols]

10, 10 ', 10 "optical sensor circuit 50 image sensor C capacitor PS photogate type optical sensor (optical-electrical conversion means) Q1 enhancement type n-channel MOS transistor (conversion MOS transistor) Q2 enhancement type n-channel MOS transistor (amplification) MOS transistor) Q3 Enhancement type n-channel MOS transistor (selection MOS transistor)

Continued on front page (72) Inventor Katsuhiko Takebe 1-4-1 Chuo, Wako-shi, Saitama Pref. Honda Research Laboratory Co., Ltd. F-term in Technical Research Institute, Inc. (reference) 4M118 AA02 AA05 AB10 BA14 BA15 CA03 DD09 FA06 FA08 5C024 AA01 CA12 CA15 FA01 FA08 FA11 GA01 GA31 GA33

Claims (4)

[Claims] 1. An optical-to-electrical converter for converting an optical signal into a sensor current, and a conversion MOS for converting the sensor current converted by the optical-to-electrical converter into a detection voltage having a logarithmic characteristic in a weakly inverted state.
A transistor connected to a detection terminal of the conversion MOS transistor, and a capacitor connected to a detection terminal of the conversion MOS transistor. Initializing means for reducing the impedance of the capacitor and controlling the charging or discharging of the capacitor, wherein the photoelectric conversion means comprises a photogate type optical sensor, and a predetermined voltage is applied to the photogate of the photogate type optical sensor. A photogate voltage application unit for applying a voltage, and when the sensor current converted by the photoelectric conversion unit is a current equal to or less than a predetermined current, a detection voltage proportional to a charging current or a discharging current of the capacitor is detected. Having a linear response region, wherein the sensor current converted by the photoelectric conversion means corresponds to the predetermined current. If it is obtain current light sensor circuit, characterized in that it comprises a logarithmic response region for detecting a detection voltage having a logarithmic characteristic corresponding to a load characteristic of the conversion MOS transistor. 2. The optical sensor circuit according to claim 1, further comprising an amplification MOS transistor for amplifying and detecting a voltage signal at a detection terminal of the conversion MOS transistor to which the capacitor is connected. . 3. The conversion MOS transistor according to claim 1, further comprising a selection MOS transistor for setting a timing for detecting a voltage signal of a detection terminal of the conversion MOS transistor to which the capacitor is connected. Optical sensor circuit. 4. An image sensor comprising a plurality of optical sensor circuits according to claim 1 arranged in a one-dimensional or two-dimensional array.