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JP2000196240A - Stacked circuit board - Google Patents

Stacked circuit board

Info

Publication number
JP2000196240A
JP2000196240A JP36827598A JP36827598A JP2000196240A JP 2000196240 A JP2000196240 A JP 2000196240A JP 36827598 A JP36827598 A JP 36827598A JP 36827598 A JP36827598 A JP 36827598A JP 2000196240 A JP2000196240 A JP 2000196240A
Authority
JP
Japan
Prior art keywords
conductor
terminal electrode
layer
pattern
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36827598A
Other languages
Japanese (ja)
Inventor
Yoichi Makino
洋一 牧野
Akihiro Sakanoue
聡浩 坂ノ上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP36827598A priority Critical patent/JP2000196240A/en
Publication of JP2000196240A publication Critical patent/JP2000196240A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer circuit board which has excellent conduction reliability between an internal wiring layer and a terminal electrode, and can be miniaturized. SOLUTION: In a multilayer circuit board, a recessed part 51 extending in the thickness direction of a multilayer body 1 on an end of the body 1 in which insulation layers 1a to 1e and an internal wiring layer 3 are laminated, and a conductive layer 52 which is connected to the layer 3 and extends to the thickness direction of the inner wall surface of the recessed part 51 is exposed and formed, and moreover, an electrode terminal conductive film 53 is adhered and formed on the inner wall of a penetrating recessed part 51 including the layer 52.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層回路基板の端
面電極の構造に関するものである。
The present invention relates to a structure of an end face electrode of a laminated circuit board.

【0002】[0002]

【従来の技術】従来、積層回路基板は、複数の絶縁層を
積層し、積層体の層間に所定内部配線層が配置されて、
積層体を構成していた。また、積層体の表面には、所定
表面配線パターンが形成され、必要に応じて該表面配線
パターンには、ICチップ、電子部品素子、厚膜抵抗体
膜、コンデンサ膜、保護膜などが形成されていた。
2. Description of the Related Art Conventionally, a laminated circuit board has a structure in which a plurality of insulating layers are laminated, and a predetermined internal wiring layer is arranged between layers of the laminated body.
A laminate was formed. Further, a predetermined surface wiring pattern is formed on the surface of the laminate, and an IC chip, an electronic component element, a thick film resistor film, a capacitor film, a protective film, and the like are formed on the surface wiring pattern as necessary. I was

【0003】尚、積層体の内部には、所定内部配線層と
の間を接続したり、また、内部配線層と表面配線パター
ンとの間を接続したりするビアホール導体が形成されて
いた。
Incidentally, via-hole conductors for connecting between predetermined internal wiring layers and connecting between internal wiring layers and surface wiring patterns have been formed inside the laminate.

【0004】このような積層回路基板と外部のプリント
配線基板との接続は、端子電極によって導電部材を介し
て行なわれる。最も一般的には積層体の裏面に裏面端子
電極パッドを形成し、この裏面端子電極をプリント配線
基板の電極パッドとの間をハンダ接合する構造である。
[0004] The connection between such a laminated circuit board and an external printed wiring board is made via conductive members by terminal electrodes. Most commonly, a backside terminal electrode pad is formed on the backside of the laminate, and this backside terminal electrode is soldered to an electrode pad of a printed wiring board.

【0005】また、積層体の端面に、積層体の厚み方向
に延びる凹部を形成し、この凹部内に端面端子電極を形
成し、この端面端子電極をプリント配線基板の電極パッ
ドとの間をハンダ接合する構造である。
Further, a concave portion extending in the thickness direction of the laminate is formed on an end surface of the laminate, and an end terminal electrode is formed in the concave portion. A solder is provided between the end terminal electrode and an electrode pad of a printed wiring board. It is a structure to be joined.

【0006】例えば、特開平9−330991号公報
は、両者の端子電極が開示されており、特に、この特開
平9−330991号公報の技術は、端面側端子電極と
裏面側端子電極との積層体の外側面での導通信頼性を向
上させるために、積層体の内部で内部配線層とビアホー
ル導体とでも端面側端子電極と裏面側端子電極との積層
体の外側面での導通信頼性を向上させていた。
For example, Japanese Patent Application Laid-Open No. 9-330991 discloses both terminal electrodes. In particular, the technology disclosed in Japanese Patent Application Laid-Open No. 9-330991 discloses a technique of laminating an end face side terminal electrode and a back side terminal electrode. In order to improve the conduction reliability on the outer surface of the body, the internal wiring layer and the via hole conductor inside the laminate must also have the conduction reliability on the outer surface of the laminate of the end surface terminal electrode and the back surface terminal electrode. Had improved.

【0007】このうような端面電極は、積層体を構成す
るビアホール導体及び端子電極となる貫通孔を形成し、
且つ内部配線層となる導体膜が形成されたグリーンシー
トを複数積層し、所定焼成条件で焼成処理した後、端子
電極となる貫通孔の積層体表面の貫通孔の周囲及び貫通
孔の内壁面に導体膜を被着形成していた。
[0007] Such an end face electrode forms a through-hole serving as a via-hole conductor and a terminal electrode constituting a laminate, and
A plurality of green sheets on which a conductor film serving as an internal wiring layer is formed are laminated and fired under predetermined firing conditions. A conductive film was formed by deposition.

【0008】[0008]

【発明が解決しようとする課題】端面電極の内壁面の導
体膜と内部配線層との接続は、内部配線層が貫通孔の内
壁面から露出している電極層の厚みのみであった。この
ため、内部配線層と端子電極との導通信頼性を向上させ
るためには、貫通孔の周囲にランド電極パターンを形成
しておく必要があった。
The connection between the conductor film on the inner wall surface of the end face electrode and the internal wiring layer is limited to the thickness of the electrode layer whose internal wiring layer is exposed from the inner wall surface of the through hole. Therefore, in order to improve the reliability of conduction between the internal wiring layer and the terminal electrode, it is necessary to form a land electrode pattern around the through hole.

【0009】このように、貫通孔の周囲にランド電極パ
ターンを形成すると、この端子電極部分でのランド電極
パターンを含む内部配線層の専有面積が増加してしま
い、その結果、積層体基板の大型化になってしまう。
As described above, when the land electrode pattern is formed around the through hole, the occupied area of the internal wiring layer including the land electrode pattern at the terminal electrode portion increases, and as a result, the size of the laminate substrate becomes large. It will become.

【0010】このような積層回路基板は、内部配線層、
ビアホール導体を形成した絶縁性グリーンシートを所定
積層順序に応じて積層し、焼成して形成するが、ビアホ
ール導体となる貫通孔の加工ずれ、各グリーンシート上
に形成する内部配線層となる印刷パターンずれ、各グリ
ーンシートの積層ズレが生じた場合、ランド電極と貫通
孔内の導体膜、ランド電極と内部配線層との接続信頼性
が欠けてしまう。これは、同時に端子電極と内部配線層
との接続の信頼性の低下につながる。
[0010] Such a laminated circuit board has an internal wiring layer,
Insulating green sheets on which via-hole conductors are formed are laminated and fired according to a predetermined lamination order, but formed by firing. However, processing patterns of through holes serving as via-hole conductors and printing patterns serving as internal wiring layers formed on each green sheet are formed. If the stacking and the misalignment of the green sheets occur, the connection reliability between the land electrode and the conductor film in the through hole, and the connection between the land electrode and the internal wiring layer is lacked. This leads to a decrease in the reliability of the connection between the terminal electrode and the internal wiring layer.

【0011】本発明は上述の課題に鑑みて案出されたも
のであり、その目的は、内部配線層と端子電極との導通
信頼性に優れ、且つ小型化が可能な積層回路基板を提供
することにある。
The present invention has been devised in view of the above-mentioned problems, and an object of the present invention is to provide a laminated circuit board which is excellent in the reliability of conduction between an internal wiring layer and a terminal electrode and which can be miniaturized. It is in.

【0012】[0012]

【課題を解決するための手段】本発明によれば、絶縁層
と内部配線層とを積層して成る積層体の端面に、該積層
体の厚み方向を貫く端子電極用の凹部を形成し、該凹部
の内壁面に、前記内部配線層に接続し、且つ厚み方向に
延びる導体層を一部が露出するようにして埋設させると
ともに、凹部の内壁面に端子電極導体膜を被着形成させ
たことを特徴とする積層回路基板である。
According to the present invention, a concave portion for a terminal electrode is formed in an end face of a laminated body formed by laminating an insulating layer and an internal wiring layer, the concave portion penetrating in the thickness direction of the laminated body. A conductor layer connected to the internal wiring layer and extending in the thickness direction was buried on the inner wall surface of the recess so as to partially expose the terminal layer, and a terminal electrode conductor film was formed on the inner wall surface of the recess. A laminated circuit board characterized by the above.

【0013】層体の厚み方向を貫く端子電極用貫通凹部
を形成するとともに、前記貫通凹部の内壁面に、該内部
配線層に接続し、且つ貫通凹部の内壁面の厚み方向に延
びるビアホール導体が露出形成し、該ビアホール導体を
含む該貫通孔の内壁面を端子電極導体膜を被着形成して
成ることを特徴とする積層回路基板である。
A through recess for a terminal electrode is formed through the thickness of the layered body, and a via hole conductor connected to the internal wiring layer and extending in the thickness direction of the inner wall of the through recess is formed on the inner wall surface of the through recess. A laminated circuit board, which is formed by exposing a terminal electrode conductor film on an inner wall surface of the through hole including the via hole conductor.

【0014】[0014]

【作用】以上のように、本発明では積層体の端面には端
子電極となる端子電極用凹部が形成され、その内壁面に
は積層体の厚み方向に延び、且つ内部配線層と接続する
導体層の一部が露出するように埋設されている。このよ
うに、導体層の一部が露出している内壁面に端子電極導
体膜が形成されているため、各グリーンシートで印刷ず
れ、積層ずれが発生しても、端子電極(端子電極導体
膜)と内部配線層との導通信頼性が安定する。
As described above, according to the present invention, a terminal electrode concave portion serving as a terminal electrode is formed on the end surface of the laminate, and a conductor extending in the thickness direction of the laminate and connected to the internal wiring layer is formed on the inner wall surface. It is buried so that part of the layer is exposed. As described above, since the terminal electrode conductor film is formed on the inner wall surface where a part of the conductor layer is exposed, even if printing misalignment or lamination misalignment occurs in each green sheet, the terminal electrode (terminal electrode conductor film). ) And the internal wiring layer have stable conduction reliability.

【0015】この貫通用凹部の内壁面に露出する導体層
の一部が形成されており、グリーンシートに内部配線層
となる導体膜と実質的に同一の工程で形成されるため、
内部配線層と導体層との接続が確実に行なわれることに
起因する。
A portion of the conductor layer exposed on the inner wall surface of the through recess is formed and formed on the green sheet in substantially the same process as the conductor film serving as the internal wiring layer.
This is because the connection between the internal wiring layer and the conductor layer is reliably performed.

【0016】[0016]

【発明の実施の形態】以下、本発明の積層回路基板を図
面に基づいて詳説する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a laminated circuit board according to the present invention will be described in detail with reference to the drawings.

【0017】図1は本発明の積層回路基板の外観斜視図
であり、図2は図1中のA−A線で示す部分断面図であ
り、図3は端子電極の端子電極導体膜を省略した状態の
端子電極部分斜視図である。
FIG. 1 is an external perspective view of a laminated circuit board according to the present invention, FIG. 2 is a partial sectional view taken along line AA in FIG. 1, and FIG. 3 omits a terminal electrode conductor film of a terminal electrode. It is a partial perspective view of the terminal electrode of the state which carried out.

【0018】図1において、10は回路基板であり、1
は積層体、2は積層体1の表面に形成した表面導体パタ
ーン、3は積層体1内の形成された内部配線層(内部導
体パターン)、4は積層体1内の形成されたビアホール
導体、5は積層体1の端面に形成された端子電極であ
り、6は電子部品である。
In FIG. 1, reference numeral 10 denotes a circuit board,
Is a surface conductor pattern formed on the surface of the laminate 1, 3 is an internal wiring layer (internal conductor pattern) formed in the laminate 1, 4 is a via-hole conductor formed in the laminate 1, Reference numeral 5 denotes a terminal electrode formed on the end face of the laminate 1, and reference numeral 6 denotes an electronic component.

【0019】端子電極5は、図2に示すように積層体1
の端面の厚み方向に延びる凹部51とこの凹部51の内
壁面に、その一部が露出する複数の導体層52・・・、
端子電極導体膜53、メッキ層54とから構成されてい
る。
The terminal electrode 5 is, as shown in FIG.
A plurality of conductor layers 52, a part of which is exposed on the inner wall surface of the recess 51 extending in the thickness direction of the end face of the recess 51,
It comprises a terminal electrode conductor film 53 and a plating layer.

【0020】積層体1は、絶縁層1a〜1eが積層され
て構成されている。その材料は、例えば、アルミナを主
成分とする材料からなる。また、内部導体パターン3に
材料によって、例えば、低温焼成(800〜1050
℃)で焼成可能な材料、例えばアルミナ粉末、誘電体セ
ラミック粉末、磁性体材料(広義にセラミック)粉末な
どの粒体の周囲に結晶化ガラス成分が存在するガラス−
セラミック材料などが例できる。
The laminate 1 is configured by laminating insulating layers 1a to 1e. The material is, for example, a material containing alumina as a main component. Further, depending on the material of the internal conductor pattern 3, for example, low-temperature firing (800 to 1050)
C), for example, a glass in which a crystallized glass component exists around granules such as alumina powder, dielectric ceramic powder, and magnetic material (ceramic in a broad sense) powder.
Examples include ceramic materials.

【0021】絶縁層1a〜1eの各層間には、所定回路
網を達成し、また必要に応じて容量成分、インダクタ成
分を発生するための内部導体パターン3が配置されてい
る。
Between each of the insulating layers 1a to 1e, an internal conductor pattern 3 for achieving a predetermined circuit network and generating a capacitance component and an inductor component as required is arranged.

【0022】また、絶縁層1a〜1eには、その層の厚
み方向を貫くビアホール導体4が形成されている。
Further, via-hole conductors 4 are formed in the insulating layers 1a to 1e so as to extend through the thickness direction of the layers.

【0023】内部導体パターン3、ビアホール導体4
は、W系、Mo系、Ag系(Ag単体、Ag−Pdなど
のAg合金)、Cu系など導体膜(導体)からなり、内
部導体パターン3の厚みは8〜15μm程度であり、ビ
アホール導体4の直径は任意な値とすることができる
が、例えば直径は80〜250μmである。
Internal conductor pattern 3, via-hole conductor 4
Is composed of a conductor film (conductor) such as W-based, Mo-based, Ag-based (Ag alone (Ag alloy such as Ag-Pd)), Cu-based, etc., and the thickness of the internal conductor pattern 3 is about 8 to 15 μm. The diameter of 4 can be any value, for example, the diameter is 80 to 250 μm.

【0024】また、このような構造の積層体1の表面に
は、表面導体パターン2が形成されている。表面導体パ
ターン2は、Au系(Au単体、Au−Pt、Au−P
dななどのAu合金)、Ag系(Ag単体、Ag−Pd
などAg合金)、Cu系(Cu単体やCu合金)導体膜
からなっている。表面線導体パターン2は、積層体1の
表面の回路配線を構成するとともに、半田を介して接合
される電子部品6の接続パッドを構成したり、また、厚
膜抵抗膜、厚膜コンデンサ素子の端子電極を構成したり
する。
A surface conductor pattern 2 is formed on the surface of the laminate 1 having such a structure. The surface conductor pattern 2 is made of Au (Au alone, Au-Pt, Au-P
Au alloy such as d-type), Ag-based (Ag alone, Ag-Pd)
Ag alloy) and Cu-based (Cu simple substance or Cu alloy) conductive film. The surface line conductor pattern 2 constitutes a circuit wiring on the surface of the laminate 1 and also constitutes a connection pad of an electronic component 6 to be joined via solder, and also forms a thick film resistive film and a thick film capacitor element. Or configure terminal electrodes.

【0025】また、積層体回路基板10の端面には端子
電極5が形成されている。端子電極5は、積層体1の端
面の厚み方向に延びる凹部51とこの凹部51の内壁面
に、その端面が露出する複数の導体層52・・・、端子
電極導体膜53、メッキ層54とから構成されている。
A terminal electrode 5 is formed on an end face of the multilayer circuit board 10. The terminal electrode 5 includes a concave portion 51 extending in the thickness direction of the end surface of the laminated body 1, a plurality of conductor layers 52... With the end surface exposed on the inner wall surface of the concave portion 51, a terminal electrode conductive film 53, and a plating layer 54. It is composed of

【0026】凹部51は、図3に示すように、積層体1
の端面に形成した厚み方向に延びるように形成さされ
る。この凹部51は、積層体1 の表面の開口形状が概略
半円形状または半長円形状(図では半円形状)となって
いる。
As shown in FIG. 3, the concave portion 51
Is formed so as to extend in the thickness direction formed on the end face. The concave portion 51 has a substantially semicircular or semi-elliptical opening (semicircular in the figure) in the opening shape on the surface of the laminate 1.

【0027】そして、導体層52は、凹部51の内壁面
に1個もしくは複数形成され、その一部、即ち、導体層
52の積層体1の厚み方向に延びる面が、凹部51の内
壁面に露出している。これらの導体層52は、積層体1
の全絶縁層1a〜1eに渡って形成してもよい、また、
任意の絶縁層のみに形成し、全体として断続的としても
よい。尚、図では、3つの導体層52が各々全絶縁層1
a〜1eに連続するように形成されている。各々導体層
52は凹部51の内壁面に同一位置または千鳥状の位置
関係でもよい。
One or more conductor layers 52 are formed on the inner wall surface of the recess 51, and a part of the conductor layer 52, that is, the surface of the conductor layer 52 extending in the thickness direction of the laminate 1 is formed on the inner wall surface of the recess 51. It is exposed. These conductor layers 52 are made of the laminate 1
May be formed over all the insulating layers 1a to 1e.
It may be formed only on an arbitrary insulating layer and may be intermittent as a whole. In the figure, the three conductor layers 52 are all formed of the entire insulating layer 1.
It is formed so as to continue from a to 1e. Each of the conductor layers 52 may have the same position or a staggered positional relationship on the inner wall surface of the concave portion 51.

【0028】即ち、凹部51の内壁面と導体層52との
関係により、導体層52の平面形状は、概略円形状、楕
円形状もしくは矩形状の一部が円弧状に欠けた形状とな
る。
That is, due to the relationship between the inner wall surface of the concave portion 51 and the conductor layer 52, the plane shape of the conductor layer 52 is substantially circular, elliptical, or a shape in which a part of a rectangle is cut off in an arc shape.

【0029】この導体層52の積層体1側の絶縁層1a
〜1eの層間には、導体層52の周囲に形成されたラン
ド電極パターン55が形成されている。
The insulating layer 1a of the conductor layer 52 on the laminate 1 side
A land electrode pattern 55 formed around the conductor layer 52 is formed between the layers 1 to 1e.

【0030】導体パターン3に接続され、内部導体パタ
ーン53を端子電極5に安定的に導出するものであり、
且つ、各絶縁層1a〜1eの凹部51の内壁面に沿って
形成された導体層52どうしを安定して接続するための
ものである。
The inner conductor pattern 53 is connected to the conductor pattern 3 to stably lead the inner conductor pattern 53 to the terminal electrode 5.
Further, it is for stably connecting the conductor layers 52 formed along the inner wall surface of the concave portion 51 of each of the insulating layers 1a to 1e.

【0031】また、凹部51の内壁面表面に、この内壁
面に露出する導体層52を覆うように端子電極導体膜5
3が被着されており、さらに、必要に応じてその表面に
メッキ層54が被着形成されている。
The terminal electrode conductor film 5 is formed on the inner wall surface of the recess 51 so as to cover the conductor layer 52 exposed on the inner wall surface.
3, and a plating layer 54 is formed on the surface thereof as required.

【0032】導体層52、ランド電極パターン55は、
内部導体パターン3やビアホール導体4と同一の材料で
構成されている。また、端子電極導体膜53も、積層体
1の焼成処理で一括的に焼き付け可能なAg系(Ag単
体、Ag−PdなどのAg合金)、Cu系で構成するこ
とが望ましい。
The conductor layer 52 and the land electrode pattern 55
It is made of the same material as the internal conductor pattern 3 and the via-hole conductor 4. The terminal electrode conductor film 53 is also preferably made of an Ag-based material (Ag alone, an Ag alloy such as Ag-Pd) or a Cu-based material that can be baked at a time in the firing process of the laminate 1.

【0033】また、メッキ層54は、プリント配線基板
にハンダ接合した時に、端子電極導体膜53のはんだ食
われを防止して、ハンダ塗れ性を向上させるものであ
る。
The plating layer 54 prevents solder erosion of the terminal electrode conductor film 53 when solder-bonded to a printed wiring board, and improves solderability.

【0034】例えば、端子電極導体膜53をAg系導体
膜で構成した場合には、メッキ層54は、Niメッキ、
ハンダ(錫)メッキなどの順に被着して形成され、端子
電極導体膜53をCu系、タングステン系やモリブデン
系で形成した場合には、メッキ層54は、Niメッキ、
Auメッキなどの順に被着して形成される。
For example, when the terminal electrode conductor film 53 is made of an Ag-based conductor film, the plating layer 54 is formed by Ni plating,
When the terminal electrode conductor film 53 is formed of Cu, tungsten, or molybdenum, the plating layer 54 is formed of Ni plating,
It is formed by being applied in the order of Au plating or the like.

【0035】上述の構成の積層回路基板10において
は、積層体1の内部導体パターン3と端子電極5との電
気的な接続信頼性が著しく向上する。
In the laminated circuit board 10 having the above configuration, the reliability of the electrical connection between the internal conductor pattern 3 of the laminate 1 and the terminal electrode 5 is significantly improved.

【0036】これは、内部導体パターン3がランド電極
パターン55を介して、端子電極5に導出されるためで
ある。また、端子電極5の端子電極導体膜53が、ラン
ド電極パターン55間を厚み方向に接続し、その一部が
凹部51の内壁面に露出する導体層52を覆うように形
成されていることに起因する。
This is because the internal conductor pattern 3 is led out to the terminal electrode 5 via the land electrode pattern 55. In addition, the terminal electrode conductor film 53 of the terminal electrode 5 connects the land electrode patterns 55 in the thickness direction and is formed so as to partially cover the conductor layer 52 exposed on the inner wall surface of the concave portion 51. to cause.

【0037】以上のように、内部導体パターン3は、内
部導体パターン3の厚みに相当するランド電極パターン
55の膜厚に加え、導体層52の厚み方向の露出部分
(厚み方向の距離×露出幅)で、端子電極5の端子電極
導体膜53に接続するため端子電極5と内部導体パター
ン3との電気的な接続信頼性が飛躍的に向上する。
As described above, in addition to the thickness of the land electrode pattern 55 corresponding to the thickness of the internal conductor pattern 3, the internal conductor pattern 3 has an exposed portion in the thickness direction of the conductor layer 52 (distance in the thickness direction × exposed width). ), The reliability of the electrical connection between the terminal electrode 5 and the internal conductor pattern 3 is greatly improved because the terminal electrode 5 is connected to the terminal electrode conductor film 53.

【0038】また、1つの端子電極5の凹部51に複数
の導体層52を形成するとともに、例えばある1つの導
体層52を、その円筒状の略中央部分が凹部51の内壁
面が横切るような位置に形成し、また、ある1つの導体
層52を、凹部51の内壁面によって、その一部に小さ
な円弧状の切り欠けとなるような位置に形成し、さら
に、ある1つの導体層52を、凹部51の内壁面によっ
て、その一部に大きな円弧状の切り欠けとなるような位
置に形成する。
In addition, a plurality of conductor layers 52 are formed in the recess 51 of one terminal electrode 5, and, for example, a certain conductor layer 52 is formed so that a substantially central portion of a cylindrical shape of the conductor layer 52 crosses the inner wall surface of the recess 51. Position, and a certain conductor layer 52 is formed at a position where a small arc-shaped notch is formed in a part thereof by the inner wall surface of the concave portion 51, and further, a certain conductor layer 52 is formed. The inner wall surface of the concave portion 51 is formed at a position where a large arc-shaped notch is formed in a part thereof.

【0039】即ち、1つのランド電極パターン55に、
異なる円周上に複数の導体層52を配置するようにす
る。
That is, in one land electrode pattern 55,
A plurality of conductor layers 52 are arranged on different circumferences.

【0040】これにより、製造工程中に凹部51の形成
位置が若干位置ずれても、また、導体層52の形成位置
が若干位置ずれても凹部51の内壁面から確実に少なく
とも1つの導体層52を露出することができき、非常に
高い接続信頼性が維持できる。
Thus, even if the formation position of the concave portion 51 is slightly displaced during the manufacturing process, or if the formation position of the conductive layer 52 is slightly displaced, at least one conductive layer 52 is surely removed from the inner wall surface of the concave portion 51. Can be exposed, and very high connection reliability can be maintained.

【0041】次に、本発明の積層回路基板の製造方法
を、特に、端子電極5の形成部分に着目して説明する。
尚、説明では、大型グリーンシート積層方法を用いた製
造方法で説明するとともに、特に、図1の積層体1の
内、絶縁層1cとなるグリーンシート10c部分の平面
図で説明する。
Next, the method for manufacturing a laminated circuit board according to the present invention will be described, focusing particularly on the portion where the terminal electrode 5 is formed.
In the description, the manufacturing method using the large-sized green sheet laminating method will be described, and in particular, the plan view of the green sheet 10c that becomes the insulating layer 1c in the laminated body 1 of FIG. 1 will be described.

【0042】まず、絶縁層1a〜1eとなる大型セラミ
ック(またはガラスセラミック)グリーンシート用意す
る。
First, a large ceramic (or glass ceramic) green sheet to be used as the insulating layers 1a to 1e is prepared.

【0043】次に、各グリーンシートに通常の回路網を
形成するビアホール導体となる貫通孔をNCパンチング
処理により形成する。図4(a)に示すグリーンシート
10cにおいて、回路網を形成するビアホール導体4と
なる貫通孔を40で、端子電極5部分の導体層52とな
る貫通孔を56で示している。尚、貫通孔56の直径は
例えば0.15〜0.3mmであり、境界部分を点線x
で示す。
Next, a through-hole serving as a via-hole conductor for forming a normal circuit network is formed in each green sheet by NC punching. In the green sheet 10c shown in FIG. 4A, reference numeral 40 denotes a through hole serving as a via hole conductor 4 forming a circuit network, and reference numeral 56 denotes a through hole serving as a conductor layer 52 of the terminal electrode 5 portion. The diameter of the through hole 56 is, for example, 0.15 to 0.3 mm, and the boundary portion is indicated by a dotted line x.
Indicated by

【0044】次に、各グリーンシートの貫通孔に所定導
電性ペーストの印刷・充填により、貫通孔に導体を充填
するとともに、各グリーンシート上にランド電極パター
ンを含む内部導体パターンを含む導体膜を形成する。図
4(b)に示すグリーンシート10cでは、貫通孔40
に充填した導体を4’で、貫通孔56に充填した導体を
52’で、また、ランド電極パターン55となる導体膜
を55’で,内部導体パターン3となる導体膜を3’で
示している。この工程により、各グリーンシートに形成
される内部導体パターン3となる導体膜3’は、ランド
電極パターン55となる導体膜55’、ビアホール導体
4となる導体4’、導体層52となる導体52’は各々
一体的に形成されており、それらの接続信頼性が非常に
向上する。
Next, a conductor is filled into the through holes by printing and filling a predetermined conductive paste into the through holes of each green sheet, and a conductor film including an internal conductor pattern including a land electrode pattern is formed on each green sheet. Form. In the green sheet 10c shown in FIG.
The conductor filled in the through hole 56 is denoted by 4 ', the conductor filled in the through hole 56 is denoted by 52', the conductor film serving as the land electrode pattern 55 is denoted by 55 ', and the conductor film serving as the internal conductor pattern 3 is denoted by 3'. I have. By this step, the conductor film 3 ′ serving as the internal conductor pattern 3 formed on each green sheet is made up of the conductor film 55 ′ serving as the land electrode pattern 55, the conductor 4 ′ serving as the via hole conductor 4, and the conductor 52 serving as the conductor layer 52 Are integrally formed, and their connection reliability is greatly improved.

【0045】次に、端子電極5となる凹部51となる打
ち抜き加工孔を形成する。図4(c)でこの打ち抜き加
工孔を50で示す。打ち抜き加工孔50は、境界部線x
を跨ぎ、また、ランド電極パターン55となる導体膜5
5’及び導体層52の導体の一部が打ち抜き加工孔50
の内面から露出するように形成する。
Next, a punched hole serving as the concave portion 51 serving as the terminal electrode 5 is formed. In FIG. 4C, this punched hole is indicated by 50. The punched hole 50 has a boundary line x
Conductor film 5 that straddles and becomes the land electrode pattern 55
5 ′ and a part of the conductor of the conductor layer 52 are formed by punching holes 50.
It is formed so as to be exposed from the inner surface.

【0046】この打ち抜き加工孔50の開口径は、例え
ば概略0.4〜2.0mmである。
The opening diameter of the punched hole 50 is, for example, approximately 0.4 to 2.0 mm.

【0047】尚、上述したように、複数の導体層52と
なる導体を、この加工孔50の外周となる線上に、千鳥
状に形成することが望ましい。これにより、導体層52
の導体は、加工孔50の内壁面に埋設された状態とな
る。
As described above, it is desirable that the conductors that become the plurality of conductor layers 52 be formed in a zigzag pattern on the line that is the outer periphery of the processing hole 50. Thereby, the conductor layer 52
Are buried in the inner wall surface of the processing hole 50.

【0048】次に、各グリーンシートの打ち抜き加工孔
の内壁面に、導電性ペーストの印刷により、端子電極導
体膜53となる導体膜を塗布する。具体的には、加工孔
50の内壁面への導電性ペーストの塗布は、その自重に
より簡単に形成することができる。尚、この端子電極導
体膜53となる導体膜の印刷に際しては、開口に比較し
てひと回り大きな印刷可能領域の製版を用いるため、上
述のランド電極パターン55の形成を省略することがで
きる。また、端子電極導体膜53となる導体膜の形成に
あたり、グリーンシートの両主面側から印刷するため、
内部導体パターン3が形成された一方主面側にも、開口
の周囲に導体膜が形成されることになる。従って、この
グリーンシートを積層した時、隣接するグリーンシート
の一方主面側のランド電極パターン55となる導体膜と
との電気的な接続が確実に行なえることになる。
Next, a conductive film to be the terminal electrode conductive film 53 is applied to the inner wall surface of the punched hole of each green sheet by printing a conductive paste. Specifically, application of the conductive paste to the inner wall surface of the processing hole 50 can be easily formed by its own weight. When printing the conductor film to be the terminal electrode conductor film 53, the plate making of a printable area slightly larger than the opening is used, so that the formation of the land electrode pattern 55 can be omitted. In forming the conductor film to be the terminal electrode conductor film 53, printing is performed from both main surfaces of the green sheet.
A conductor film is formed around the opening also on one main surface side on which the internal conductor pattern 3 is formed. Therefore, when the green sheets are stacked, electrical connection with the conductor film serving as the land electrode pattern 55 on one main surface side of the adjacent green sheet can be reliably performed.

【0049】次に、このようにビアホール導体4となる
導体、導体層52となる導体、内部導体パターン3、ラ
ンド電極パターン55、端子電極導体膜53となる導体
膜が形成された絶縁層1a〜1eとなるグリーンシート
を積層し、圧着一体化して、未焼成状態の大型積層体を
形成する。
Next, the insulating layer 1a to the conductor layer serving as the via hole conductor 4, the conductor layer 52, the internal conductor pattern 3, the land electrode pattern 55, and the terminal electrode conductor film 53 are formed. The green sheets to be 1e are laminated and pressure-bonded and integrated to form an unfired large-sized laminate.

【0050】尚、最外層となる絶縁層1e、1eのグリ
ーンシートに関しては、内部導体パターン3となる導体
膜の変わりに、必要に応じて表面導体パターン2となる
導体膜を形成しても構わない。
As for the green sheets of the insulating layers 1e and 1e as the outermost layers, a conductor film as the surface conductor pattern 2 may be formed as necessary instead of the conductor film as the internal conductor pattern 3. Absent.

【0051】次に、この大型未焼成状態のこの積層体を
各回路基板の形状に応じて、分割溝を形成したり、また
は、切断を行なう。例えば、切断することにより、加工
孔50は、2分割されて、端子電極5の凹部51とな
る。
Next, according to the shape of each circuit board, a division groove is formed or the large unfired laminate is cut or cut. For example, by cutting, the processing hole 50 is divided into two and becomes the concave portion 51 of the terminal electrode 5.

【0052】次に、未焼成状態の積層体を焼成処理を行
なう。これにより、端子電極5部分に、導体層52、ラ
ンド電極パターン55、端子電極導体膜53を有すると
ともに、ビアホール導体4、内部導体パターン3、表面
導体パターン2を有する積層体1が達成される。この状
態における絶縁層1cの表面状態を図4(d)に示す。
Next, a firing process is performed on the unfired laminate. As a result, a laminate 1 having the conductor layer 52, the land electrode pattern 55, and the terminal electrode conductor film 53 in the terminal electrode 5 portion, and having the via hole conductor 4, the internal conductor pattern 3, and the surface conductor pattern 2 is achieved. FIG. 4D shows the surface state of the insulating layer 1c in this state.

【0053】その後、必要応じて表面導体パターン2を
導電性ペーストの印刷焼き付けにより形成し、上述の工
程で分割溝を形成した場合に、個々の回路基板の形状に
分割処理を行ない、その後、積層体1の端子電極導体膜
53の表面に、メッキ処理して表面メッキ層54を形成
し、また、表面導体パターン2に電子部品6を搭載す
る。これにより、図1に示す積層体1が完成する。
After that, if necessary, the surface conductor pattern 2 is formed by printing and baking a conductive paste, and when the dividing grooves are formed in the above-described steps, a dividing process is performed on the shape of each circuit board. The surface of the terminal electrode conductor film 53 of the body 1 is plated to form a surface plating layer 54, and the electronic component 6 is mounted on the surface conductor pattern 2. Thereby, the laminate 1 shown in FIG. 1 is completed.

【0054】本発明の製造方法では、導体層52となる
導体が、積層体の厚み方向に、分割または切断されて凹
部51となる貫通孔55に完全に露出または一部露出す
るようになっており、さらに、その凹部51の内壁面に
端子電極導体膜53が形成されている。従って、上述の
ように端子電極導体膜53とランド電極パターン55を
含む内部導体パターン3との接続部分が、導体層52の
厚み方向に渡って行なわれるため、その接続信頼性が向
上にする。
According to the manufacturing method of the present invention, the conductor to be the conductor layer 52 is divided or cut in the thickness direction of the laminate so that the conductor is completely exposed or partially exposed to the through hole 55 that becomes the recess 51. Further, a terminal electrode conductor film 53 is formed on the inner wall surface of the concave portion 51. Therefore, as described above, the connection between the terminal electrode conductor film 53 and the internal conductor pattern 3 including the land electrode pattern 55 is made in the thickness direction of the conductor layer 52, so that the connection reliability is improved.

【0055】また、積層回路基板10の製造方法におい
て避けることのできない、グリーンシート上の導体膜の
印刷ずれ、シートの積層ずれ、また、貫通孔の形成ずれ
が発生したとしても、導体層52は、各絶縁層1a〜1
eのランド電極パターン55に接続されているため、端
子電極5の端子導体導体膜53の積層による開放状態を
回避でき、接続信頼性が大きく向上する。
Also, even if printing misalignment of the conductor film on the green sheet, sheet lamination misalignment, or formation misalignment of the through-hole, which cannot be avoided in the method of manufacturing the laminated circuit board 10, occurs, the conductor layer 52 remains , Each insulating layer 1a-1
Since the terminal electrode 5 is connected to the land electrode pattern 55, the open state due to the lamination of the terminal conductor conductor film 53 of the terminal electrode 5 can be avoided, and the connection reliability is greatly improved.

【0056】尚、上述の製造方法では、各グリーンシー
トの状態で、端子電極5の凹部51となる加工孔50を
形成したが、導体層52、ランド電極パターン55を形
成した各グリーンシートを積層一体化した後、絶縁層1
a〜1eとなるグリーンシートの積層体を一括的に端子
電極5の凹部51となる加工孔50を形成し、その後、
端子電極導体膜53となる導体膜を導電性ペーストの塗
布により形成しても構わない。
In the above-described manufacturing method, the processing hole 50 which becomes the concave portion 51 of the terminal electrode 5 is formed in each green sheet, but the green sheets on which the conductor layer 52 and the land electrode pattern 55 are formed are laminated. After integration, the insulating layer 1
A processing hole 50 which becomes the concave portion 51 of the terminal electrode 5 is formed in a lump of the green sheet laminates a to 1e.
The conductor film serving as the terminal electrode conductor film 53 may be formed by applying a conductive paste.

【0057】また、上述の製造方法では、グリーンシー
ト多層方法で形成したが、導電性ペーストと絶縁ペース
トとの印刷多層により、積層体を形成しても構わない。
In the above-described manufacturing method, the green sheet is formed by a multilayer method. However, a laminate may be formed by printing multiple layers of a conductive paste and an insulating paste.

【0058】上述の説明では、5層の絶縁層が積層され
た積層回路基板10で説明したが、絶縁層の総数は任意
に変えることができ、また、絶縁層の材料も、各導体膜
の材料も任意に変えることもできる。さらにビアホール
導体の形状、貫通孔の形状は任意に変えることができ
る。
In the above description, the laminated circuit board 10 in which five insulating layers are stacked has been described. However, the total number of insulating layers can be changed arbitrarily. Materials can also be changed arbitrarily. Further, the shape of the via hole conductor and the shape of the through hole can be arbitrarily changed.

【0059】[0059]

【発明の効果】本発明によれば、端子電極の凹部の内壁
面に、この内壁面に露出するビアホール導体が形成され
ている。これにより、端子電極と内部導体パターンとの
接続が、従来の平面的な接続に加え、積層体の厚み方向
での接続が付加されることにより、端子電極と内部導体
パターンとの接続信頼性が飛躍的に向上する。
According to the present invention, the via-hole conductor exposed on the inner wall surface is formed on the inner wall surface of the concave portion of the terminal electrode. As a result, the connection reliability between the terminal electrode and the internal conductor pattern is improved by adding the connection in the thickness direction of the laminate to the connection between the terminal electrode and the internal conductor pattern in addition to the conventional planar connection. Improve dramatically.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の積層回路基板の斜視図である。FIG. 1 is a perspective view of a laminated circuit board according to the present invention.

【図2】本発明の積層回路基板のA−A線断面図であ
る。
FIG. 2 is a sectional view taken along line AA of the laminated circuit board of the present invention.

【図3】本発明の積層回路基板の端子電極部分の端子電
極導体膜を省略した斜視図である。
FIG. 3 is a perspective view of the laminated circuit board of the present invention in which a terminal electrode conductor film in a terminal electrode portion is omitted.

【図4】(a)〜(d)は、本発明の積層回路基板の製
造方法を説明する部分平面図である。
FIGS. 4A to 4D are partial plan views illustrating a method for manufacturing a laminated circuit board according to the present invention.

【符号の説明】[Explanation of symbols]

10 ・・・・・ 回路基板 1・・・・・ 積層体 1a〜1e・・・ 絶縁層 2・・・表面導体パターン 3・・・内部導体パターン 4・・・ビアホール導体 5・・・端子電極 51・・・凹部 52・・・ビアホール導体 53・・・端子電極導体膜 54・・・メッキ層 55・・・ランド電極パターン 10 Circuit board 1 Laminated body 1a-1e Insulating layer 2 Surface conductor pattern 3 Internal conductor pattern 4 Via-hole conductor 5 Terminal electrode 51 ... concave part 52 ... via hole conductor 53 ... terminal electrode conductor film 54 ... plating layer 55 ... land electrode pattern

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA01 AA07 AA22 AA24 BB12 BB13 BB14 BB15 BB16 BB17 BB18 CC05 CC15 CC31 CD27 CD32 5E346 AA42 AA43 BB11 CC16 CC32 CC35 CC36 CC39 CC40 DD22 EE29 FF04 FF07 FF09 FF10 FF18 FF22 GG15 GG19 HH07 HH22  ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5E317 AA01 AA07 AA22 AA24 BB12 BB13 BB14 BB15 BB16 BB17 BB18 CC05 CC15 CC31 CD27 CD32 5E346 AA42 AA43 BB11 CC16 CC32 CC35 CC36 CC39 CC40 DD22 EE29 FF04 FF07 FF19 FF10 FF07 FF10 HH22

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁層と内部配線層とを積層して成る積
層体の端面に、該積層体の厚み方向を貫く端子電極用の
凹部を形成し、該凹部の内壁面に、前記内部配線層に接
続し、且つ厚み方向に延びる導体層を一部が露出するよ
うにして埋設させるとともに、凹部の内壁面に端子電極
導体膜を被着形成させたことを特徴とする積層回路基
板。
1. A concave portion for a terminal electrode penetrating in a thickness direction of the laminated body is formed on an end surface of a laminated body formed by laminating an insulating layer and an internal wiring layer, and the internal wiring is formed on an inner wall surface of the concave portion. A laminated circuit board, wherein a conductor layer connected to a layer and extending in a thickness direction is buried so as to partially expose the terminal layer, and a terminal electrode conductor film is formed on the inner wall surface of the concave portion.
JP36827598A 1998-12-24 1998-12-24 Stacked circuit board Pending JP2000196240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36827598A JP2000196240A (en) 1998-12-24 1998-12-24 Stacked circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36827598A JP2000196240A (en) 1998-12-24 1998-12-24 Stacked circuit board

Publications (1)

Publication Number Publication Date
JP2000196240A true JP2000196240A (en) 2000-07-14

Family

ID=18491409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36827598A Pending JP2000196240A (en) 1998-12-24 1998-12-24 Stacked circuit board

Country Status (1)

Country Link
JP (1) JP2000196240A (en)

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