JP2000188593A - Multiple address distribution transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitter that can make communication with a plurality of receivers even when transmission rates of them connecting to the transmitter are different. SOLUTION: The transmitter 1 that transmits a consecutive signal consisting of a 1st frame at a basic transfer rate including a frame synchronization bit, transfer rate and phase information and frames at a transfer rate being an integer multiple of the basic transfer rate consisting of a data area, detects a destination recorded in input data, stores the input data to a buffer memory for each destination, reads the data when the capacity of the data is a prescribed capacity or over and transmits the data after ORing the output of the read buffer memory and the basic transfer rate frame. Each of receivers 3-1-3-n reproduces timing from a change point of the input data to take frame synchronization in the input data, detects the transfer rate and phase information in the input data, decides a head position of the received data in frames and separates and receives the signal at the same transfer rate as that of the concerned receiver from the consecutive signal consisting of frames at different speeds.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a broadcast distribution apparatus for transmitting and receiving transmission signals of different speeds in a one-to-n one-way communication system.

[0002]

2. Description of the Related Art FIGS. 10 and 11 show burst transmissions described in B-833, "Transmission frame configuration method in ATM-PDS system", published in the IEICE Spring Conference, March 10, 1994. FIG. 1 shows a system diagram and a schematic configuration diagram of a burst signal.

In recent years, it has been proposed to use an optical fiber for a subscriber transmission line. As shown in FIG. 10, an optical fiber connected to an optical line terminal 101 is connected to an optical star coupler 102 through the optical transmission line in the subscriber transmission line. : An n-branch configuration is used, and the branched optical fibers are connected to the subscriber units 103-1 to 103-n to form a system.

Here, for example, burst signals # 1a to #na from the optical line terminal 101 to the optical line terminals 103-1 to 103-n are transmitted.
The data is multiplexed and transmitted by the TDMA method. On the other hand, each of the subscriber units 103-1 to 103-n transmits a burst signal # 1b, # 2b,..., #Nb in a predetermined time slot. At this time,
These burst signals are combined by the optical star coupler 102 and transmitted to the optical line terminal 101 via one optical fiber, and the optical line terminal 101 performs bit synchronization of data for each burst by an internal burst synchronization circuit. Receive.

Here, if the signal direction from the optical line terminal 101 to the subscriber side devices 103-1 to 103-n is the down direction and the reverse is the up direction, the transmission speeds in the down direction are the same.
Therefore, the speed of each of the subscriber-side devices 103-1 to 103-n has to be the same for all the systems. Further, since the transmission speeds in the upstream direction are the same, the burst synchronization circuit of the optical line terminal 101 only needs to be operable at the same speed.

As shown in FIG. 11, the burst signal format includes a guard time part, a preamble part, a delimiter part, and a data area. In the guard time part, a pattern of all {0} is inserted so that each burst signal is not continuous. Is done. The preamble part is for sampling clock extraction.
10 alternation patterns are inserted. In the delimiter, a pattern indicating the head position of the packet data is inserted, so that the head position of the data can be recognized.

[0007]

For this reason, in the conventional one-to-n broadcast communication, every time the communication speed of each device is increased, it is necessary to replace all devices. SUMMARY OF THE INVENTION It is an object of the present invention to provide a broadcast transmission apparatus which can be upgraded simply by replacing a necessary additional reception apparatus and transmission apparatus without changing an existing reception apparatus.

[0008]

According to a first aspect of the present invention, there is provided a broadcast distributing / transmitting apparatus comprising a transmitting apparatus for transmitting a continuous signal composed of frames and a receiving apparatus for receiving the continuous signal. , Frame sync bit, speed information,
The transmitting apparatus, which transmits a continuous signal including a first frame including phase information and a second frame or a frame that is an integral multiple of the first frame or less, transmits the destination described in the input data. A destination detecting means for detecting, a buffer memory for storing input data for each destination, a frequency dividing circuit for dividing a clock for each destination from a clock source,
A clock having the lowest speed among the clocks output from the frequency divider circuit is used as a basic transmission speed clock, a frame counter that receives the clock at the basic transmission speed and generates a timing signal for generating a transmission frame, A basic rate frame generating unit configured to generate a frame at a basic transmission rate by the generated timing signal;
A memory capacity monitoring means for detecting a case where the capacity of the buffer memory becomes equal to or more than a certain value; a read control means for performing read control based on the output; and a logical sum of the output of the read buffer memory and the basic speed frame. Transmitting means for transmitting data, a receiving apparatus for receiving a continuous signal composed of the frames, a timing reproducing means for performing timing reproduction from a change point of the input data, and a frame for synchronizing frames in the input data. Synchronizing means, detecting speed information in the input data, among the sub-frames in the frame, speed information detecting means to determine a sub-frame of the same speed as its own device, detecting the phase information in the input data, Phase information detecting means for determining the start position of the received data in the sub-frames therein, and a clock generated from the clock source. Based on the timing generated by the timing reproducing means and the transmission rate information received by the speed information detecting means, a sub-cell clock generating means for transmitting a clock of the transmission rate of the received data for receiving the data in the frame; The determination signal received by the speed information detection means, the head position information of the reception data in the frame received by the phase information detection means, and the reception clock generated by the sub-cell clock generation means are consecutive frames composed of different transmission speeds. Data separating means for separating and receiving a signal having the same speed as that of the own device from among the signals.

According to a second aspect of the present invention, there is provided a broadcast distributing / transmitting apparatus comprising a transmitting apparatus for transmitting a continuous signal composed of frames and a receiving apparatus for receiving the continuous signal. And a transmission device for transmitting a continuous signal composed of a frame at a basic rate or a frame at an integral multiple of the basic rate including a data area, a destination detecting means for detecting a destination described in the input data, Memory for storing the clock for each destination, a frequency divider for dividing the clock for each destination from the clock source, and the clock with the lowest speed among the clocks output from the frequency divider as the basic transmission speed clock. A frame counter for receiving a clock of a transmission rate and generating a timing signal for generating a transmission frame; A sub-frame generating means for reading out and adding a preamble and a cell synchronization bit to the beginning of a frame, and a memory capacity monitoring means for detecting a case where the capacity of the buffer memory becomes equal to or more than a certain value. A read-out control unit that performs the read operation, and a read-out control unit that forms a frame of the data read from the buffer memory by the sub-frame generation unit of each transmission rate, and a transmission unit that transmits the data. A receiving device for receiving a signal, a sub-cell clock timing regenerating means for generating a clock synchronized with a change point of input data at a frequency to be received, and detecting a preamble in the received data with a clock generated by the sub-cell clock timing regenerating means. Preamble detection means for performing Means for detecting a cell synchronization bit in the data for which the preamble has been detected by the means; and means for detecting the preamble by the preamble detection means, and for detecting the cell synchronization bit by the cell synchronization bit detection means, the sub-cell clock. Data separating means for separating and receiving a signal having the same speed as that of the own device from a continuous signal composed of frames having different transmission speeds by using the received clock generated by the generating means.

A broadcast distribution transmission apparatus according to a third aspect of the present invention comprises a first frame including a frame synchronization bit, speed information, and phase information, and a second frame or the like that is an integral multiple of the first frame or less. A transmission device for transmitting a continuous signal composed of frames includes destination detection means for detecting a destination written in input data, a buffer memory for storing input data for each destination, and a clock for each destination from a clock source. A frequency dividing circuit for dividing the frequency and a clock having the lowest speed among the clocks output from the frequency dividing circuit are used as a basic transmission speed clock, a clock having the basic transmission speed is received, and a timing signal for generating a transmission frame is generated. Basic rate frame generation for generating a frame at a basic transmission rate based on a frame counter and a timing signal generated by the frame counter Stage, a terminal for determining the calling order of the buffer memory, read control means for performing a read control based on the output, and a logical sum of the read buffer memory output and the basic speed frame to transmit data. Transmission means.

According to a fourth aspect of the present invention, there is provided a broadcast distributing / transmitting apparatus which transmits a continuous signal composed of a frame of a basic rate including a preamble, a cell synchronization bit and a data area or a frame of an integral multiple of the basic rate. Destination detecting means for detecting a destination described in input data, a buffer memory for storing input data for each destination, a frequency dividing circuit for dividing a clock for each destination from a clock source, and a frequency dividing circuit Among the clocks to be output, a clock having the lowest speed is set as a basic transmission speed clock, a clock having the basic transmission speed is received, a frame counter for generating a timing signal for generating a transmission frame, and data is read from the buffer memory. Sub-frame generating means for adding a preamble, a preamble, and a cell synchronization bit to the beginning of a frame and transmitting the frame. A terminal for determining the calling order of the memory, read control means for performing read control based on the output, and a read control means for forming a frame from data read from the buffer memory by a subframe generating means for each transmission rate, And transmission means for transmitting the information.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 In the present embodiment, in data transmission from a transmitting device to a receiving device, data transmission of frames of different speeds is performed based on a basic speed specified in advance by the transmitting device or a speed that is an integral multiple of the basic speed. FIG. 1 illustrates a configuration of a transmitting device and a receiving device. The transmission data 2-1, 2,...
.., N. First data 2-1
Is always information on the basic speed f, and is data that can be received by all the receiving transmission devices 3-1 to 3-1-n facing each other. Here, OAM information, speed information request and the like of each receiving device are assigned. After the transmission data 2-2, transmission data of each individual and each transmission speed is allocated, and the receiving device 3-
2 to n.

FIG. 2 shows a block diagram of the transmitting apparatus. 5 is a transmission destination detecting means, 6-1 to n are buffer memories, 7 is a clock source, 8 is a frequency divider, 9 is a frame counter, 10 is a basic speed frame generating means, 11 is a buffer memory read control means, 12 Is a memory capacity monitoring means, and 13 is an OR gate.

FIG. 3 shows a block diagram of the receiving apparatus. 14 is a timing reproducing unit, 15 is a frame synchronizing unit, 16 is a speed information detecting unit, 17 is a phase information detecting unit, 18 is a sub-cell clock generating unit, and 19 is a data separating unit.

FIG. 4 shows a frame format in the present embodiment. Reference numeral 20 denotes an overhead of the basic speed f0, the contents of which are frame synchronization bits 22,
It comprises speed information 23-1 to n and phase information 24-1 to n. Reference numerals 21-1 to 21-n denote subframes each of which is an integral multiple of the basic speed f0, and are composed of data areas.

The operation of FIG. 2 will be described. The input data is detected by the transmission destination detection means 5 at the transmission destination of the input data. The format of the input data is assumed to be an ATM cell, and the destination of the input data is detected by referring to the header of the cell.
1 to n. Writing to the buffer memories 6-1 to n is performed by a parallel clock with input data. In the present embodiment, when the capacity of the buffer memory becomes equal to or more than a certain value, memory reading is performed using a clock at the transmission speed, and data at the transmission speed is transmitted. The clock is supplied from the clock source 7 to the buffer memory 6-1 in the frequency dividing circuit 8.
Ｎn and output. The clock speed having the lowest speed among them is set as the basic transmission speed, and the frame counter 9 generates the timing for generating the basic speed frame. The generated timing signal is input to the basic speed frame 10, and generates the overhead of the basic speed f0 shown in FIG. On the other hand, each buffer memory 6-1
When the capacity of .about.n exceeds a certain value, each buffer memory sends a capacity alarm to the memory capacity monitoring means 12. The memory capacity alarm from the capacity monitoring means 12 is sent to the read control means 1
Sent to 1. The read control unit 11 transmits a control signal for each of the buffer memories 6-1 to n, and reads data written from the buffer memories. The logical sum of each of the read subframes 21-1 to 21-n and the overhead of the basic speed f0 is calculated by the logical OR gate 13, and the transmission data is output.

The operation of FIG. 3 will be described. The input data is subjected to timing reproduction by the timing reproduction means 14 to extract the timing. Also, frame synchronization means 1
In step 5, frame synchronization is performed, and a frame synchronization pulse is output to the speed information detecting means 16 and the phase information detecting means 17. The speed information detecting means 16 receives the speed information 23-1 to n in the basic speed overhead in the input data. Further, the phase information detecting means 17 receives the phase information 24-1 to n within the basic speed overhead in the input data. Further, the speed information 23 is stored in the sub-cell clock generation unit 1.
The sub-cell clock generating means 18 generates a clock at the speed synchronized with the timing signal generated by the timing reproduction 14 and at the speed indicated by the speed information. The data separating means 19 separates data of the speed designated by the speed information detecting means 16 and the phase designated by the phase information detecting means 17 from the input data and outputs the data.

Embodiment 2 FIG. This embodiment is an example of the first embodiment in which a cell synchronization byte exists on each subframe. In this case, the first subframe is an integral multiple of the basic rate, and has the same format as other subframes. FIG. 7 shows the frame format.

FIG. 5 shows a block diagram of the transmitting apparatus. 25 is a destination detection means, 26-1 to n are buffer memories, 27 is a clock source, 28 is a frequency divider, 29 is a frame counter, 30-1 to n are subframe generation means, and 31 is read control of the buffer memory. Means, 32 is a memory capacity monitoring means, and 33 is an OR gate.

FIG. 6 shows a block diagram of the receiving apparatus. 34 is a sub-cell clock reproducing means, 35 is a preamble detecting means, 36 is a cell synchronization bit detecting means,
7 is an AND gate, and 38 is a data separating means.

FIG. 7 shows a frame format in the present embodiment. 39-1 to n are speeds C1
Subframes f0 to Cn · f0, 40 is a cell synchronization byte area, and 41 is a data area. The contents of the cell synchronization byte area are 42 a preamble and 43 a cell synchronization bit.

The operation of FIG. 5 will be described. Operations up to writing and reading of the buffer memories 26-1 to n + 1 are the same as those of the first embodiment. Each of the read data is added to the subframe generating means 30-1 to n + 1 by adding the cell synchronization byte 40 to the subframes 39-1 to n.
Generate +1. The logical sum of the subframes 39-1 to n + 1 is calculated by the logical sum gate 33, and the transmission data is output.

The operation of FIG. 6 will be described. The input data is subjected to timing reproduction by the sub-cell clock timing reproducing means 34, and a clock synchronized with the timing is extracted. Further, in the preamble detecting means 35,
The preamble 42 in the cell synchronization byte 40 is detected using the clock generated by the sub-cell clock recovery 34. In the data in which the preamble is detected, the cell synchronization bit is detected in the cell synchronization bit 36 to establish the cell synchronization. The data separation unit 38 determines the logical product of the position detected by the preamble detection unit 35 and the phase of the synchronization bit detected by the cell synchronization bit detection unit 36 as the received data phase, and separates and outputs the data from the data.

Embodiment 3 FIG. The present embodiment is an example in which the read control from the buffer memory of the first embodiment is not controlled by the overflow of the buffer memory, but the read control and the transmission data transmission order are determined by an external operation.

FIG. 8 shows a block diagram of the transmitting apparatus. It is the same as the first embodiment except that the terminal 52 controls the read control 50. By controlling the reading of the buffer memory by the external terminal, it is possible to transmit data at a speed desired by the user.

Embodiment 4 The present embodiment is an example in which read control from the buffer memory according to the second embodiment is not controlled by overflow of the buffer memory, but read control and transmission data transmission order are determined by an external operation.

FIG. 9 shows a block diagram of the transmitting apparatus. It is the same as the second embodiment except that the terminal 61 controls the read control 59. By controlling the reading of the buffer memory by the external terminal, it is possible to transmit data at a speed desired by the user.

[0028]

As described above, according to the first aspect of the present invention, in the transmission apparatus, the input data is stored in each buffer memory for each destination, and when the capacity of the buffer memory becomes a certain amount or more,
By reading and outputting with a clock having a speed that is an integral multiple of each basic speed, an integral multiple of the basic speed composed of the first frame and the data area of the basic speed including the frame synchronization bit of the speed, speed information, and phase information Can transmit a continuous signal composed of the second and subsequent frames, and after receiving the frame synchronization, receives the speed information of the first frame, and in the sub-cell clock generating means, refers to the speed information detected above. Then, a receiving clock is generated, the phase information of the first frame is received, and input data of a subframe phase having the same speed as that of the own apparatus can be separated, so that different speed communication can be performed.

According to a second aspect of the present invention, in a transmission apparatus, input data is stored in each buffer memory for each destination, and when the capacity of the buffer memory exceeds a certain value, the data is read out with a clock having a speed that is an integral multiple of each basic speed. In each sub-frame generating means, a preamble and a cell synchronization byte are added and transmitted, so that a frame of a basic rate including a preamble, a cell synchronization bit and a data area or a frame of an integral multiple of the basic rate is transmitted. A continuous signal can be transmitted, and the receiving apparatus performs sub-cell clock recovery, and performs preamble detection and cell synchronization bit detection, thereby separating input data of the same sub-frame phase as that of the own apparatus. Can be.

According to a third aspect of the present invention, by controlling the reading of the buffer memory by an external terminal in the transmission apparatus of the first aspect, it is possible to transmit data at a desired speed for the convenience of the user.

According to a fourth aspect of the present invention, by controlling the readout of the buffer memory by an external terminal in the transmission apparatus of the second aspect, it is possible to transmit data at a desired speed for the convenience of the user.

[Brief description of the drawings]

FIG. 1 is a system configuration example using a broadcast distribution transmission device of the present invention.

FIG. 2 is a block diagram of a transmission device according to the first embodiment.

FIG. 3 is a block diagram of a receiving device according to the first embodiment.

FIG. 4 is a frame format according to the first embodiment.

FIG. 5 is a block diagram of a transmission device according to a second embodiment.

FIG. 6 is a block diagram of a receiving device according to a second embodiment.

FIG. 7 shows a frame format according to the second embodiment.

FIG. 8 is a block diagram of a transmission device according to a third embodiment.

FIG. 9 is a block diagram of a transmission device according to a fourth embodiment.

FIG. 10 shows how data is multiplexed in a conventional one-to-n double star subscriber transmission device.

FIG. 11 shows a conventional continuous signal format from an optical line terminal to a subscriber side device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Transmitting device 2-1 to n Transmission different speed signal 3-1 to n Receiving device 4 Optical star coupler 5, 25, 44, 53 Destination detecting unit 6-1 to n, 26-1 to n, 45-1 n, 54-1 to
n buffer memory 7, 27, 46, 55 clock source 8, 28, 47, 56 frequency divider 9, 29, 48, 57 frame counter 10, 49 basic speed frame generator 11, 31, 50, 59 read controller 12 , 32 Memory capacity monitoring unit 13, 33, 51, 60 OR gate 14 Timing recovery unit 15 Frame synchronization unit 16 Speed information detection unit 17 Phase information detection unit 18 Sub-cell clock generation unit 19, 38 Data separation unit 20 Overhead (basic speed) f0) 21-1 to n Subframe 22 Frame synchronization bit 23-1 to n Speed information 24-1 to n Phase information 30-1 to n, 58-1 to n Subframe generator 34 Subcell clock timing reproducer 35 Preamble Detector 36 Cell synchronization bit detector 37 AND gate 39-1 to n Over arm 40 cell sync byte 41 data region 42 preamble 43 cell synchronization bits 52 and 61 terminal portion

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Ichigase 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term in Mitsubishi Electric Corporation (reference) 5K030 GA19 HB15 JL03 KA03 KA21 LD04 MA13 MB15 5K034 AA14 BB07 DD02 EE02 HH42 MM08 PP07 5K047 AA15 BB02 BB14 GG24 GG52 HH01 HH53 LL09 MM24 MM55 MM56 9A001 CC02 JZ12 KK60

Claims (4)

[Claims] A broadcast distribution transmission device comprising a transmitting device for transmitting a continuous signal composed of frames and a receiving device for receiving the continuous signal, comprising: a frame synchronization bit, speed information,
The transmitting apparatus, which transmits a continuous signal including a first frame including phase information and a second frame or a frame that is an integral multiple of the first frame or less, transmits the destination described in the input data. A destination detecting means for detecting, a buffer memory for storing input data for each destination, a frequency dividing circuit for dividing a clock for each destination from a clock source,
A clock having the lowest speed among the clocks output from the frequency divider circuit is used as a basic transmission speed clock, a frame counter that receives the clock at the basic transmission speed and generates a timing signal for generating a transmission frame, A basic rate frame generating unit configured to generate a frame at a basic transmission rate by the generated timing signal;
A memory capacity monitoring means for detecting a case where the capacity of the buffer memory becomes equal to or more than a certain value; a read control means for performing read control based on the output; and a logical sum of the output of the read buffer memory and the basic speed frame. Transmitting means for transmitting data, the receiving apparatus for receiving a continuous signal comprising the frame, the timing reproducing means for performing timing reproduction from a change point of the input data, and synchronizing a frame in the input data. Frame synchronization means, detects the speed information in the input data, among the sub-frames in the frame, speed information detection means to determine a sub-frame of the same speed as its own device, and detects phase information in the input data, A phase information detecting means for determining a start position of received data in a sub-frame of the frame; and a clock generated from the clock source. A sub-cell clock for transmitting a clock of the transmission rate of the received data for receiving the data in the frame based on the timing generated by the timing reproducing means and the transmission rate information received by the rate information detecting means. Generating means;
A continuous signal composed of frames having different transmission speeds based on the determination signal received by the speed information detecting means, the head position information of the received data in the frame received by the phase information detecting means, and the receiving clock generated by the subcell clock generating means. And a data separating means for separating and receiving a signal of the same speed as the own device from among the receiving device. 2. A broadcast / distribution apparatus comprising a transmitting apparatus for transmitting a continuous signal composed of frames and a receiving apparatus for receiving the continuous signal, comprising: a frame having a basic rate including a preamble, a cell synchronization bit and a data area; A transmission device for transmitting a continuous signal composed of frames at an integer multiple of the speed includes destination detection means for detecting a destination written in the input data, a buffer memory for storing the input data for each destination, and a clock. A frequency dividing circuit that divides a clock for each destination from a source, and a clock having the lowest speed among clocks output from the frequency dividing circuit is used as a basic transmission speed clock. A frame counter for generating a timing signal to be generated, and reading data from the buffer memory, preamble and cell synchronization. Sub-frame generating means for adding a bit to the beginning of a frame and transmitting the data; memory capacity monitoring means for detecting when the capacity of the buffer memory becomes equal to or more than a certain value; read control means for performing read control based on the output; A control unit configured to form a frame with data read from the buffer memory by a sub-frame generation unit at each transmission rate, and a transmission unit configured to transmit data; a reception device configured to receive a continuous signal including the frame includes:
A sub-cell clock timing regenerating means for generating a clock synchronized with a change point of input data at a frequency to be received; a preamble detecting means for detecting a preamble in the received data with a clock generated by the sub-cell clock timing regenerating means; Cell synchronization bit detection means for detecting a cell synchronization bit in the data for which the preamble has been detected by the detection means; and data for which the preamble has been detected by the preamble detection means and the cell synchronization bit has been detected by the cell synchronization bit detection means. Data distribution means for separating and receiving a signal having the same speed as that of its own device from a continuous signal composed of frames having different transmission speeds with a reception clock generated by the clock generation means. apparatus. 3. A first frame including a frame synchronization bit, speed information, and phase information, and a first frame including a second frame and the like.
A transmission device that transmits a continuous signal composed of frames such as an integral multiple of the frame of the frame includes a destination detection unit that detects a destination described in the input data, and a buffer memory that stores the input data for each destination. A frequency dividing circuit that divides a clock for each destination from a clock source, and a clock having the lowest speed among the clocks output from the frequency dividing circuit is used as a basic transmission speed clock, and a clock having this basic transmission speed is received and transmitted. A frame counter for generating a timing signal for generating a frame, a basic rate frame generating means for generating a frame of a basic transmission rate by the timing signal generated by the frame counter, and a terminal for determining a calling order of the buffer memory. Read control means for performing read control based on the output, and a read buffer memo. Taking the logical sum of the output and the basic speed frame, broadcast distribution transmission apparatus according to claim 1, characterized in that it comprises a transmitting means for transmitting data. 4. A transmitting apparatus for transmitting a continuous signal composed of a frame of a basic rate including a preamble, a cell synchronization bit, and a data area or a frame of an integer multiple of the basic rate detects a destination described in input data. Destination detecting means, a buffer memory for storing input data for each destination, a frequency dividing circuit for dividing a clock for each destination from a clock source, and a clock having the lowest speed among clocks output from the frequency dividing circuit. The basic transmission rate clock is used as the basic transmission rate clock, a frame counter that generates a timing signal for generating a transmission frame, reads data from the buffer memory, and adds a preamble and a cell synchronization bit to the beginning of the frame. Sub-frame generating means for transmitting the sub-frame, and an end for determining the calling order of the buffer memory. And read control means for performing read control based on this output, and transmission means for forming a frame of data read from the buffer memory by the read control means at a subframe generating means of each transmission rate and transmitting the data. 3. The method according to claim 2, wherein
A broadcast distribution transmission device according to claim 1.