JP2000187984A - Semiconductor memory and sub-word line drive signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable adoption of a hierarchical type word line constitution even in a DRAM in which memory blocks being adjacent holding a sense amplifier array between them in a memory array is defined as a bank. SOLUTION: Each memory block MA1-MA4 operates as a bank. Each sense amplifier array SL2-SL4 is positioned between tow adjacent memory blocks, and it is shared by these two memory blocks. Plural main word lines being not illustrated are arranged in each memory block MA1-MA4 in parallel to sense amplifier trains SL2-SL4, also driven by main word line driving circuits RDEC1-RDEC4. Sub-word line drive signal lines SWCL1-SWCL5 are arranged at each sense amplifier array SL1-SL5 respectively. The sub-word line drive signal lines SWCL2-SWCL4 are shared by adjacent memory blocks MA1-MA4 respectively. The sub-word line drive signal lines (SWCL2, SWCL3), (SWCL3, SWCL4) arranged separately to sense amplifier arrays (SL2, SL3), (SL3, SL4) being positioned at the both sides are connected to the memory blocks MA2, MA3 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a hierarchical word line structure in which word lines are hierarchized into a main word line and a sub word line, and a sub word line driving signal generation. Circuit.

[0002]

2. Description of the Related Art In recent years, a dynamic random access memory (hereinafter referred to as DRAM) has been highly integrated at a rate of four times in three years.
bit DRAM is mass-produced in earnest, and at research level 4Gb
itDRAM has been developed. In DRAMs that are required to operate at high speeds in addition to high integration, hierarchical word line configurations have been adopted from 64 Mbit onwards in order to improve the random access speed and cover delays in miniaturization process technology. I have. This hierarchical word line configuration
For example, 1995 IEEE INTERNATIONAL SOLID-STATE CIRCUI
TS CONFERENCE, DIGEST OF TECHNICAL PAPERS pp246-24
7 "A 29ns 64Mb DRAM with Hierarchical Array Archit
ecture, M. Nakamura etc. ".

In order to realize a high data transmission rate, various improvements have been made to circuit technology.
For example, as shown in PURODUCT CATALOG manufactured by “RAMBUS”, a high-speed DRA such as a Direct Rambus DRAM
M is under development.

[0004]

However, the aforementioned Di
In a rect Rambus DRAM, memory blocks adjacent to each other across a sense amplifier row in a memory array are defined as banks, while in the hierarchical word line configuration shown by M. Nakamuta etc., a sub-word line drive signal line is mainly used. A configuration in which the components are arranged in a configuration orthogonal to the word lines is employed.
For this reason, it is impossible to arrange the sub-word line drive signal lines between adjacent blocks in a configuration orthogonal to the main word line as shown by the above M. Nakamura etc. It cannot be applied immediately to DRAM.

[0005] In view of the above problems, the present invention has as its object:
A semiconductor memory device that defines a memory block adjacent to a sense amplifier row as a bank is to adopt a hierarchical word line configuration.

[0006]

In order to achieve the above object, the present invention employs a configuration in which a sub-word line drive signal line is arranged on a sense amplifier row positioned between two memory blocks. And

In other words, the semiconductor memory device according to the first aspect of the present invention comprises a memory cell array, a plurality of memory blocks each operating as a bank, and arranged between the plurality of memory blocks. A sense amplifier array shared by the located memory blocks, a plurality of main word lines arranged on each of the memory blocks in parallel with the sense amplifier array, and a main word line drive for driving the plurality of main word lines A circuit and a sub word line drive signal line arranged on the sense amplifier row, and each of the memory blocks is divided into a plurality of sub memory blocks,
Each of the sub-memory blocks includes a plurality of sub-word lines and a sub-word line drive circuit for activating any of the plurality of sub-word lines. It is controlled by a word line and the sub-word line drive signal line.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, the sub word line drive signal lines arranged on the sense amplifier row are located on both sides of the sense amplifier row. The memory blocks are shared and are activated corresponding to the respective bank addresses of the two memory blocks.

According to a third aspect of the present invention, in the semiconductor memory device according to the first aspect, the sub-word line driving signal line connected to the sub-word line driving circuit in one memory block is connected to the memory block. Are arranged in a distributed manner in sense amplifier rows located on both sides.

According to a fourth aspect of the present invention, in the semiconductor memory circuit according to the second aspect, a plurality of column selection signal lines and a plurality of column selection signal lines are arranged across the plurality of memory blocks. A column selection signal line driving circuit that drives any of the plurality of memory blocks, a bank selection signal line that selects any of the plurality of memory blocks, and a corresponding one of the sense amplifier circuits in the sense amplifier row.
A switch element for connecting the corresponding sense amplifier circuit and the data line pair, and arranged corresponding to the switch element;
A data switch control circuit that controls opening and closing of the corresponding switch element in accordance with each signal of the column selection signal line and the bank selection signal line.

According to a fifth aspect of the present invention, a sub-word line driving signal generating circuit has a structure in which word lines are hierarchized into a main word line and a sub-word line, and the sub-word line driving signal line is shared by two memory blocks. A sub-word line drive signal generation circuit in a semiconductor memory device, comprising: a first bank address determination unit that determines one bank address of the memory block; and a second bank address determination unit that determines another bank address of the memory block. A second bank address determining unit, the first bank address determining unit;
And an OR circuit for adding the results of the two judgments by the second bank address judging unit, so that a sub-word line drive signal can be generated when any one of the two memory blocks is selected. I do.

According to a sixth aspect of the present invention, in the sub word line drive signal generating circuit according to the fifth aspect, an output of the OR circuit is output as a bank selection signal.

With the above arrangement, in the semiconductor memory device according to the first to fourth aspects of the present invention, a sub word line drive signal line is arranged on the sense amplifier row in parallel with the main word line. Are distributed to the sub-word line driving circuits for a plurality of sub-memory blocks in the memory block. Therefore, in a memory block adjacent to the sense amplifier row, a sub-word line drive signal line is arranged corresponding to the memory block (bank). The configuration has been combined.

In particular, in the semiconductor memory device according to the second and third aspects of the present invention, two adjacent memory blocks share a sense amplifier array located therebetween.
Since the adjacent memory blocks are not activated at the same time, the sub-word line drive signal lines arranged on the sense amplifier row are shared by the two adjacent memory blocks. Therefore, the number of sub-word line drive signal lines is limited, and the layout area is reduced, so that the increase in the area of the sense amplifier row is reduced.

Further, in the semiconductor memory device according to the present invention, since the bank selection signal is added to the selection of the column address, it is ensured that only data from the selected bank is taken out to the data line. .

Further, in the sub-word line drive signal generating circuit according to the present invention, when the sub-word line drive signal line is shared by two memory blocks, one of the two memory blocks is used. Is selected, the shared sub-word line drive signal line can be always activated.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 schematically shows a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, MA
1 to MA4 are memory arrays, SL1 to SL5 are sense amplifier rows, YD
EC is a column decoder circuit, RDEC1 to RDEC4 are main word line drive circuits, SWC1 to SWC5 are sub word line drive signal generation circuits, SW
CL1 to SWCL5 are sub word line drive signal lines, DO is a data input / output circuit, DB is a data bus, CAB is a column address input circuit, RAB is a row address input circuit, CA is a column address bus, RA is a row address bus, and BAB Is a bank address input circuit, and BA is a bank address bus.

In FIG. 1, the memory arrays MA1 to MA4
Are blocks operating as banks. The sense amplifier rows SL2 to SL4 are shared by the memory arrays located on both sides. Each of the memory arrays MA1 to MA4 has a hierarchical word line configuration, and the internal configuration is the same. FIG. 2 illustrates an outline of the internal configuration of the memory array MA3.

In FIG. 2, the memory array MA3 is divided into a plurality of (four in the figure) sub memory blocks SMB1 to SMB4, and each of the sub memory blocks SMB1 to SMB4 is provided with a sub word line drive circuit SWLDR. MWL1 to MWL4 are main word lines, S
WL11 to SWL48 are sub-word lines, and SWCL3 and SWCL4 are sub-word line drive signal lines. The sub-word line drive circuit SWLDR determines one of a plurality of sub-word lines from two inputs of a main word line and a sub-word line drive signal line. For example, when the main word line MWL3 is activated and the sub word line drive signal line SWCL4 is activated, one sub word line SWL35 to SWL38 is selectively activated in each of the sub memory blocks SMB1 to SMB4. Is done.

In the memory array MA3 shown in FIG. 2, the sub-word line drive signal line SWCL3 extends from the sense amplifier row SL3 located on the left side in the figure, and enters the sub-word line drive signal line SWCL4. It extends from the amplifier row SL4 and enters. With this configuration, the sub word line drive signal line
SWCL3 can be shared by the two adjacent memory arrays MA2 and MA3, and the sub word line drive signal line SWCL4 can be shared by the two adjacent memory arrays MA3 and MA4. Therefore, the number of sub-word line drive signal lines can be reduced, and
Even if SWCL1 to SWCL4 are arranged on the sense amplifier rows SL1 to SL5, an increase in the area of the sense amplifier rows is reduced.

In FIG. 1, main word line drive circuit RD
EC1 to RDEC4 receive a part of the input row address and activate the main word line. The sub-word line drive signal generation circuits SWC1 to SWC5 also generate a sub-word line drive signal upon receiving a part of the input row address. Main word line drive circuits RDEC1 to RDEC4 and sub word line drive signal generation circuits SWC1 to
SWC5 is activated in accordance with the activated bank address. For example, when the memory array MA3 is selected as a bank, the main word line drive circuit RDEC3 operates to activate one of the main word lines MWL1 to MWL4 in the memory array MA3, and The drive signal generation circuits SWC3 and SWC4 are respectively connected to the sub-word line drive signal lines SWCL arranged on the adjacent sense amplifier blocks SL3 and SL4.
3.Output the sub-word line drive signal to SWCL4.
By the activated main word line (for example, MWL3) and the sub word line drive signal on the sub word line drive signal lines SWCL3 and SWCL4, the sub word lines SWL31 to SWL38 in the memory array MA3 are provided.
Is activated, data is read from the memory cell to the sense amplifier and amplified.

Here, the sub-word line drive signal lines SWCL3, SWC
L4 requires an independent sub-word line drive signal for each bank.
~ Cannot be arranged perpendicular to SL5. For this reason, the sub-word line drive signal lines SWCL3 and SWCL4 are connected to the sense amplifier train SL1.
Are arranged in a direction parallel to the main word lines MWL1 to MWL4 and distributed to the sub word line drive circuits SWLDR.

However, in such a chip having a configuration in which a sense amplifier array is shared between two adjacent memory arrays,
Although adjacent memory blocks are not activated at the same time even though they are in different banks, as shown in FIG. 1, two adjacent memory arrays (for example, MA2
And MA3) can share a sub-word line driving signal line (SWCL3), so that the layout is such that the sub-word line driving signal line does not occupy an extra area.

FIG. 3 shows an example of the internal configuration of the sub-word line drive signal generation circuit SWC2 shown in FIG. Other sub-word line drive signal generating circuits SWC1, SWC3 to SWC5 have the same configuration as the internal configuration of FIG. In the figure, NAND1 to NAND4 are NAND circuits, INV is an inverter circuit, SWCL is a sub-word line drive signal line, EN is a control signal to a sub-word line drive signal generation circuit (not shown in FIG. 1), and CNT is A sub word line drive signal timing control signal (not shown in FIG. 1), BA is a bank address bus, and BANK is a bank selection signal line.

The sub-word line drive signal generation circuit SWC2 shown in FIG.
Is a circuit for realizing activation of any of the bank addresses with respect to the input of the bank addresses of two adjacent memory blocks MA1 and MA2. In the figure, when the control signal EN to the sub-word line drive signal generation circuit becomes "H" and the circuit becomes operable, the input of the bank address is accepted. The two NAND circuits (first and second bank address determination units) NAND1 and NAND2 determine the bank addresses BA1 and BA2 of the two adjacent memory blocks MA1 and MA2 so as to determine one and the other bank addresses BA1 and BA2. It is connected to the address signal line of the bus BA. NAND circuit NAND
1, when the bank address BA1 or BA2 is input to either of the NAND2, the NAND circuit (OR circuit unit) NAND3 adds both of the inputs, and one of the inputs becomes “L”. An "H" level signal BANK is output to the NAND circuit NAND4. The NAND circuit NAND4 receives the input timing signal C
The sub word line drive signal is activated on the sub word line drive signal line SWCL in synchronization with the timing of NT. The output signal BANK of the NAND circuit NAND3 is output to a data switch control circuit (described later) as a bank selection signal.

In the present embodiment, the timing signal CN
Include row address in T, but if multiple row address signals need to be input to generate sub word line drive signal, timing signal CNT includes decode signal from multiple row address signals I can do it. Also,
The control signal EN to the sub-word line drive signal generation circuit may include the row address.

Returning to FIG. 1, a column decoder circuit (column selection signal line driving circuit) YDEC generates a column decode signal corresponding to the input column address, and outputs a sense amplifier row corresponding to the selected bank. , A corresponding sense amplifier is selected, the data is output to the data bus DB, and the data is read out of the chip via the input / output circuit DO.

FIG. 4 shows a part of the sense amplifier row SL3 shown in FIG. In the figure, BL Pair is a bit line pair, DL Pa
ir is a data line pair, SA1 to SA4 are sense amplifier circuits, and SW1 is a first switch element arranged in the bit line pair BL Pair. Y1 to Y4 are column decode signal lines (column selection signal lines), and SH1 and SH2 are bit line switching signals. The switching signals SH1 and SH2 control opening and closing of the first switch element SW1, The input bit line pair BL Pair of either the left or right bank is connected to the sense amplifier circuits SA1 to SA.
Controls whether to connect to 4. Sense amplifier circuits SA1 to SA4
Amplifies the data on the input bit line pair BL Pair.

Further, in FIG. 4, SW2 is arranged corresponding to the sense amplifier circuits SA1 to SA4, a second switch element for connecting the corresponding sense amplifier circuit to the data line pair DL Pair, and YD1 to YD4 are data. Switch control circuit, the control circuits YD1 to YD4
1 to SA4 and the second switch element SW2, control the corresponding two switch elements SW2, connect the corresponding sense amplifier circuit to the data line pair DL Pair, and connect the amplified data to the data line Output to DL Pair.

The data switch control circuits YD1 to YD4 are:
The signals of the column decode signal lines Y1 to Y4 and the bank select signal line BANK are used to control the corresponding second switch element SW.
2 is controlled to open and close. The bank selection signal line BANK includes:
The sub-word line drive signal generation circuits SWC1-SW shown in FIG.
A bank selection signal is supplied from the NAND circuit NAND3 of C5. Thus, the bank selection signal is used to select the column address.
With the configuration that adds a bank, only data from the selected bank can be output to the data line pair DL Pair, eliminating output collision between data from the unselected bank and data from the selected bank, preventing malfunction. It becomes possible to do. Note that the data switch control circuits YD1 to YD4 may employ any circuit configuration as long as the above functions are satisfied.

[0032]

As described above, according to the semiconductor memory device of the first to fourth aspects of the present invention, the sub word line drive signal lines are arranged on the sense amplifier row in parallel with the main word lines. Therefore, it is possible to adopt a hierarchical word line configuration in a DRAM in which a memory block adjacent to a sense amplifier row is defined as a bank as represented by a Direct Rambus DRAM.

In particular, according to the semiconductor memory device of the second and third aspects of the present invention, in a configuration in which a sense amplifier array is shared by two memory blocks located on both sides of the sense amplifier array, the sense amplifier array is arranged on the sense amplifier array. Since the sub-word line drive signal line to be used is also shared by the two memory blocks,
By reducing the number of sub-word line drive signal lines and their layout area, an increase in the area of the sense amplifier array can be reduced.

According to the semiconductor memory device of the present invention, since the selection of the column address includes the bank selection signal, it is possible to ensure that only the data required to be output is taken out to the data line.

Further, according to the sub-word line driving signal generating circuit of the invention according to the fifth and sixth aspects, when the sub-word line driving signal line is shared by two memory blocks, it is so shared. The sub-word line drive signal supplied to the sub-word line drive signal line can be reliably generated regardless of which of the two shared memory blocks is selected.

It is possible to provide a generating circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall schematic configuration of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a diagram showing a schematic internal configuration of one memory block in the semiconductor memory device of the embodiment;

FIG. 3 is a diagram illustrating a circuit configuration of a sub-word line drive signal generation circuit according to the embodiment of the present invention;

FIG. 4 is a diagram showing a schematic configuration around a sense amplifier array in the semiconductor memory device according to the embodiment of the present invention;

[Explanation of symbols]

MA1 to MA4 Memory array (memory block) SL1 to SL5 Sense amplifier row YDEC Column decoder circuit (column selection signal line drive circuit) RDEC1 to RDEC4 Main word line drive circuit SWC1 to SWC5 Sub word line drive signal generation circuit BAB Bank address input circuit SMB1 to SMB4 Sub memory block SWLDR Sub word line drive circuit MWL1 to MWL4 Main word line SWL11 to SWL48 Sub word line SWCL1 to SWCL5 Sub word line drive signal line NAND1 NAND circuit (first bank address determination unit) NAND2 NAND circuit (first 2 Bank address determination section) NAND3 NAND circuit (OR circuit section) BANK Bank selection signal line BL Pair Bit line pair DL Pair Data line pair SA1 to SA4 Sense amplifier circuit YD1 to YD4 Data switch control circuit SW2 Second switch element (Switch element) Y1 to Y4 Column decode signal line (column select signal line)

Claims (6)

[Claims] A plurality of memory blocks each comprising a memory cell array, each of which operates as a bank; and a plurality of memory blocks arranged between the plurality of memory blocks.
A sense amplifier array shared by the memory blocks located on both sides, a plurality of main word lines arranged on each of the memory blocks in parallel with the sense amplifier array, and a main word for driving the plurality of main word lines A line drive circuit, and a sub-word line drive signal line disposed on the sense amplifier row. Each of the memory blocks is divided into a plurality of sub-memory blocks. A word line, and a sub-word line drive circuit for activating any of the plurality of sub-word lines, wherein each of the sub-word line drive circuits comprises a main word line and a sub-word line drive signal line. A semiconductor memory device controlled by: 2. A sub-word line drive signal line arranged on the sense amplifier row is shared by memory blocks located on both sides of the sense amplifier row, and corresponds to each bank address of both memory blocks. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is activated. 3. A sub-word line driving signal line connected to a sub-word line driving circuit in one memory block is distributed and arranged in sense amplifier rows located on both sides of the memory block. 2. The semiconductor memory device according to claim 1, wherein: 4. A plurality of column selection signal lines traversing over the plurality of memory blocks, a column selection signal line driving circuit driving any one of the plurality of column selection signal lines, and A bank selection signal line for selecting any one of the memory blocks, a switch element arranged corresponding to each sense amplifier circuit in the sense amplifier row, and connecting a corresponding sense amplifier circuit and a data line pair; A data switch control circuit arranged corresponding to the switch element and controlling opening and closing of the corresponding switch element according to each signal of the column selection signal line and the bank selection signal line. Item 3. A semiconductor memory circuit according to item 2. 5. A sub-word line driving signal generation in a semiconductor memory device in which word lines are hierarchized into a main word line and a sub-word line, and a sub-word line driving signal line is shared by two memory blocks. A first bank address determination unit that determines one bank address of the memory block; a second bank address determination unit that determines the other bank address of the memory block; And an OR circuit for adding the two determination results of the two bank address determination units, and enabling the generation of the sub word line drive signal when any one of the two memory blocks is selected. Word line drive signal generation circuit. 6. The sub-word line drive signal generation circuit according to claim 5, wherein an output of said OR circuit is output as a bank selection signal.