JP2000183355A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for speeding up a semiconductor integrated circuit device which has a MISFET formed on an SOI substrate and improving reliability. SOLUTION: A groove, which is surrounded by a side wall spacer 11 and whose depth (d) is about 90-100 nm is formed on a polycrystalline silicon film 6, constituting the gate electrode of a MISFET. Silicons 13a and 13b with a thickness of about 100 nm are stacked on the surface of the exposed thin-film silicon layer 3. Thereafter, a titanium silicide layer is formed on the surfaces of the silicons 13a and 13b through self-matching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to an SOI (Silicon On Insula) device.
tor) Fully depleted MISFET (Met
al Insulator Semiconductor Field Effect Transistor
The present invention relates to a technique which is effective when applied to a semiconductor integrated circuit device having ()).

[0002]

2. Description of the Related Art A fully depleted MISFET has a structure in which a MISFET is completely surrounded by an insulating film by forming a thick field insulating film on the surface of a thin silicon layer.
Swing) can be reduced, and the substrate floating effect can be suppressed.

However, as the thin film silicon layer becomes thinner, the semiconductor region forming the source and drain of the MISFET is formed shallower. For this reason, it is necessary to suppress the impurity diffusion by suppressing the impurity concentration of the semiconductor region to a low level. At the same time, however, the resistance of the semiconductor region increases, and the operating speed of the MISFET decreases.

Therefore, as a method of lowering the resistance of the semiconductor region forming the shallow source and drain, a method of siliciding the surface of the semiconductor region by self-alignment has been studied.
However, since the thin silicon layer is thin, there is a possibility that the formed silicide layer comes into contact with the buried insulating film constituting the SOI substrate and the silicide layer is peeled off.

[0005] Fully depleted MISF which has solved the above problems
For example, an ET formation method is described in IEEE Electron Device Letters (IEEE Electron Device Letters).
ce Letters. Vol. 18, No. 6, PP. 251-253, 1997). That is, first, a field insulating film is formed on a thin silicon layer of several tens of nm, and then a MISFET
Gate insulating film, a gate electrode formed of a polycrystalline silicon film, and a sidewall spacer formed of a silicon oxide film are sequentially formed, and then an upper layer of a thin film silicon layer in which a semiconductor region forming a source and a drain is formed Is selectively grown to several tens of nm (selective silicon growth). Thereafter, impurities are introduced into the thin film silicon layer thickened by the selective silicon growth to form a semiconductor region constituting a source and a drain.

As a result, although the thin film silicon layer below the gate electrode of the MISFET is as thin as several tens of nanometers,
Since the thin film silicon layer on which the semiconductor regions constituting the source and drain of the ET are formed becomes thicker by selective silicon growth, the subthreshold swing can be reduced by complete depletion, and at the same time, the silicidation or the concentration is increased. It is possible to reduce the resistance of the semiconductor region forming the source and the drain.

[0007]

However, the present inventor has found the following problems in the method of forming the fully depleted MISFET.

That is, in the selective silicon growth, silicon is deposited on the thin film silicon layer on which the semiconductor regions constituting the source and the drain are formed.
When forming a side wall spacer on the side wall of the gate electrode of the ET, the silicon oxide film on the thin silicon layer on which the semiconductor regions constituting the source and drain of the MISFET are formed and the insulating film of the same layer as the gate insulating film are formed. It is necessary to sequentially etch to expose the surface of the thin silicon layer. The silicon oxide film is an insulating film deposited on a gate electrode to form a sidewall spacer.

Therefore, in order to expose the thin silicon layer on which the semiconductor regions constituting the source and drain of the MISFET are formed, it is necessary to make the etching amount larger than the thickness of the silicon oxide film. Therefore, the surface of the polycrystalline silicon film forming the gate electrode is exposed, and further, the upper part of the side surface of the polycrystalline silicon film forming the gate electrode is also exposed.

When selective silicon growth is carried out in a state where the upper side of the polycrystalline silicon film constituting the gate electrode is exposed,
Silicon deposited on the upper layer of the gate electrode overhangs. In a subsequent step, when a contact hole for connecting the wiring layer and the semiconductor region forming the source and the drain is provided in the interlayer insulating film, the contact hole may come into contact with overhanging silicon. When the contact hole comes into contact with silicon, a short circuit occurs between the gate electrode and the semiconductor region forming the source and drain by the wiring layer, thereby lowering the reliability of the MISFET. Therefore, the distance between the gate electrode and the contact hole is 0.1 μm.
It is not possible to form a MISFET of a minute size.

An object of the present invention is to provide a technique capable of increasing the speed of a semiconductor integrated circuit device having a MISFET formed on an SOI substrate and at the same time improving the reliability.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, when a MISFET is formed on an SOI substrate having a thin silicon layer provided on a supporting substrate via a buried insulating film, the main surface of the thin silicon layer is Forming a field insulating film thereon, forming a gate insulating film on the surface of the thin silicon layer, then sequentially depositing a polycrystalline silicon film and a silicon nitride film on the SOI substrate; Forming a part of a gate electrode made of the polycrystalline silicon film and a cap insulating film made of a silicon nitride film on a part of the gate electrode by sequentially processing the polycrystalline silicon film; After depositing a silicon oxide film on the silicon oxide film, the silicon oxide film is processed by anisotropic etching to form a film on the side wall of the cap insulating film and part of the gate electrode. Forming a side wall spacer made of a silicon nitride film, subsequently exposing the surface of the thin silicon layer where a part of the semiconductor region constituting the source and drain is formed, and selectively removing the cap insulating film Exposing the surface of the polycrystalline silicon film forming a part of the gate electrode, forming a groove on the polycrystalline silicon film surrounded by the silicon oxide film forming the side wall spacer; By
Silicon is deposited inside the upper groove of the polycrystalline silicon film forming a part of the gate electrode to form another part of the gate electrode, and at the same time, a part of the semiconductor region forming the source and the drain is formed. A step of depositing silicon on which another part of the semiconductor region constituting the source and the drain is formed above the thin film silicon layer, and a step of forming a silicide layer on the surface of the silicon.

According to the above-described means, even if silicon constituting another part of the gate electrode is deposited on the polycrystalline silicon film constituting a part of the gate electrode by selective silicon growth, the silicon is not removed. Since it is deposited inside the trench surrounded by the sidewall spacer and is unlikely to overhang, contact between the contact hole reaching the semiconductor region constituting the source and the drain and silicon can be prevented, and the gate electrode and the source and the drain can be separated. There is no short circuit with the constituent semiconductor region. Further, the distance between the gate electrode and the contact hole can be made as small as about 0.1 μm, so that the MISFET can be miniaturized.

[0016] Further, silicon forming another part of the semiconductor region forming the source and drain is formed on the thin film silicon layer on which part of the semiconductor region forming the source and drain is formed. By forming a silicide layer on the surface of the substrate, the silicide layer is less likely to come into contact with the buried insulating film, so that the silicide layer can be prevented from peeling off.

Further, by forming a silicide layer on each of the surface of silicon forming another part of the gate electrode and the surface of silicon forming another part of the semiconductor region forming the source and drain, the gate is formed. The electric resistance of the semiconductor region forming the electrode, the source, and the drain can be reduced, and the circuit operation can be performed at high speed.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A method for manufacturing an n-channel MISFET on an SOI substrate according to an embodiment of the present invention will be described with reference to FIGS. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and
The description of the repetition is omitted.

First, as shown in FIG. 1, a LOCOS (Local Oxidation of LOCOS) for element isolation is formed on a surface of an SOI substrate composed of a support substrate 1, a buried oxide film 2 and a p-type thin silicon layer 3 by a known method. Silicon) oxide film 4
To form The thickness of the buried oxide film 2 is, for example, about 80 nm, and the thickness of the thin silicon layer 3 is, for example, about 50 nm.
nm.

Next, although not shown, an impurity for adjusting the threshold voltage of the MISFET, for example, boron (B) is implanted into the thin film silicon layer 3 by ion implantation.
Boron ions are implanted at an acceleration energy of, for example, 10 KeV and about 2 × 10 ¹² cm ⁻² .

Next, as shown in FIG. 2, after a gate insulating film 5 made of a silicon oxide film is formed on the surface of the thin film silicon layer 3 to a thickness of, for example, about 8 nm, the SOI
A polycrystalline silicon film 6 and a silicon nitride film 7 to which phosphorus (P) is added at about 1 × 10 ²⁰ cm ⁻³ are sequentially deposited on a substrate by a chemical vapor deposition (CVD) method. The thickness of the polycrystalline silicon film 6 is
For example, the thickness of the silicon nitride film 7 is, for example, about 200 nm, and the thickness of the silicon nitride film 7 is, for example, about 100 nm.
The thickness is set to be equal to or larger than the thickness of silicon deposited by selective silicon growth in a later step.

Next, as shown in FIG. 3, the silicon nitride film 7 and the polycrystalline silicon film 6 are sequentially etched using the photoresist film 8 as a mask to form a cap insulating film and a polycrystalline silicon film formed of the silicon nitride film 7. A part of the gate electrode constituted by the crystalline silicon film 6 is formed.

Next, as shown in FIG. 4, an n-type impurity, for example, phosphorus ions is implanted into the thin silicon layer 3 by ion implantation using the cap insulating film composed of the silicon nitride film 7 as a mask. A low-concentration n ⁻ type semiconductor region (source, drain) 9 constituting a part of the drain is formed. Phosphorus ions are, for example, 20 Ke
It is driven at an acceleration energy of V of about 4 × 10 ¹³ cm ⁻² .

Next, as shown in FIG.
A silicon oxide film 10 having a thickness of 0 nm is
It is deposited by the VD method.

Next, as shown in FIG. 6, an insulating film of the same layer as the silicon oxide film 10 and the gate insulating film 5 is formed by RIE.
(Reactive Ion Etching) processing is performed by anisotropic etching to form sidewall spacers 11 made of the silicon oxide film 10 on the side walls of the silicon nitride film 7 and the polycrystalline silicon film 6, and at the same time, the n ⁻ type. Thin film silicon layer 3 on which semiconductor regions (source, drain) 9 are formed
Expose the surface.

At this time, the silicon nitride film 7 is hardly shaved due to the difference between the etching rates of the silicon nitride film 7 and the silicon oxide film 10, but if the silicon oxide film 10 is over-etched, the silicon nitride film 7 The upper portion of the side surface is exposed, and silicon deposited on the polycrystalline silicon film 6 in a later step becomes overhang. To prevent this, the amount of over-etching of the silicon oxide film 10 is suppressed to 10% or less.

Next, as shown in FIG. 7, the silicon nitride film 7 is formed by wet etching using, for example, hot phosphoric acid.
Is selectively removed, and a trench 12 surrounded by a sidewall spacer 11 formed of a silicon oxide film 10 is formed on the polycrystalline silicon film 6.

Next, as shown in FIG. 8, silicon 13a constituting another part of the gate electrode is deposited on the exposed surface of the polycrystalline silicon film 6 by selective silicon growth, and the exposed thin film silicon layer is simultaneously formed. The silicon 13b is deposited on the surface of No.3. The thickness of the silicon 13a, 13b is, for example, about 100 nm. As described above, since the over-etching amount of the silicon oxide film 10 is suppressed to 10% or less, the depth d of the groove 12 is set to about 90 to 1
00 nm, which is approximately 100 nm on the surface of the polycrystalline silicon film 6.
Even if silicon 13a having a thickness of
3a does not overhang.

Next, as shown in FIG.
And an n-type impurity such as arsenic (A
s) Ions are implanted by an ion implantation method to form a high-concentration n ⁺ -type semiconductor region (source, drain) 14 constituting another part of the source and the drain. Arsenic ions are 2 × 10 ¹⁵ at an acceleration energy of, for example, 10 KeV.
^Driven about cm ^-2 . Thus, n ⁺ -type semiconductor region (source, drain) in the thin film silicon layer 3 14 part of is formed, n ⁺ -type semiconductor region (source, drain) another portion of 14 is formed on the silicon 13b. Thereafter, a heat treatment is performed on the SOI substrate at a temperature of 900 ° C. for about 1 minute to activate the n-type impurities.

Next, as shown in FIG. 10, after a titanium (Ti) film is deposited on the SOI substrate to a thickness of about 40 nm, a heat treatment is performed on the SOI substrate at a temperature of 850 ° C. for about 1 minute, and then an unreacted titanium By removing the film, the MISFET
Surface of the silicon 13a constituting another part of the gate electrode and the n ⁺ type semiconductor region (source,
Silicon 13b on which another part of drain 14 is formed
A low-resistance titanium silicide (TiSi ₂ ) layer 15 having a thickness of about 80 nm is formed on the surface of the substrate.

Next, as shown in FIG. 11, after an interlayer insulating film 16 is formed on the SOI substrate by the CVD method, the interlayer insulating film 16 is chemically and mechanically polished (Chemical Vapor Dep.
The surface is polished by an osition (CMP) method to flatten the surface. Next, the interlayer insulating film 16 is etched using the photoresist pattern as a mask to form a contact hole 17 reaching the titanium silicide layer 15 on the n ⁺ type semiconductor region (source, drain) 14. After this, SO
A tungsten (W) film and an aluminum (Al) alloy film are sequentially deposited on the I substrate, and then the aluminum alloy film and the tungsten film are sequentially etched using the photoresist pattern as a mask to form a wiring layer 18.

In the present embodiment, the cap insulating film is constituted by the silicon nitride film 7 and the side wall spacer 11 is constituted by the silicon oxide film 10.
However, the present invention is not limited to this. Cap insulating films and sidewall spacers 1 may be formed by insulating films having different etching rates.
1 and 1 as long as the selectivity in wet etching or dry etching can be obtained. For example, the cap insulating film may be formed of a silicon oxide film, the sidewall spacer 11 may be formed of a silicon nitride film, or the cap insulating film may be formed of a relatively coarse silicon oxide film,
1 may be composed of a relatively dense silicon oxide film.

As described above, according to the present embodiment, the polycrystalline silicon film 6 constituting a part of the gate electrode is
Even if silicon 13a constituting another part of the gate electrode is deposited by selective silicon growth, the silicon 13a
Is deposited inside the trench 12 surrounded by the sidewall spacer 11 and is unlikely to overhang, so that contact between the contact hole 17 reaching the n ⁺ type semiconductor region (source and drain) 14 and the silicon 13a can be prevented. As a result, the gate electrode and the n ⁺ type semiconductor region (source, drain) 14 are not short-circuited. Further, the distance between the gate electrode and the contact hole 17 can be made as small as about 0.1 μm, so that the MISFET can be miniaturized.

Further, another part of the n ⁺ type semiconductor region (source, drain) 14 is formed on the thin film silicon layer 3 where a part of the n ⁺ type semiconductor region (source, drain) 14 is formed. Silicon 13b is provided, and by forming titanium silicide layer 15 on the surface of silicon 13b, titanium silicide layer 15 is filled with buried oxide film 2.
Therefore, the titanium silicide layer 15 can be prevented from peeling off.

Further, the surface of the silicon 13a and the n ⁺ type semiconductor region (source,
Silicon 13b on which another part of drain 14 is formed
By forming the titanium silicide layer 15 on the surface of the semiconductor device, the electrical resistance of the gate electrode and the n ⁺ type semiconductor region (source and drain) 14 can be reduced, and the circuit operation can be performed at high speed.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the invention. However, the invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, the case where the present invention is applied to a method of manufacturing an n-channel MISFET formed on an SOI substrate has been described. The present invention can be applied to a method of manufacturing a MISFET.

[0039]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the contact between the gate electrode of the MISFET and the contact hole reaching the semiconductor region constituting the source and the drain is prevented, and the distance between the two is set to 0.1 μm.
m, and a low-resistance silicide layer without peeling can be formed on the surface of the semiconductor region constituting the gate electrode, source and drain of the MISFET.
The circuit operation can be speeded up by miniaturizing the ISFET and reducing the electric resistance, and at the same time, the reliability can be improved.

[Brief description of the drawings]

FIG. 1 shows M on an SOI substrate according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 2 is a diagram showing M on an SOI substrate according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 3 shows M on an SOI substrate according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 4 illustrates an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 5 is a diagram showing M on an SOI substrate according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 6 illustrates an example of M on an SOI substrate according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 7 is a diagram showing M on an SOI substrate according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 8 illustrates an example of M on an SOI substrate according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 9 illustrates an example of M on an SOI substrate according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing an ISFET.

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing a MISFET on an SOI substrate according to an embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing a MISFET on an SOI substrate according to an embodiment of the present invention;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 support substrate 2 buried oxide film 3 thin silicon layer 4 LOCOS oxide film 5 gate insulating film 6 polycrystalline silicon film 7 silicon nitride film 8 photoresist film 9 n ^- type semiconductor region (source, drain) 10 silicon oxide film 11 sidewall Spacer 12 Groove 13a Silicon 13b Silicon 14 n ⁺ type semiconductor region (source, drain) 15 Titanium silicide layer 16 Interlayer insulating film 17 Contact hole 18 Wiring layer d Depth of groove

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) HL06 NN02 NN35 NN40 NN62 NN66 QQ01 QQ11 QQ19

Claims (7)

[Claims] An MISFET on an SOI substrate having a thin silicon layer provided on a supporting substrate via a buried insulating film.
Forming a semiconductor integrated circuit device,
(a) After forming a field insulating film on the main surface of the thin film silicon layer, a gate insulating film is formed on the surface of the thin film silicon layer, and then a polycrystalline silicon film and a first insulating film are formed on the SOI substrate. (B) sequentially processing the first insulating film and the polycrystalline silicon film to form a part of a gate electrode made of the polycrystalline silicon film and a part of the gate electrode; Forming a cap insulating film made of the first insulating film as an upper layer of (c).
After depositing a second insulating film on the OI substrate, the second insulating film is processed by anisotropic etching, and the second insulating film is formed on a side wall of the cap insulating film and a part of the gate electrode. Forming a sidewall spacer made of a film, and subsequently exposing the surface of the thin film silicon layer on which a semiconductor region constituting a source and a drain is formed; and (d) selectively removing the cap insulating film. Exposing the surface of the polycrystalline silicon film constituting a part of the gate electrode, and (e) depositing silicon on the polycrystalline silicon film constituting a part of the gate electrode by selective silicon growth. Depositing to form another part of the gate electrode, and simultaneously depositing silicon on the thin film silicon layer on which the semiconductor regions constituting the source and drain are formed. The method of manufacturing a semiconductor integrated circuit device. 2. A method of manufacturing a semiconductor integrated circuit device in which a MISFET is formed on a bulk substrate made of single crystal silicon, comprising: (a) forming a field insulating film on a main surface of the bulk substrate; Forming a gate insulating film on the surface of the bulk substrate and then sequentially depositing a polycrystalline silicon film and a first insulating film on the bulk substrate; (b) the first insulating film and the polycrystalline silicon Forming a part of the gate electrode made of the polycrystalline silicon film and a cap insulating film made of the first insulating film in an upper layer of a part of the gate electrode by sequentially processing the film; After depositing a second insulating film on the bulk substrate, the second insulating film is processed by anisotropic etching to form the second insulating film on the side wall of the cap insulating film and a part of the gate electrode. Side wall consisting of 2 insulating films Forming a metal spacer, followed by exposing a surface of the bulk substrate on which a semiconductor region constituting a source and a drain is formed; and (d) selectively removing the cap insulating film to form a gate electrode. Exposing the surface of the polycrystalline silicon film forming a part of the gate electrode, and (e) depositing silicon on the polycrystalline silicon film forming a part of the gate electrode by selective silicon growth. Depositing silicon on an upper layer of a bulk substrate on which a semiconductor region forming the source and the drain is formed at the same time as the other part of the semiconductor integrated circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a silicide layer is formed on a surface of said silicon. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film has a thickness of:
A method for manufacturing a semiconductor integrated circuit device, wherein the thickness is equal to or larger than the thickness of the silicon. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film and the second
The method for manufacturing a semiconductor integrated circuit device, wherein selectivity is obtained by wet etching or dry etching with the insulating film. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film is a silicon nitride film, and said second insulating film is a silicon oxide film. Of manufacturing a semiconductor integrated circuit device. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the amount of over-etching is 1 when the second insulating film is processed by anisotropic etching.
A method for manufacturing a semiconductor integrated circuit device, which is 0% or less.