JP2000182394A - Redundancy circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arrange fuse circuits separately from a comparator circuit by hardly increasing a wiring area. SOLUTION: A comparator circuit 11 and a shift register circuit 14 are arranged for example on a small block in a standard cell system, and fuse circuit parts 12 and a shift register circuit 13 are arranged separately from the comparator circuit 11. The parallel fuse signals of the fuse circuit parts 12 are converted into a serial signal by the shift register circuit 13, and transmitted through one data signal line to the shift register circuit 14, and return to the original parallel fuse signals, and inputted to the comparator circuit 11. The comparator circuit 11 compares input address signals with the fuse signals, and outputs a hit signal for allowing a certain address signal to use a spare memory cell. The comparator circuit 11 and the fuse circuit parts 12 are connected through one data signal line 16 so that arrangement constitution can be realized by hardly increasing a wiring area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy circuit for using a spare memory cell for a specific input address signal using a fuse, and a semiconductor device equipped with the redundancy circuit.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device such as a semiconductor memory, when a memory cell at a certain address has a defect,
A redundancy circuit for controlling the use of a redundancy memory (spare memory) for the address by programming the address using a fuse is mounted.

FIG. 7 is a block diagram showing a schematic configuration example of a conventional redundancy circuit. The redundancy circuit mainly includes a comparator circuit 1 and a fuse circuit section 2 in which a plurality of fuse circuits are assembled.

FIG. 8 is a detailed circuit diagram of FIG. A signal (fuse signal) in which an input address signal and a defective address are programmed based on whether or not a fuse in the fuse circuit unit 2 is blown.
Xn, X2,... Xn are compared by the comparator circuit 1. If the memory cell specified by the input address signal is a defective address, a hit signal is generated.
This hit signal is a signal for judging whether or not there is access to the spare memory cell. If there is a hit signal, the spare memory cell is accessed at the address.

In the above configuration, the comparator circuit 1 responds to N address signals input to the comparator circuit 1.
The number of signal lines connecting the fuse circuit unit 2 and the fuse circuit unit 2 is required for the number of independent sets of redundancy (N × the number of sets), and is usually a considerable number.

The comparator circuit 1 comprises an exclusive OR circuit 91 as shown in FIG.
Each of the fuse circuits is composed of a memory circuit composed of two inverters 41 and a fuse 42 as shown in FIG. 10, and if the corresponding address is a defective address, the fuse 42 is blown. Invert the data held in the circuit.

[0007]

In the layout of the above-described conventional semiconductor device equipped with a redundancy circuit, consider a case as shown in FIG. 11 in which small blocks are arranged in an array as in a standard cell system.
In the layout of the small blocks 61, the aluminum wiring is usually routed over the entirety, so that a plurality of small blocks 61 are arranged along both sides of the wiring region 62.

For example, when the above-described comparator circuit 1 is arranged on a small block, a configuration in which a power supply line 611 is placed on the surface of the small block 61 as shown in FIG. If placed,
The fuse 42 needs to be arranged on the surface of the small block 61 as shown in FIG. 13 so that the fuse can be blown.

For this reason, as shown in FIG. 14, a small block 61 (shown in black) in which a fuse circuit is arranged becomes larger than the other small blocks 61, as shown in FIG. Biting into the wiring area 62,
The wiring area 62 is reduced. In particular, automatic wiring CAD
In such a case, as shown in FIG. 15, the wiring area 62 may be greatly reduced due to the restriction of the wiring area by the wiring algorithm, and a problem that the useless area 63 is increased accordingly.

Therefore, in order to avoid the above-mentioned inconvenience, the small blocks of the fuse circuit need not be arranged on the small block array shown in FIG. A method may be considered in which a small block 61 of the comparator circuit is separated from a position other than on the array. Note that the position of the small block 61 of the comparator circuit cannot be located away from the critical path due to the effect on the operation speed.
It must be placed on the small block array.

However, when the small blocks 61 of the fuse circuit are arranged apart from each other as described above, the number of signal lines between the comparator circuit 1 and the fuse circuit unit 2 becomes N × N × the number of address lines as described above. The required number of redundancy independent sets is required, and a wiring area corresponding to this number of bus lines is required between the comparator circuit 1 and the fuse circuit section 2, so that the entire wiring area is considerably increased, and the minus side becomes very large. Failure occurs.

Further, since the number of signal lines between the comparator circuit 1 and the fuse circuit unit 2 tends to increase in the future,
The minus side also tends to increase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. An object of the present invention is to dispose a fuse circuit apart from a comparator circuit without increasing the wiring area. An object of the present invention is to provide a redundancy circuit that can be used and a semiconductor device equipped with the redundancy circuit.

[0014]

In order to achieve the above object, a feature of the present invention is to provide a fuse circuit for generating a parallel fuse signal for indicating whether or not a spare memory cell is accessed for each address signal. And a comparison circuit for comparing the input address signal and the fuse signal to generate a hit signal for instructing access to the spare memory cell, wherein the spare memory is provided for a specific address signal. In a redundancy circuit using cells, transmission means for converting the parallel fuse signal into a serial fuse signal and transmitting the serial fuse signal to the comparison circuit is provided.

According to the first aspect of the present invention, when a comparison circuit is arranged on a small block array as in the standard cell system, the fuse circuit group has the same layout as the other small blocks due to restrictions due to the layout of the multilayer wiring. Since the configuration cannot be taken, it cannot be arranged on the small block array described above, and the fuse circuit group is arranged away from the comparison circuit. At this time, since the parallel fuse signals of the fuse circuit group are serialized and sent to the comparison circuit side by one signal line, an increase in the wiring area for transmitting the fuse signal is greatly suppressed. Even if the fuse circuit groups are arranged apart from each other, the increase in the wiring area can be greatly suppressed.

A second feature of the present invention is that a fuse circuit group for generating a parallel fuse signal for notifying the presence or absence of access to a spare memory cell for each address signal is compared with an input address signal and a fuse signal. And a comparison circuit for generating a hit signal instructing access to a spare memory cell. In a redundancy circuit for using the spare memory cell for a specific input address signal, the parallel fuse signal is First signal conversion means for converting a serial fuse signal into a serial fuse signal, second signal conversion means for converting the serial fuse signal into a parallel fuse signal, and a serial fuse obtained by the first signal conversion means And a signal line for transmitting a signal to the second signal conversion means.

According to a third aspect of the present invention, the first and second signal conversion circuits are first and second shift register circuits, and the first and second signal conversion circuits are transmitted from the first shift register circuit through the signal lines. Detecting means for detecting the timing when the serial fuse signal has just been input to the second shift register circuit; and
Transmission control means for stopping transmission of the serial fuse signal from the first shift register circuit.

According to a fourth aspect of the present invention, the transmission control means shifts the stored signal of the first and second shift register circuits and stops generating a clock signal to be sent out on the signal line, so that the transmission control means stops the generation of the clock signal. The transmission of the serial fuse signal from the first shift register circuit is stopped.

According to a fifth aspect of the present invention, the detecting means adds a specific signal to a fuse signal transmitted from the first shift register circuit to the signal line, and supplies the specific signal to the second shift register circuit side through the signal line. , The timing at which the serial fuse signal has just been input to the second shift register circuit is detected.

A feature of the invention according to claim 6 is that the fuse circuit group and the comparison circuit are arranged apart from each other.

According to a seventh aspect of the present invention, the first and second signal conversion circuits are first and second shift register circuits, and apply the parallel fuse signal to the first shift register circuit for a predetermined period. Load means for loading, and clock generating means for generating a clock for shifting a save signal of the first shift register circuit after the predetermined period and transmitting the signal on the signal line.

The predetermined period of the invention according to claim 8 is that the predetermined period is a predetermined period immediately after power-on.

The feature of the ninth aspect of the present invention is that
A redundancy circuit according to any one of the above embodiments is mounted, and the redundancy circuit has a function of accessing a spare memory cell for a specific input address signal.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the redundancy circuit of the present invention. The redundancy circuit includes an input address signal 50 and a fuse circuit 1.
, Xn input from the comparator circuit 2 to generate a hit signal instructing access to the spare memory cell, and a comparator circuit 11 for accessing the spare memory cell corresponding to the address signal. Fuse circuit section 12 programmed for presence / absence, fuse circuit section 12
, Xn into a serial signal, and a shift register for returning the serial signal sent from the shift register circuit 13 to the original parallel fuse signals X1, X2,. The circuit 14 includes a clock generation circuit 15 for generating an operation clock of the shift register circuit 13, one data signal line 16 connecting the shift register circuit 13 and the shift register circuit 14, and one clock signal line 17. .

FIG. 2 is a block diagram showing a layout example of the redundancy circuit shown in FIG. The comparator circuit 11 and the shift register circuit 14 are arranged on the small block 61 adjacent to the wiring area 62. On the other hand, the fuse circuit section 12, the shift register circuit 13, and the clock generation circuit 15 are arranged at different places away from the comparator circuit 11 and the shift register circuit 14.

FIG. 3 is a block diagram showing a detailed configuration example of the shift register circuits 13 and 14 of the redundancy circuit shown in FIG. 1 and its peripheral circuits. The shift register circuit 13 is connected to the shift register circuit 14 via a set latch 18 via a data signal line 16. The shift register circuit 14 is connected via a reset latch 19 and an inverter 20 to
The control signal line 23 is connected to the clock generation circuit 15. The clock generation circuit 15 generates a clock CK using the pulse A generated from the pulse generation circuit 21 as a trigger. The pulse generation circuit 21 outputs one pulse A to the clock generation circuit 15 in response to the input of the power-on reset signal 101 delayed by the delay circuit 22. The power-on reset signal 100 is directly input to the clock generation circuit 15.

Next, the operation of this embodiment will be described. When the power is turned on, a power-on reset signal 100 is generated as shown in FIG. 6 (A), which is directly input to the clock generation circuit 15 of FIG. 3, and by the delay circuit 22 as shown in FIG. 6 (B). The signal is delayed and becomes a delayed power-on reset signal 101, which is input to the pulse generation circuit 21.

FIG. 4 is a circuit diagram showing a detailed configuration example of the clock generation circuit 15. The above-described power-on reset signal 100 is input to the gate of the transistor 24 and also to the reset terminal R of the RS latch circuit 25. As a result, the transistor 24 is turned on, the output terminal of the clock generation circuit 15 is grounded, the RS latch circuit 25 is reset, and a fuse set signal (low active) 200 is generated during this reset period.
It is output to the shift register circuit 13.

FIG. 5 is a circuit diagram showing a detailed configuration example of the shift register circuit 13. As shown in FIG. The inverter 51 and the switched inverter 52 constitute a 1-bit register, and a paster 53 is connected to an input portion of the register.

A fuse set signal 2 is applied to the paster 53.
Only when the signal 00 is input, the paster 53 conducts, the fuse signal from the fuse circuit 121 is input to the register and held, and thereafter, after a reset period, the fuse set signal 200 becomes high level. As a result, since the paster 53 is cut off, the fuse signal of the fuse circuit 121 is not input to the shift register circuit 13 thereafter.

That is, the shift register circuit 13 loads the parallel fuse signal of the fuse circuit section 12 only while the fuse set signal 200 is being output.

During the period when the power-on reset signal 100 is input and the RS latch circuit 25 is reset, as shown in FIG. 6B, the power-on reset signal 100 is delayed and the pulse generation circuit is reset. The pulse A is not generated from the pulse generation circuit 21, and the pulse A is not generated from the pulse generation circuit 21. Further, since the RS latch circuit 25 is reset, the output of the RS latch circuit 25 is at low level and the NAND circuit 26 is cut off. I have.

Thus, the clock CK is not generated from the clock generation circuit 15 and is not output to the shift register circuit 13. Further, since the output terminal of the clock generation circuit 15 is grounded via the transistor 24 as described above, noise such as a clock signal is not output to the shift register circuit 13.

After that, when the power-on reset signal 100 disappears as shown in FIG. 6A, the delayed power-on reset signal 101 is inputted to the pulse generation circuit 21 as shown in FIG. The pulse A is input from the circuit 21 to the set terminal S of the RS latch circuit 25, and R
In order to set the S latch circuit 25 and set its output to the high level, the NAND circuit 26 is turned on and the generation of the clock CK is started. The generated clock CK is output to the shift register circuit 13.

Thus, the shift register circuit 13 sequentially shifts the stored n-bit fuse signals one by one and sends them out to the data lines 16 via the set latches 18 one by one.

Since "1" is set in the set latch 18 in advance, the shift register circuit 13
The head of the n-bit fuse signal output in order from "1" is "1". The n-bit fuse signal is sequentially input to the shift register circuit 14 through the data line 16. When the n-bit fuse signal is input to the shift register circuit 14, the leading “1” becomes the reset latch 1.
9, the output of the reset latch 19 is set to "1". However, when the power is turned on, the reset latch 19
Is "0", and a signal of "1" is generated from the inverter 20. The signal of "1" is input to the NAND circuit 26 of the clock generation circuit 15 to make the NAND circuit 26 conductive.

When the output of the reset latch 19 becomes "1", a clock stop signal of "0" is generated from the inverter 20 and input to the NAND gate 26 of the clock generation circuit 15. Therefore, NAND gate 2
6 is cut off, the generation of the clock CK is stopped, and the transmission of the fuse signal from the shift register circuit 13 is stopped. At this time, an n-bit fuse signal is stored in the shift register circuit 14, and the n-bit fuse signal is converted into a parallel signal to become a comparator signal.
Is input to

Thereafter, the comparator circuit 11 compares the input address signal with the fuse signal, and outputs a hit signal 60 if the fuse signal indicates that the memory cell to which the address signal is accessed is a defective address. Then, the spare memory cell is accessed by the input address signal.

According to the present embodiment, the fuse circuit section 12 is arranged apart from the comparator circuit 11, and the parallel fuse signal from the fuse circuit section 12 is converted into a serial signal to the comparator circuit 11. By sending, the comparator circuit 11 and the fuse circuit unit 1
A fuse signal can be sent by one data signal line 16 and one clock signal line 17 connected between the two.

As a result, the wiring area 62 adjacent to the small block 61 of the comparator circuit 11 is prevented from being reduced or an unnecessary area is not generated. Moreover, since the wiring area occupied by the signal lines 16 and 17 for transmitting the fuse signal is small, the fuse circuit section 12 can be arranged away from the comparator circuit 11 without increasing the wiring area.

Although the increase in the shift register circuits 13 and 14 inevitably increases the circuit area, the input / output signal lines 16 and 17 of these shift register circuits 13 and 14 affect the speed of the chip body. Since there is no path, the circuit itself does not require a large driving force, can be designed with a small circuit, and requires only a small area increase.

Therefore, even if the comparator circuit 11 and the fuse circuit section 12 are arranged apart from each other, the data signal lines 16 and
The wiring area for the clock signal line 17 and the like can be small, and the number of signal lines to be routed is small, so that the fuse circuit section 12 can be easily separated.
The degree of freedom in the layout of the entire semiconductor device can be improved.

Further, in the automatic wiring CAD, the wiring area is largely reduced due to the restriction of the wiring area by the wiring algorithm. However, as shown in this example, the wiring is reduced by disposing the fuse circuit section 12 apart. Since the hindrance of the degree of freedom of wiring in the region 62 can be avoided, an ideal wiring region can be easily secured.

[0044]

As described above in detail, according to the present invention, the fuse circuit can be arranged apart from the comparator circuit without increasing the wiring area. Accordingly, when the comparator circuit is arranged on the small block array as in the standard cell system, the fuse circuit can be arranged apart from the small block array, and the wiring area adjacent to the small block array can be reduced and unnecessary area can be generated. And an ideal wiring area can be easily secured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a redundancy circuit of the present invention.

FIG. 2 is a block diagram showing a specific arrangement example of the redundancy circuit shown in FIG. 1;

FIG. 3 is a block diagram showing a detailed configuration example of a shift register circuit and its peripheral circuits of the redundancy circuit shown in FIG. 1;

FIG. 4 is a circuit diagram showing a detailed circuit configuration example of the clock generation circuit shown in FIG. 3;

FIG. 5 is a circuit diagram showing a detailed configuration example of a shift register circuit 13 shown in FIG. 3;

FIG. 6 is a timing chart illustrating activation and operation of the shift register circuit illustrated in FIG. 3;

FIG. 7 is a block diagram showing a schematic configuration example of a conventional redundancy circuit.

FIG. 8 is a block diagram showing a detailed configuration example of the redundancy circuit shown in FIG. 7;

FIG. 9 is a circuit diagram showing a specific example of the comparator circuit shown in FIG.

FIG. 10 is a circuit diagram showing a specific example of a fuse circuit constituting the fuse circuit unit shown in FIG.

FIG. 11 is a schematic diagram showing a layout example when small blocks are arranged in an array as in the standard cell system.

FIG. 12 is a diagram illustrating a configuration example of a small block illustrated in FIG. 11;

FIG. 13 is a diagram showing a configuration example when a fuse circuit is made into small blocks.

FIG. 14 is a diagram showing the relationship between the arrangement of the fuse circuits in small blocks and the wiring area.

FIG. 15 is a diagram showing a reduction in a wiring area by an automatic wiring algorithm when a fuse circuit divided into small blocks is arranged.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Comparator circuit 12 Fuse circuit part 13, 14 Shift register circuit 15 Clock generation circuit 16 Data signal line 17 Clock signal line 18 Set latch 19 Reset latch 20, 51 Inverter 21 Pulse generation circuit 22 Delay circuit 23 Control signal line 24 Transistor 25 RS Latch circuit 26 NAND circuit 52 Switched inverter 53 Pastora 121 Fuse circuit 122 Fuse

Continued on the front page F term (reference) 5F064 AA04 DD04 DD24 DD26 EE15 FF02 FF27 FF36 HH03 5F083 GA09 LA10 LA11 ZA10 5L106 CC04 GG06

Claims (9)

[Claims] 1. A fuse circuit group for generating a parallel fuse signal for notifying the presence or absence of access to a spare memory cell for each address signal, and an input address signal and a fuse signal are compared with each other. And a comparison circuit for generating a hit signal instructing access to the memory. In a redundancy circuit for using the spare memory cell for a specific address signal, the parallel fuse signal is converted into a serial fuse signal. A transmission circuit for transmitting the data to the comparison circuit. 2. A fuse circuit group for generating a parallel fuse signal for notifying the presence / absence of access to a spare memory cell for each address signal, and an input address signal and a fuse signal are compared. A redundancy circuit for generating a hit signal for instructing access, wherein the redundancy circuit uses the spare memory cell for a specific input address signal, and converts the parallel fuse signal into a serial fuse signal. A first signal converter, a second signal converter for converting the serial fuse signal into a parallel fuse signal, and a second signal converter for converting the serial fuse signal obtained by the first signal converter into the second signal. And a signal line for transmitting to the conversion means. 3. The first and second signal conversion circuits are first and second shift register circuits, and the serial fuse signal transmitted from the first shift register circuit through the signal line. The second
Detection means for detecting the timing just input to the shift register circuit, and transmission control means for stopping transmission of the serial fuse signal from the first shift register circuit when the timing is detected, 3. The redundancy circuit according to claim 2, comprising: 4. The transmission control means according to claim 1, wherein said transmission control means shifts a signal stored in said first shift register circuit and stops generating a clock signal to be sent out on said signal line, whereby said first shift register circuit outputs said signal. 4. The redundancy circuit according to claim 3, wherein the transmission of the serial fuse signal is stopped. 5. The detection means adds a specific signal to a fuse signal sent from the first shift register circuit to the signal line, and is sent to the second shift register circuit side through the signal line. 4. The redundancy circuit according to claim 3, wherein a timing at which the serial fuse signal has just been input to the second shift register circuit is detected by detecting the specific signal. 6. The redundancy circuit according to claim 1, wherein the fuse circuit group and the comparison circuit are separated from each other. 7. The load means for loading the parallel fuse signal into the first shift register circuit for a predetermined period, wherein the first and second signal conversion circuits are first and second shift register circuits. 4. A clock generating means for generating a clock for shifting a signal stored in the first shift register circuit and transmitting the signal on the signal line after the predetermined period. Redundancy circuit. 8. The redundancy circuit according to claim 7, wherein said predetermined period is a certain period immediately after power-on. 9. A semiconductor device comprising the redundancy circuit according to claim 1, wherein the redundancy circuit has a function of accessing a spare memory cell with respect to a specific input address signal. apparatus.