JP2000164756A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2000164756A JP2000164756A JP10336004A JP33600498A JP2000164756A JP 2000164756 A JP2000164756 A JP 2000164756A JP 10336004 A JP10336004 A JP 10336004A JP 33600498 A JP33600498 A JP 33600498A JP 2000164756 A JP2000164756 A JP 2000164756A
- Authority
- JP
- Japan
- Prior art keywords
- resin substrate
- adhesive
- semiconductor device
- semiconductor element
- porous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Adhesive Tapes (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、樹脂基板の接着剤
を介して半導体素子が搭載される半導体装置に関する。The present invention relates to a semiconductor device on which a semiconductor element is mounted via an adhesive on a resin substrate.
【０００２】[0002]
【従来の技術】従来、図３に示すような、スルーホール
２１および導電パターン２２が形成された樹脂基板２
３、樹脂基板の半導体素子搭載面２４に接着剤２５を介
して搭載された半導体素子２６、半導体素子２６の電極
と導電パターン２２を導通するワイヤー２７、半導体素
子２６、接着剤２５、ワイヤー２７及び導電パターン２
２を封止する封止樹脂２８、スルーホールを通って導電
パターンと導通する半田ボール部２９からなる半導体装
置が用いられることがあった。2. Description of the Related Art Conventionally, as shown in FIG. 3, a resin substrate 2 on which a through hole 21 and a conductive pattern 22 are formed.
3, a semiconductor element 26 mounted on the semiconductor element mounting surface 24 of the resin substrate via an adhesive 25, a wire 27 for conducting an electrode of the semiconductor element 26 to the conductive pattern 22, a semiconductor element 26, an adhesive 25, a wire 27, Conductive pattern 2
In some cases, a semiconductor device including a sealing resin 28 for sealing 2 and a solder ball portion 29 electrically connected to the conductive pattern through a through hole is used.
【０００３】この半導体装置は、スルーホール２１及び
導電パターン２２が形成された樹脂基板２３の半導体素
子搭載面２４に接着剤２５を介して半導体素子２６を搭
載し、導電パターン２２と半導体素子２６の電極をワイ
ヤー２７により導通し、封止樹脂２８により半導体素子
２６と接着剤２５とワイヤー２７と導電パターン２２を
封止し、スルーホール２１上に球状半田を搭載してリフ
ローすることにより半田ボール部２９を形成することに
より製造される。In this semiconductor device, a semiconductor element 26 is mounted via an adhesive 25 on a semiconductor element mounting surface 24 of a resin substrate 23 on which a through hole 21 and a conductive pattern 22 are formed. The electrodes are electrically connected by wires 27, the semiconductor element 26, the adhesive 25, the wires 27, and the conductive patterns 22 are sealed by a sealing resin 28, and a spherical solder is mounted on the through holes 21 and reflowed to form a solder ball portion. 29.
【０００４】[0004]
【発明が解決しようとする課題】従来の半導体装置で
は、半田ボール部２９の形成におけるリフロー時、半導
体装置実装時および耐熱性検査時等に加熱されると、接
着剤２５からガスや水蒸気が発生し、封止樹脂２８と樹
脂基板２３が剥離することや封止樹脂２８が破損するこ
とがあった。In the conventional semiconductor device, when the solder ball portion 29 is heated at the time of reflow, at the time of mounting the semiconductor device, or at the time of heat resistance test, gas or water vapor is generated from the adhesive 25. However, the sealing resin 28 may be separated from the resin substrate 23 or the sealing resin 28 may be damaged.
【０００５】このような現象は、パッケージクラックと
呼ばれ、半導体装置の製造過程において大きな問題とな
っていた。[0005] Such a phenomenon is called a package crack and has been a serious problem in the process of manufacturing a semiconductor device.
【０００６】また、近年、半導体装置の高集積化が進む
中で、パッケージサイズを小さくすることが要望され、
半導体素子のサイズに近づけた半導体装置が提案されて
いる。Further, in recent years, as semiconductor devices have become more highly integrated, it has been demanded to reduce the package size.
There has been proposed a semiconductor device having a size close to that of a semiconductor element.
【０００７】このような半導体装置においては、樹脂基
板と封止樹脂の接触面積が小さくなるためパッケージク
ラックが発生する可能性が高くなり、さらに大きな問題
となっていた。[0007] In such a semiconductor device, the contact area between the resin substrate and the sealing resin is reduced, so that the possibility of occurrence of package cracks increases, which has been a further problem.
【０００８】本発明の目的は、樹脂基板の半導体素子搭
載面に接着剤を介して半導体素子が搭載される半導体装
置であって、接着剤から発生するガスや水蒸気により、
パッケージクラックが発生することを防止できる半導体
装置を提供することにある。An object of the present invention is to provide a semiconductor device in which a semiconductor element is mounted on a semiconductor element mounting surface of a resin substrate via an adhesive.
An object of the present invention is to provide a semiconductor device capable of preventing occurrence of a package crack.
【０００９】[0009]
【課題を解決するための手段】本発明の特徴は、樹脂基
板の素子搭載面に接着剤を介して半導体素子が搭載され
る半導体装置であって、前記樹脂基板が通気性を有する
多孔樹脂基板であり、前記樹脂基板の少なくとも一部が
露出していることをにある。A feature of the present invention is a semiconductor device in which a semiconductor element is mounted on an element mounting surface of a resin substrate via an adhesive, wherein the resin substrate has air permeability. And at least a part of the resin substrate is exposed.
【００１０】また、特には、前記樹脂基板の前記素子搭
載面と反対の面の、接着剤搭載領域と対抗する領域が露
出していることにある。[0010] In particular, a region of the resin substrate opposite to the element mounting surface is exposed to a region opposed to the adhesive mounting region.
【００１１】また、特には、前記多孔樹脂基板は、多孔
性フッ素樹脂からなることにある。[0011] In particular, the porous resin substrate is made of a porous fluororesin.
【００１２】また、特には、前記多孔樹脂基板は、接着
剤が素子搭載面と反対の面に流出しない孔径の貫通穴が
形成された樹脂基板であることにある。Further, in particular, the porous resin substrate is a resin substrate in which a through-hole having a hole diameter such that an adhesive does not flow out to the surface opposite to the element mounting surface is formed.
【００１３】[0013]
【発明の実施形態】本発明の実施形態の半導体装置は、
半導体素子搭載面と外部導通面からなる樹脂基板、樹脂
基板に接着剤を介して搭載された半導体素子、半導体素
子搭載面に形成されて半導体素子の電極とワイヤーを介
して導通された導電パターン、導電パターンと樹脂基板
のスルーホールを介して導通されて外部導通面に形成さ
れる半田ボール部、樹脂基板の半導体素子搭載面に形成
されて半導体素子と接着剤とワイヤーと導電パターンを
封止する封止樹脂からなり、半導体素子電極がワイヤー
及び導電パターンを介して外部端子と導通されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention
A resin substrate comprising a semiconductor element mounting surface and an external conductive surface, a semiconductor element mounted on the resin substrate via an adhesive, a conductive pattern formed on the semiconductor element mounting surface and electrically connected to the electrodes of the semiconductor element via wires, A solder ball portion formed on the external conductive surface by conduction through the conductive pattern and the through hole of the resin substrate, and formed on the semiconductor element mounting surface of the resin substrate to seal the semiconductor element, the adhesive, the wire, and the conductive pattern. The semiconductor element electrode is made of a sealing resin, and is electrically connected to an external terminal via a wire and a conductive pattern.
【００１４】本実施形態の半導体装置の製造方法は、ス
ルーホール及び導電パターンが形成された樹脂基板に接
着剤を介して半導体素子を搭載し、半導体素子電極と導
電パターンをワイヤーボンディングして導通させ、半導
体素子と接着剤とワイヤーと導電パターンを封止樹脂に
より封止し、樹脂基板の外部導通面に半田ボール部が形
成されスルーホールを介して導電パターンと導通する外
部端子を搭載する。In the method of manufacturing a semiconductor device according to the present embodiment, a semiconductor element is mounted via an adhesive on a resin substrate on which a through hole and a conductive pattern are formed, and the semiconductor element electrode and the conductive pattern are electrically connected by wire bonding. The semiconductor element, the adhesive, the wires, and the conductive pattern are sealed with a sealing resin, and a solder ball portion is formed on an external conductive surface of the resin substrate, and an external terminal that is connected to the conductive pattern via a through hole is mounted.
【００１５】ここにおいて、外部端子は、外部導通面の
スルーホール上に球状半田が搭載され、リフローするこ
とにより形成される。Here, the external terminal is formed by mounting a spherical solder on the through hole of the external conduction surface and reflowing.
【００１６】リフロー時において半導体装置は加熱さ
れ、接着剤も加熱される。At the time of reflow, the semiconductor device is heated, and the adhesive is also heated.
【００１７】接着剤が加熱されると、接着剤に吸湿され
た水分が気化し、水蒸気とガスが発生する。When the adhesive is heated, the moisture absorbed by the adhesive is vaporized, generating water vapor and gas.
【００１８】しかしながら、本実施形態の樹脂基板は、
通気性を有する多孔樹脂基板から形成されており、前記
水蒸気とガスは樹脂基板の露出部から外部に排出され
る。However, the resin substrate of this embodiment is
It is formed of a porous resin substrate having air permeability, and the water vapor and gas are discharged to the outside from an exposed portion of the resin substrate.
【００１９】これにより、リフロー時におけるパッケー
ジクラックを防止することができる。Thus, it is possible to prevent a package crack during reflow.
【００２０】[0020]
【実施例】以下、本発明の実施例につき図面を用い詳細
に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.
【００２１】[0021]
【実施例１】本実施例の半導体装置は、図１（ａ）に断
面図及び図1（ｂ）に底面図を示す通りであり、半導体
素子搭載面１と外部導通面２からなる多孔樹脂基板３、
多孔樹脂基板３に熱硬化性の接着剤４を介して搭載され
た半導体素子５、半導体素子搭載面１に形成されて半導
体素子５の電極とワイヤー６を介して導通された導電パ
ターン７、外部導通面２に形成され導電パターン７と多
孔樹脂基板３のスルーホール８を介して導通される半田
ボール部９、多孔樹脂基板３の半導体素子搭載面１に形
成され半導体素子５と接着剤４とワイヤー６と導電パタ
ーン７を封止する封止樹脂１０からなり、半導体素子５
の電極がワイヤー６及び導電パターン７を介して外部導
通端子である半田ボール部９と導通されている。Embodiment 1 A semiconductor device of this embodiment is shown in FIG. 1 (a) as a cross-sectional view and FIG. 1 (b) as a bottom view, and shows a porous resin comprising a semiconductor element mounting surface 1 and an external conduction surface 2. Substrate 3,
A semiconductor element 5 mounted on the porous resin substrate 3 via a thermosetting adhesive 4, a conductive pattern 7 formed on the semiconductor element mounting surface 1 and electrically connected to an electrode of the semiconductor element 5 via a wire 6, A solder ball portion 9 formed on the conductive surface 2 and electrically connected to the conductive pattern 7 through the through hole 8 of the porous resin substrate 3; a semiconductor element 5 and an adhesive 4 formed on the semiconductor element mounting surface 1 of the porous resin substrate 3; The semiconductor element 5 is made of a sealing resin 10 for sealing the wire 6 and the conductive pattern 7.
Are electrically connected to the solder ball portion 9 as an external conductive terminal via the wire 6 and the conductive pattern 7.
【００２２】多孔樹脂基板３は、厚さ６０μｍであり、
多孔性フッ素樹脂であるポリテトラルフオロエチレンか
らなる樹脂シートを加工して形成されたものであり、通
気性を有している。The porous resin substrate 3 has a thickness of 60 μm,
It is formed by processing a resin sheet made of polytetrafluoroethylene, which is a porous fluororesin, and has air permeability.
【００２３】また、上記半導体装置の製造方法は、ま
ず、多孔樹脂テープ素材を加工してスルーホール８及び
導電パターン７が形成された多孔樹脂テープ３が複数形
成されたフレームを形成し、次に、多孔樹脂テープ３の
半導体素子搭載面１における半導体素子搭載領域に接着
剤４を塗布し、接着材４上に半導体素子５を搭載し、リ
フローすると接着剤４が硬化し、半導体素子５が多孔樹
脂基板３に接着される。In the method of manufacturing a semiconductor device, a frame is first formed by processing a porous resin tape material to form a plurality of porous resin tapes 3 having through holes 8 and conductive patterns 7 formed thereon. Then, an adhesive 4 is applied to the semiconductor element mounting area on the semiconductor element mounting surface 1 of the porous resin tape 3, the semiconductor element 5 is mounted on the adhesive 4, and the adhesive 4 is cured by reflow, and the semiconductor element 5 becomes porous. It is bonded to the resin substrate 3.
【００２４】次に、半導体素子５の電極と導電パターン
７をワイヤー６により接続するワイヤーボンディング工
程を行い、次に、封止樹脂１０により半導体素子５、接
着剤４、ワイヤー６、導電パターン７を封止するモール
ド工程を行う。Next, a wire bonding step of connecting the electrode of the semiconductor element 5 and the conductive pattern 7 with the wire 6 is performed, and then the semiconductor element 5, the adhesive 4, the wire 6, and the conductive pattern 7 are sealed with the sealing resin 10. A molding step for sealing is performed.
【００２５】次に、外部導通面２のスルーホール８上に
球状半田を搭載し、リフローすることにより半田ボール
部９を形成し、フレームから個々の半導体装置に分離し
て半導体装置を完成させる。Next, a spherical solder is mounted on the through hole 8 of the external conduction surface 2 and reflowed to form a solder ball portion 9 and separated from the frame into individual semiconductor devices to complete the semiconductor device.
【００２６】完成した半導体装置は、検査を経てマザー
ボードに実装される。The completed semiconductor device is mounted on a mother board after inspection.
【００２７】以上に述べた本実施例によれば、半田ボー
ル形成時、マザーボード実装時及び耐熱性検査等におい
て、加熱された場合、接着剤４に吸湿された水分が気化
し、ガスや水蒸気が発生しても、多孔樹脂基板３の接着
剤４と接している領域から多孔樹脂基板３内にガスや水
蒸気が吸収され、多孔樹脂基板３の露出されている部分
から半導体装置外へ排出される。According to the present embodiment described above, when solder balls are formed, when mounted on a mother board, and when inspected for heat resistance, etc., when heated, the moisture absorbed by the adhesive 4 evaporates, and gas and water vapor are removed. Even if it occurs, gas or water vapor is absorbed into the porous resin substrate 3 from the region of the porous resin substrate 3 which is in contact with the adhesive 4 and is discharged out of the semiconductor device from the exposed portion of the porous resin substrate 3. .
【００２８】また、本実施例の多孔樹脂基板３は多孔性
フッ素樹脂であるポリテトラルフオロエチレンからなる
ため、接着剤４が反対の面に流出することなく通気性を
持たせることができ、加工性や耐熱性も優れている。Since the porous resin substrate 3 of this embodiment is made of polytetrafluoroethylene, which is a porous fluororesin, the adhesive 4 can have air permeability without flowing out to the opposite surface. Excellent workability and heat resistance.
【００２９】また、本実施例では、ポリテトラルフオロ
エチレンを使用したが、これは任意であり、ＰＦＡ、Ｆ
ＥＰ、ＥＴＦＥ等の通気性を有する多孔フッ素樹脂でも
よい。Further, in this embodiment, polytetrafluoroethylene was used, but this is arbitrary, and PFA, F
A porous fluororesin having air permeability such as EP and ETFE may be used.
【００３０】[0030]
【実施例２】以下、本発明のもう一つの実施例つき図面
を用い詳細に説明する。Embodiment 2 Hereinafter, another embodiment of the present invention will be described in detail with reference to the accompanying drawings.
【００３１】本実施例の半導体装置は、多孔樹脂基板３
の材質以外は実施例１と同様であり、製造方法も同様で
ある。The semiconductor device according to the present embodiment has a porous resin substrate 3
Are the same as in Example 1 except for the material, and the manufacturing method is also the same.
【００３２】本実施例の多孔樹脂基板３は、厚さが２５
μｍのポリイミドテープから形成されており、図２に示
すように孔径３０μｍの貫通孔１１が多数形成されてい
る。The porous resin substrate 3 of this embodiment has a thickness of 25
It is formed from a μm polyimide tape, and has a large number of through holes 11 having a hole diameter of 30 μm as shown in FIG.
【００３３】このような貫通孔１１をポリイミドテープ
に形成する方法としては、レーザーによる加工方法があ
り、特にエキシマレーザー加工を用いれば底面に残留物
や飛散物が残ることも少なく、良好に貫通孔１１を形成
することができる。As a method for forming such a through hole 11 in a polyimide tape, there is a processing method using a laser. Particularly, when excimer laser processing is used, there is little residue or scattered matter remaining on the bottom surface, and the through hole is preferably formed. 11 can be formed.
【００３４】以上の本実施例によれば、孔径３０μｍの
貫通孔１１が多数形成されているので、接着剤４塗布工
程において接着剤が反対の面に流出することなく、接着
剤４から発生するガスや水蒸気を貫通孔１１から排出す
ることができ、パッケージクラックの発生を防止するこ
とができる。According to the above embodiment, since a large number of through holes 11 having a hole diameter of 30 μm are formed, the adhesive is generated from the adhesive 4 without flowing out to the opposite surface in the adhesive 4 applying step. Gas and water vapor can be discharged from the through-hole 11, and the occurrence of package cracks can be prevented.
【００３５】本実施例において、貫通穴１１を孔径３０
μｍとしたが、これは任意であり、接着剤が反対の面に
流出しない孔径であればよく、接着剤の種類により異な
るが孔径５０μｍ未満の貫通孔であれば本発明の効果を
得ることができる。In this embodiment, the through hole 11 has a hole diameter of 30.
Although it was set to μm, this is arbitrary, and it is sufficient if the pore size does not allow the adhesive to flow out to the opposite surface, and if the through hole has a pore size of less than 50 μm depending on the type of the adhesive, the effect of the present invention can be obtained. it can.
【００３６】また、本実施例では板厚２５μｍのポリイ
ミドテープを用いたが、これは任意であり、他の板厚で
もよい。In this embodiment, a polyimide tape having a thickness of 25 μm is used. However, this is arbitrary, and other thicknesses may be used.
【００３７】以上の２つの実施例においては、外部導通
面２の接着剤４塗布領域と対抗する領域が露出されてい
るので、ガスや水蒸気を吸収する領域と排出する領域の
距離が短かく、効率良くガスや水蒸気を排出することが
できる。In the above two embodiments, since the area opposite to the area where the adhesive 4 is applied on the external conductive surface 2 is exposed, the distance between the area for absorbing gas and water vapor and the area for discharging is short, and Gas and water vapor can be efficiently discharged.
【００３８】また、多孔樹脂基板３として、実施例１で
は多孔性フッ素樹脂、実施例２では３０μｍの貫通孔１
１が多数形成されているポリイミドテープを用いたがこ
れは任意であり、接着剤が他方の面に流出せずに通気性
を有している多孔樹脂基板であればよく、また、厚さも
任意であり限定されるものではない。Further, as the porous resin substrate 3, a porous fluororesin is used in the first embodiment, and a 30 μm through hole 1 is used in the second embodiment.
Although a polyimide tape in which a large number of 1 were formed was used, this is optional, and any adhesive may be used as long as it is a porous resin substrate that does not allow the adhesive to flow out to the other surface and has air permeability. And is not limited.
【００３９】また、本実施例において、接着剤としてペ
ース途上のものを使用したが、これは任意であり、テー
プ状の接着剤でも同様の作用効果が生じる。In the present embodiment, the adhesive in the middle of the pace is used as the adhesive. However, the adhesive is optional, and a tape-like adhesive produces the same effect.
【００４０】[0040]
【発明の効果】以上の本発明によれば、樹脂基板が通気
性を有する多孔樹脂基板から形成されており、接着剤か
ら発生する水蒸気とガスが樹脂基板の露出部から外部に
排出されるため、リフロー時等におけるパッケージクラ
ックの発生を防止することができる。According to the present invention described above, the resin substrate is formed of a porous resin substrate having air permeability, and the water vapor and gas generated from the adhesive are discharged to the outside from the exposed portion of the resin substrate. Also, it is possible to prevent the occurrence of package cracks at the time of reflow or the like.
【００４１】[0041]
【図１】本発明の実施例１における半導体装置を示す図
である。FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の実施例２における半導体装置の多孔樹
脂基板を示す図である。FIG. 2 is a diagram illustrating a porous resin substrate of a semiconductor device according to a second embodiment of the present invention.
【図３】従来の半導体装置を示す図である。FIG. 3 is a diagram showing a conventional semiconductor device.
１ 半導体素子搭載面 ２ 外部導通面 ３ 多孔樹脂基板 ４ 接着剤 ５ 半導体素子 ６ ワイヤー ７ 導電パターン ８ スルーホール ９ 半田ボール部 １０ 封止樹脂 １１ 貫通孔 ２１ スルーホール ２２ 導電パターン ２３ 樹脂基板 ２４ 半導体素子搭載面 ２５ 接着剤 ２６ 半導体素子 ２７ ワイヤー ２８ 封止樹脂 ２９ 半田ボール部 REFERENCE SIGNS LIST 1 semiconductor element mounting surface 2 external conduction surface 3 porous resin substrate 4 adhesive 5 semiconductor element 6 wire 7 conductive pattern 8 through hole 9 solder ball portion 10 sealing resin 11 through hole 21 through hole 22 conductive pattern 23 resin substrate 24 semiconductor element Mounting surface 25 Adhesive 26 Semiconductor element 27 Wire 28 Sealing resin 29 Solder ball part
Claims (4)
半導体素子が搭載される半導体装置であって、前記樹脂
基板は通気性を有する多孔樹脂基板であり、少なくとも
一部が露出していることを特徴とする半導体装置。1. A semiconductor device having a semiconductor element mounted on an element mounting surface of a resin substrate via an adhesive, wherein the resin substrate is a porous resin substrate having air permeability, and at least a part of the resin substrate is exposed. A semiconductor device.
面の、接着剤搭載領域と対抗する領域が露出しているこ
とを特徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein a region opposing an adhesive mounting region on a surface of the porous resin substrate opposite to the element mounting surface is exposed.
からなることを特徴とする請求項1又は請求項2に記載さ
れている半導体装置。3. The semiconductor device according to claim 1, wherein the porous resin substrate is made of a porous fluororesin.
面と反対の面に流出しない孔径の貫通穴が形成された樹
脂基板であることを特徴とする請求項１又は請求項２に
記載の半導体装置。4. The resin substrate according to claim 1, wherein the porous resin substrate is a resin substrate having a through-hole having a hole diameter such that an adhesive does not flow out on a surface opposite to a surface on which the element is mounted. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10336004A JP2000164756A (en) | 1998-11-26 | 1998-11-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10336004A JP2000164756A (en) | 1998-11-26 | 1998-11-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000164756A true JP2000164756A (en) | 2000-06-16 |
Family
ID=18294708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10336004A Pending JP2000164756A (en) | 1998-11-26 | 1998-11-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000164756A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10432867B2 (en) | 2012-04-25 | 2019-10-01 | Sony Corporation | Imaging apparatus and display control method for self-portrait photography |
-
1998
- 1998-11-26 JP JP10336004A patent/JP2000164756A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10432867B2 (en) | 2012-04-25 | 2019-10-01 | Sony Corporation | Imaging apparatus and display control method for self-portrait photography |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH08167678A (en) | Semiconductor device | |
| JP2000031327A (en) | Semiconductor device and its manufacture | |
| TW200935573A (en) | Insulative wiring board, semiconductor package using the same, and method for producing the insulative wiring board | |
| JPH06204272A (en) | Manufacture of semiconductor device | |
| JP2000277649A (en) | Semiconductor and manufacture of the same | |
| JP3939847B2 (en) | Manufacturing method of semiconductor device | |
| JPH1174312A (en) | Semiconductor device and method for forming solder bump | |
| US20020079578A1 (en) | Semiconductor device having exposed adhesive sheet and method for manufacturing the same | |
| JP3485509B2 (en) | Flip chip type semiconductor device and manufacturing method thereof | |
| JP2000150716A (en) | Package structure and semiconductor device, manufacture of package and semiconductor device | |
| JP2000164756A (en) | Semiconductor device | |
| JP2002329825A (en) | Method of removing uncontrolled void in adhesive layer of sheet | |
| JP2001332642A (en) | Semiconductor device and manufacturing method thereof | |
| JP3394479B2 (en) | Semiconductor device | |
| JP2001230267A (en) | Semiconductor device and manufacturing method | |
| JP3070544B2 (en) | Ball grid array type semiconductor device | |
| JP3827407B2 (en) | Semiconductor mounting substrate | |
| JPH11284096A (en) | Semiconductor package | |
| JPH10163256A (en) | Chip supporting board for semiconductor device | |
| JP2004047563A (en) | Semiconductor device | |
| JP2003163240A (en) | Semiconductor device and manufacturing method therefor | |
| US20040124006A1 (en) | Built up lands | |
| JP4709521B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| KR100481424B1 (en) | Method for manufacturing chip scale package | |
| KR101133126B1 (en) | Semiconductor package and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040301 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040309 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20040817 |