JP2000150665A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the realiability of an MISFET(metal insulator semiconductor field effect transistor) comprised of thin insulation film in a semiconductor integrated circuit device which is provided with the MISFET comprised of thin gate insulation film and MISFET comprised of thin gate insulation film. SOLUTION: This semiconductor integrated circuit device is provided with a gate insulation film of an n-channel type MISFET Qn and a p-channel type MISFET Qp which are formed in an area of 1.8 V system, and the gate insulation film comprises a first silicon oxide film 1b with a thickness of about 8 nm and a second silicon oxide film 1b with a thickness of about 4 nm. The first thick silicon oxide film 1a is formed on the end part of an active area 9b in contact with a shallow groove isolation SGI formed in an element isolation area, so that the leak current failure or deterioration of breakdown strength in the gate insulation film can be prevented in the n-channel type MISFET Qn and p-channel type MISFET Qp formed in the area of 1.8 V system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a MISFET (Metal Insulator Semiconducer) formed by a thin gate insulating film.
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a tor field effect transistor (MIS) and a MISFET formed of a thick gate insulating film.

[0002]

2. Description of the Related Art CMOS (Complementary Metal Oxide)
Semiconductor) Logic LSI (LargeScale Integrated)
Circuit) and SRAM (Static Rand)
Om Access Memory) or DRAM
(Dynamic Random Access Me
memory) mounted on a CMOS logic LSI.
The power supply voltages of the internal circuit and the input / output circuit may be different. For example, in a CMOS logic LSI aiming at high speed,
Since the length (gate length) of the gate electrode of the MISFET of the internal circuit is shorter than the gate length of the MISFET of the input / output circuit, in order to ensure the withstand voltage of the semiconductor region forming the source and drain of the MISFET of the internal circuit, The power supply voltage of the circuit is set lower than the power supply voltage of the input / output circuit.

Further, the MI of an input / output circuit having a high power supply voltage
The reliability of the gate insulating film is ensured by making the thickness of the gate insulating film of the SFET larger than the thickness of the gate insulating film of the MISFET of the internal circuit having a low power supply voltage.
For example, C having a gate electrode of 0.25 μm length is provided.
In a CMOS logic LSI having a MOSFET in an internal circuit, the power supply voltage of the internal circuit is 1.8 V, the power supply voltage of the input / output circuit is 3.3 V, and the thickness of the gate insulating film of the MISFET of the internal circuit is about 4 nm. The thickness of the gate insulating film of the MISFET of the output circuit is about 8 nm.

By the way, as a method of forming two types of gate insulating films having different thicknesses on a semiconductor substrate composed of silicon single crystal, first, a field insulating film is formed in an element isolation region on a main surface of the semiconductor substrate. Is formed, a first thermal oxidation process is performed on the semiconductor substrate to form a first surface on the surface of the semiconductor substrate.
Then, the first silicon oxide film in the active region where the thin gate insulating film is to be formed is removed by wet etching.
A method of forming a second silicon oxide film on the surface of a semiconductor substrate by performing a second thermal oxidation treatment is employed.

That is, the thin gate insulating film is formed by the second silicon oxide film formed by the second thermal oxidation process, and the thick gate insulating film is formed by the first thermal oxidation process and the second thermal oxidation process. And a second silicon oxide film to be formed.

[0006] As an example of a semiconductor integrated circuit device having a MISFET constituted by a thin gate insulating film and a MISFET constituted by a thick gate insulating film, "Nikkei Micro Device" published by Nikkei McGraw-Hill Co., Ltd.
D described in the March 1996 issue, P54 to P59
There is RAM embedded logic.

[0007]

However, the present inventor has found that the above-described method of forming two types of gate insulating films having different thicknesses on the surface of a semiconductor substrate has the following problems.

That is, when the first silicon oxide film in the active region where the thin gate insulating film is to be formed is removed by wet etching, the field insulating film formed in the inter-element isolation region is shaved and the end of the element isolation region is removed. The phenomenon that the upper surface of the field insulating film was lower than the surface of the semiconductor substrate in the portion occurred.

As shown in FIG. 14, a threshold voltage control layer 22 having a depth of about 10 nm for controlling a threshold voltage of a MISFET is formed on the surface of a semiconductor substrate 21. The depth of the field insulating film 24 cut at the end of the element isolation region 23 is about 12 nm, and the side wall of the semiconductor substrate 21 where the threshold voltage control layer 22 is not formed is exposed. Therefore, the electric field concentrates on the edge of the active region of the semiconductor substrate 21, and furthermore, the semiconductor substrate 21
Is formed on the side wall of the MISFET, and the drain current (I _ds ) -gate voltage (V _g ) characteristic of the MISFET composed of the thin gate insulating film 25 is kinked (Kink) to cause a leakage current defect. It was thought to be caused. Further, since the thin gate insulating film 25 covers the end of the active region of the semiconductor substrate 21 where the electric field is concentrated, the thin gate insulating film 25 is likely to have a withstand voltage failure.

An object of the present invention is to provide a semiconductor integrated circuit device having a MISFET constituted by a thin gate insulating film and a MISFET constituted by a thick gate insulating film.
An object of the present invention is to provide a technique capable of improving the reliability of an FET.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention has a first MISFET constituted by a first gate insulating film and a second MISFET constituted by a second gate insulating film. The first gate insulating film is formed of a first MIS
A first insulating film provided at an end of the first active region where the FET is formed, and a second insulating film provided at a position other than the end of the first active region; The thickness of the insulating film is relatively larger than the thickness of the second insulating film, and is the same as the thickness of the third insulating film forming the second gate insulating film.

(2) The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a semiconductor integrated circuit device according to (1), wherein the first MISFET surrounded by the field insulating film is formed on the semiconductor substrate. Forming a first active region to be formed and a second active region in which a second MISFET is formed; and performing a heat treatment on the semiconductor substrate,
Forming an insulating film on the surfaces of the first active region and the second active region; and forming a region around the first active region where a gate electrode constituting at least the first MISFET is formed and a second region. Covering the active region with a resist film;
Using the resist film as a mask, removing the exposed insulating film; and, after removing the resist film, performing a heat treatment on the semiconductor substrate to form a first active region on the first active region where the insulating film remains. Forming an insulating film, forming a second insulating film in the first active region where no insulating film remains, and forming a third insulating film in the second active region.

According to the above means, the first MISFE
And a first insulating film provided at an end of the first active region is a second MISF.
Since the ET is formed in the same manufacturing process as the third insulating film constituting the second gate insulating film, the end of the field insulating film in contact with the first active region below the gate electrode of the first MISFET is shaved. The amount is equal to the amount of shaving of the end of the field insulating film in contact with the second active region below the gate electrode of the second MISFET, and is equal to the amount of semiconductor in the first active region below the gate electrode of the first MISFET. The amount of exposure of the side wall of the substrate is
The amount of exposure is the same as the amount of exposure of the side wall of the semiconductor substrate in the second active region below the gate electrode of the second MISFET. Further, the thickness of the first insulating film forming a part of the first gate insulating film is the same as the thickness of the third insulating film forming the second gate insulating film. Accordingly, the operating characteristics of the first MISFET are relatively thinner than the first insulating film and the third insulating film, and the second insulating film forming another part of the first gate insulating film. Controlled by the film, the first MISFET
The characteristic of the parasitic MISFET is that the second MISFET
Is equivalent to the characteristic of the parasitic MISFET of FIG.
A kink characteristic that causes a leakage current defect is less likely to appear in the ISFET. Also, the first MISFET's first
The second insulating film forming another part of the gate insulating film of
Since the end portion of the semiconductor substrate in the first active region where the electric field is concentrated is not covered, the first gate insulating film is less likely to have a withstand voltage defect.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 shows a CM according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate showing a MISFET of an OS logic LSI, which is a cross-sectional view in a direction in which a gate electrode configuring the MISFET extends. Qn is an n-channel type M
ISFET and Qp indicate p-channel MISFETs.

As shown in FIG. 1, the gate insulating films of the n-channel type MISFET Qn and the p-channel type MISFET Qp formed in the 1.8 V type region have a first silicon oxide film 1a having a thickness of about 8 nm. And a second silicon oxide film 1b having a thickness of about 4 nm, and a shallow trench isolation S formed in the element isolation region.
The first silicon oxide film 1a is formed at an end of the active region in contact with the GI.

On the other hand, an n-channel MISFET Qn and a p-channel MISFE formed in a 3.3 V system region
The gate insulating film of TQp is formed of a first silicon oxide film 1a having a uniform thickness of about 8 nm.

Next, a CMO according to an embodiment of the present invention will be described.
FIG. 2 shows a method of manufacturing a MISFET constituting an S logic LSI.
This will be described with reference to FIG. 2 to 5, 8 to 11
FIG. 6 is a cross-sectional view of a main part of the semiconductor substrate in a direction in which a gate electrode of the MISFET extends. FIGS. 6 and 7 are plan views of a main part of the MISFET.
FIG. 4 is a sectional view of a principal part of a semiconductor substrate, which is perpendicular to a direction in which a gate electrode of the MISFET extends.

First, as shown in FIG. 2, a p-type semiconductor substrate 2 having a specific resistance of about 10 Ωcm is prepared, and a shallow groove 3 is formed on the main surface of the semiconductor substrate 2. The depth of the shallow groove 3 is, for example, 0.35 μm. Thereafter, a thermal oxidation process is performed on the semiconductor substrate 2 to form a silicon oxide film (not shown). After the silicon oxide film 4 is further deposited, the silicon oxide film 4 is polished by a chemical mechanical polishing (CMP) method to leave the silicon oxide film 4 only in the shallow groove 3, thereby forming a shallow groove isolation SGI. by this,
An active region 9a surrounded by a shallow trench isolation SGI is formed in a 3.3V region, and an active region 9b surrounded by a shallow trench isolation SGI is formed in a 1.8V region.

Next, as shown in FIG.
A p-type impurity such as B
(Boron) is ion-implanted to form a p-type well 5, and n is formed in a region where a p-channel type MISFET Qp is formed.
An n-type well 6 is formed by ion implantation of a type impurity, for example, P (phosphorus). Subsequent to the ion implantation, an impurity for adjusting the threshold voltage of the MISFET, for example, BF ₂ (boron fluoride) is ion-implanted into each of the p-type well 5 and the n-type well 6. Then, a threshold voltage control layer 7 is formed. The depth of the threshold voltage control layer 7 from the surface of the semiconductor substrate 2 is, for example, about 10 nm.

Next, as shown in FIG. 4, after the surfaces of the p-type well 5 and the n-type well 6 are cleaned using an HF (hydrofluoric acid) -based aqueous solution, the semiconductor substrate 2 is wet at about 850 ° C. Oxidation forms a clean silicon oxide film 8 having a thickness of about 8 nm on each surface of the p-type well 5 and the n-type well 6. Silicon oxide film 4 constituting shallow groove isolation SGI by cleaning using the above-mentioned HF-based aqueous solution
Is etched, especially the shallow groove isolation S
At the end of the GI, a silicon oxide film 4 of about 5 to 10 nm
Is etched.

Next, as shown in FIG. 5, a resist film 10 covering the end of the active region 9b in contact with the shallow trench isolation SGI of the 1.8V system region and the 3.3V system region is formed. . Here, as shown in FIG. 6, the resist film 10 has a shallow groove isolation SGI in a 1.8 V system region.
May be covered entirely, or as shown in FIG. 7, the resist film 10 has a thickness of 1.8V.
Of the ends of the active region 9b in contact with the shallow trench isolation SGI in the system region, only the region where the gate electrode is formed in a later step may be covered.

Next, as shown in FIG. 8, using the resist film 10 as a mask, the silicon oxide film 8 is etched with an aqueous solution containing HF. As a result, the active region 9a of the 3.3V region and the end of the active region 9b in contact with the shallow trench isolation SGI of the 1.8V region are about 8 nm thick.
The silicon oxide film 8 having a thickness of about a half is left.

Next, after removing the resist film 10, the semiconductor substrate 2 is subjected to a thermal oxidation treatment as shown in FIG.
A first silicon oxide film 1a is formed on the surface of the active region 9a in the 3.3V region and on the end surface of the active region 9b in the 1.8V region. A second silicon oxide film 1b having a thickness of about 4 nm is formed on the surface excluding the end. The thickness of the first silicon oxide film 1a is about 8 n because a part of the silicon oxide film 8 is shaved by the removal of the resist film 10 and the cleaning before the thermal oxidation treatment.
m.

As shown in FIG. 10, in the active region 9b in the 1.8 V system region, the first silicon oxide film 1a having a large thickness is formed.
And a thin second silicon oxide film 1b are formed, but the threshold voltage of the region where the first silicon oxide film 1a is formed is the same as the threshold voltage of the region where the second silicon oxide film 1b is formed. Is higher than the threshold voltage of
ET does not work.

Next, as shown in FIG.
A polycrystalline silicon film doped with an n-type impurity such as P is deposited thereon by a CVD (Chemical Vapor Deposition) method, and then the polycrystalline silicon film is etched using a photoresist film as a mask. A gate electrode 11 composed of a film is formed.

Next, as shown in FIG.
1 is used as a mask, and n-type impurities (for example,
P) is introduced to form a low-concentration n ⁻ -type semiconductor region 12 that forms part of the source and drain of the n-channel MISFET Qn. Similarly, a p-type impurity (for example, BF ₂ ) is introduced into the n-type well 6 using the gate electrode 11 as a mask, and a low-concentration p ⁻ -type semiconductor region forming part of the source and drain of the p-channel MISFET Qp. 13 is formed.

Next, the silicon oxide film deposited on the semiconductor substrate 2 by CVD is subjected to RIE (Reactive Ion Etching).
The sidewall spacers 14 are formed on the side walls of the gate electrode 11 by etching.

Next, an n-type impurity (for example, arsenic (As)) is introduced into the p-type well 5 by using the gate electrode 11 and the sidewall spacers 14 as a mask, and the other source and drain of the n-channel MISFET Qn are introduced. A high-concentration n ⁺ -type semiconductor region 15 constituting a part is formed. Similarly, the gate electrode 11 and the sidewall spacer 14
Is used as a mask, p-type impurities (for example,
BF ₂ ) is introduced to form a high-concentration p ⁺ -type semiconductor region 16 that forms another part of the source and drain of the p-channel MISFET Qp.

Next, a low-resistance titanium silicide film 17 is formed by the self-alignment method on the surface of the gate electrode 11 of the n-channel MISFET Qn and the surface of the n ⁺ type semiconductor region 15 and the surface of the gate electrode 11 of the p-channel MISFET Qp. It is formed on the surface of the p ⁺ type semiconductor region 16.

Thereafter, as shown in FIG. 13, after an interlayer insulating film 18 is formed on the semiconductor substrate 2, the interlayer insulating film 18 is etched to form a contact hole 19, and then deposited on the interlayer insulating film 18. By etching the metal film (not shown) thus formed to form the wiring layer 20, the CMOS logic LSI shown in FIG. 1 is completed.

As described above, according to the present embodiment, 1.8 is achieved.
The depth of the silicon oxide film 4 that can be removed at the end of the shallow trench isolation SGI in the V-based region is about 10 nm or less, which is the same as the 3.3 V-based region. On the surface of the semiconductor substrate 2,
About 10n for controlling the threshold voltage of the MISFET
The threshold voltage control layer 7 having a depth of about m is formed, but the threshold voltage control layer 7 is not formed in both the 1.8 V system region and the 3.3 V system region. The side wall is not extremely exposed. For this reason, the electric field concentrated on the edge of the semiconductor substrate 2 is reduced in the 1.8 V system region,
The characteristic of the parasitic MIEFET formed on the side wall of the semiconductor substrate 2 in the 1.8 V system region is equivalent to the characteristic of the parasitic MIEFET formed on the side wall of the semiconductor substrate 2 in the 3.3 V system region. And the MISF formed in the 1.8 V system region
The I _ds -V _g characteristics of ET, kink characteristics to cause leakage current failure of the MISFET is less likely to appear. Also,
Since the thin second silicon oxide film 1b having a thickness of about 4 nm does not cover the end portion of the semiconductor substrate 2 where the electric field is concentrated, a withstand voltage failure of the second silicon oxide film 1b hardly occurs.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the case where the present invention is applied to an element isolation region constituted by shallow groove isolation has been described. However, the present invention can be applied to other isolations such as LOCOS isolation or deep groove isolation. Effects can be obtained.

In the above embodiment, the case where the present invention is applied to a CMOS logic LSI has been described.
DRAM or CMOS logic LSI with DRAM
The same effect can be obtained.

[0038]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, in a semiconductor integrated circuit device having a MISFET composed of a thin gate insulating film and a MISFET composed of a thick gate insulating film, the MIS having a thin gate insulating film is provided.
Leakage current failure of the FET or deterioration of the withstand voltage of the gate insulating film is less likely to occur, and the reliability of the MISFET constituted by the thin gate insulating film can be improved.

[Brief description of the drawings]

FIG. 1 shows a CMOS logic LS according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate showing a MISFET of I in a direction parallel to a gate electrode.

FIG. 2 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction parallel to the gate electrode, illustrating the method of manufacturing the MISFET of I;

FIG. 3 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction parallel to the gate electrode, illustrating the method of manufacturing the MISFET of I;

FIG. 4 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction parallel to the gate electrode, illustrating the method of manufacturing the MISFET of I;

FIG. 5 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction parallel to the gate electrode, illustrating the method of manufacturing the MISFET of I;

FIG. 6 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a plan view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a MISFET of I.

FIG. 7 shows a CMOS logic LS according to an embodiment of the present invention;
FIG. 9 is a plan view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a MISFET of I.

FIG. 8 shows a CMOS logic LS according to an embodiment of the present invention.
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction parallel to the gate electrode, illustrating the method of manufacturing the MISFET of I;

FIG. 9 is a diagram illustrating a CMOS logic LS according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction parallel to the gate electrode, illustrating the method of manufacturing the MISFET of I;

FIG. 10 shows a part of FIG. 9 (in contact with shallow groove isolation);
FIG. 3 is an enlarged cross-sectional view of an end of an active region in a 1.8 V system region.

FIG. 11 shows a CMOS logic L according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction parallel to a gate electrode, illustrating a method of manufacturing an SI MISFET.

FIG. 12 shows a CMOS logic L according to an embodiment of the present invention.
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction perpendicular to a gate electrode, illustrating a method of manufacturing an SI MISFET.

FIG. 13 shows a CMOS logic L according to an embodiment of the present invention;
FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate in a direction perpendicular to a gate electrode, illustrating a method of manufacturing an SI MISFET.

FIG. 14: 1.8 V in contact with conventional shallow groove isolation
FIG. 3 is an enlarged cross-sectional view of an end of an active region in a system region.

[Explanation of symbols]

1a first silicon oxide film 1b second silicon oxide film 2 semiconductor substrate 3 shallow groove 4 silicon oxide film 5 p-type well 6 n-type well 7 threshold voltage control layer 8 silicon oxide film 9a active region 9b active region 10 Resist film 11 gate electrode 12 n ^- type semiconductor region 13 p ^- type semiconductor region 14 sidewall spacer 15 n ⁺ type semiconductor region 16 p ⁺ type semiconductor region 17 titanium silicide film 18 interlayer insulating film 19 contact hole 20 wiring layer 21 semiconductor substrate Reference Signs List 22 threshold voltage control layer 23 element isolation region 24 field insulating film 25 thin gate insulating film SGI shallow trench isolation Qn n-channel MISFET Qp p-channel MISFET

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F040 DA19 DB03 DC01 EC07 EC13 ED01 ED09 EF02 EK01 EK05 FA02 FB05 5F048 AA07 AB01 AC03 AC06 BA01 BB05 BB08 BB16 BC06 BC18 BD04 BE03 BG12 BG16 DA25

Claims (5)

[Claims] A gate insulating film of the MISFET;
A first insulating film provided at an end of the active region in which the ISFET is formed and a second insulating film provided at an end other than the end of the active region;
Wherein the thickness of the first insulating film is relatively thicker than the thickness of the second insulating film. 2. A semiconductor integrated circuit device having a first MISFET constituted by a first gate insulating film and a second MISFET constituted by a second gate insulating film, wherein the first gate comprises a first gate insulating film. The insulating film is formed of the first M
A first insulating film provided at an end of the first active region in which the ISFET is formed, and a second insulating film provided at a position other than the end of the first active region; The film thickness of the first insulating film is relatively thicker than the film thickness of the second insulating film, and the third insulating film constituting the second gate insulating film is formed.
A semiconductor integrated circuit device having the same thickness as the insulating film. 3. The semiconductor integrated circuit device according to claim 2, wherein said first insulating film forming said first gate insulating film and said third insulating film forming said second gate insulating film. Is a film formed in the same manufacturing process. 4. A step of forming an element isolation region and an active region on a semiconductor substrate, and (b) a step of performing a heat treatment on the semiconductor substrate to form an insulating film on a surface of the active region. And (c) at least the MISF in the periphery of the active region.
A step of covering a region where a gate electrode constituting ET is formed with a resist film, and (d) using the resist film as a mask,
Removing the exposed insulating film; and (e) performing a heat treatment on the semiconductor substrate after removing the resist film, thereby forming a first insulating film on the active region where the insulating film remains. Forming a film and forming a second insulating film in the active region where the insulating film does not remain. 5. An element isolation region on a semiconductor substrate, comprising:
Active region and second active region in which
Forming a second active region in which the MISFET is formed; and (b) performing a heat treatment on the semiconductor substrate to form an insulating film on the surfaces of the first active region and the second active region. (C) covering at least a region around the first active region where a gate electrode constituting the first MISFET is formed and the second active region with a resist film; d) using the resist film as a mask, removing the exposed insulating film; and (e) performing a heat treatment on the semiconductor substrate after removing the resist film so that the insulating film remains. Forming a first insulating film in the first active region, and forming a second insulating film in the first active region where the insulating film does not remain;
Forming a third insulating film in the active region according to (1).