JP2000150463A - Method for etching organic interlayer insulating film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To etch an organic interlayer insulating film at a large selection ratio against a resist even when the insulating layer has a high-aspect ratio, by forming a photoresist pattern in such a way that an inorganic film is formed on the insulating film and the insulating film is etched by using the etched inorganic film as a mask, and then, the inorganic film is removed. SOLUTION: After an etching stopper layer 102, an interlayer insulating film 103, and an inorganic film 104 are formed on an FET element area 101, a photoresist 105 for forming via hole is applied to the surface of the inorganic film 104, and a hole section 106 is formed by patterning the photoresist 105 and etching the films 104 and 103 by using the patterned photoresist 105 as a mask. Then a plug is formed. After a second etching stopper layer 108, a second interlayer insulating film 109, and a second inorganic film 110 are formed on the first interlayer insulating film 103 thereafter, a wiring groove section 112 is formed by applying a photoresist for forming wiring groove to the surface of the second inorganic film 110 and patterning the photoresist. Moreover, wiring is formed by etching the second etching stopper layer 108 and forming a metal 113 for wiring, and then, removing the metal 113 except that in the groove section 112.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for etching an organic interlayer insulating film. More specifically, the present invention provides
The present invention relates to an etching method capable of forming a wiring groove or a via hole at a nearly vertical angle even if the etching selectivity of a low dielectric constant organic interlayer insulating film used for increasing the communication speed to a photoresist is low.

[0002]

2. Description of the Related Art As semiconductor elements such as ULSIs become more highly integrated, wirings are becoming finer and multilayered. for that reason,
The planarization of the interlayer insulating film and the formation of fine wiring are important, and as one of the means for solving these problems, an embedded wiring technique called a damascene method is receiving attention.

In this buried wiring technique, a groove of a wiring pattern is formed in an interlayer insulating film, and the inside of the wiring groove is buried with a wiring material. Then, the wiring material other than the inside of the wiring groove is subjected to chemical mechanical polishing (CMP). ： Chemical Mechanical Polishing)
The wiring material is removed only in the wiring groove by removing it by a method or the like. Also, a via-hole buried plug can be formed using a similar method. Further, a method of continuously forming the embedded wiring and the embedded plug is called a dual damascene method.

According to the buried wiring technique, since the wiring portion is formed in a shape buried in the interlayer insulating film, it is extremely advantageous for flattening the interlayer insulating film thereafter. Also,
Conventional reactive ion etching (RIE)
It becomes possible to use copper (Cu) wiring, which has been difficult to process by the etching method. This Cu wiring has attracted the most attention as a next-generation wiring material because of its low resistance and high reliability.

At the time of forming the groove for the buried wiring,
In order to easily perform the etching control, usually, an etching stopper layer is provided in the interlayer insulating film. For example,
In the case of a conventional silicon oxide-based interlayer insulating film, a silicon nitride film is used as an etching stopper layer. However, silicon nitride has a high relative dielectric constant of about 7, so that
When the silicon nitride film is provided in the interlayer insulating film, there is a problem that the relative dielectric constant of the entire interlayer insulating film increases.

On the other hand, with the above-mentioned high integration of semiconductor elements, the wiring intervals have been reduced. However, a reduction in the wiring interval leads to an increase in the capacitance between wirings, which leads to a deterioration in the operation speed of the semiconductor element and an increase in power consumption. In particular, in a logic-based semiconductor element, the deterioration of the operation speed is a very serious problem.

Therefore, the use of an insulating film having a dielectric constant lower than that of a silicon oxide (relative dielectric constant: 4.2) based insulating film generally used in the past has been studied. For example, when the design rule is smaller than 0.18 μm, the relative dielectric constant of the interlayer insulating film needs to be about 2.5 or less.

Further, when the distance between the wirings is reduced, it becomes necessary to accurately form a via hole for making an upper layer wiring contact the wirings. That is, when the formation position of the via hole is slightly displaced from the lower wiring, the insulating film between the lower wirings is also etched in the etching step of forming the via hole, and when the via hole is buried later, the upper wiring is also formed in that portion. Material enters. As a result, the interval between the lower wirings is further reduced due to the upper wiring material that has entered between them, and the capacitance between the wirings unexpectedly increases, and in the worst case, there is a problem that the wirings are short-circuited. .

However, the resolution of the exposure apparatus in the photolithography process is limited, and it is technically unavoidable that the formation position of the via hole is slightly shifted. In particular,
In recent semiconductor devices that have been miniaturized and highly integrated, it has become difficult to make the wiring width at the contact part larger than other parts, and the wiring width at the contact part is the same as other parts, so-called borderless. It is a contact. As a result, the width of the lower wiring at the contact portion is inevitably substantially equal to the diameter of the via hole formed thereon, and the above-described problem of the positional deviation of the via hole is intensified.

In order to suppress an increase in inter-wiring capacitance even when the buried wiring interval becomes narrow due to a displacement or the like, a main portion of an interlayer insulating film or an etching stopper layer is provided.
Use of an organic low dielectric constant material having a lower dielectric constant than silicon oxide or silicon nitride has been studied.

When an organic low dielectric constant material is used only for the etching stopper layer, for example, polyaryl ether, polyxylene, polyimide, polynaphthalene, etc. can be used as an etching stopper layer below the interlayer insulating film made of silicon oxide. .

In the case where an organic low dielectric constant material is used for both the main part of the interlayer insulating film and the etching stopper layer,
The main part of the interlayer insulating film includes, for example, a copolymer of cycloperfluorohexane and siloxane, polypentafluorostyrene, modified polytetrafluoroethylene, polyfluoromethylbenzene, fluorinated polyarylether, fluorinated polyimide, For example, polyaryl ether, polyxylene, polyimide, polynaphthalene, or the like can be used for the etching stopper layer.

FIGS. 5 to 8 show a process of forming a multi-layer wiring in a case where an organic low dielectric constant material is used for both a main part of an interlayer insulating film and an etching stopper layer. 9 in the figure
01 is a base element region, 902 is a first etching stopper layer, 903 is a main portion of a first interlayer insulating film, 905 is a photoresist for forming a via hole, 906 is a hole portion, 90
Reference numeral 7 denotes a metal for a plug, 908 denotes a second etching stopper layer, 909 denotes a main part of the second interlayer insulating film, 911 denotes a photoresist for forming a groove, 912 denotes a wiring groove, and 913 denotes a wiring metal. The formation process is performed as follows. As shown in FIG. 5, first, (i) a first etching stopper layer 902 and a first main part 903 of an interlayer insulating film are sequentially formed on a base element region 901. Next, (ii) a via hole forming photoresist 905 is applied and pre-baked.
Patterning is performed by exposure-development-rinse-post-bake. (Iii) The first interlayer insulating film main portion 903 is etched by using the via hole forming photoresist 905 as a mask to form a hole portion 906. Further, as shown in FIG. 6, (iv) first etching stopper layer 90
2 is etched. (V) A plug metal 907 is formed. (Vi) The plug metal 907 other than the hole 906 is removed by CMP or the like to form a plug. Next, as shown in FIG. 7, (vii) a second etching stopper layer 908 and a second main portion 909 of an interlayer insulating film are formed in this order. (viii) A photoresist 911 for forming wiring grooves is applied and patterned by pre-bake-exposure-development-rinse-post-bake. (ix) Second main portion 909 of interlayer insulating film using photoresist 911 for forming wiring groove as a mask
Is etched to form a wiring groove 912. Further, as shown in FIG. 8, (x) the second etching stopper layer 908 is etched. (Xi) A wiring metal 913 is formed. (Xii) The wiring metal 913 other than the wiring groove 912 is removed by CMP or the like to form a wiring.

For example, the etching stopper layers 902, 9
Substrate temperature: 25 using polyaryl ether as 08, using a copolymer of cycloperfluorocarbon polymer and siloxane as main parts of interlayer insulating films 903 and 909, and using a magnetron RIE (Reactie Ion Etching) apparatus as an etching apparatus. ° C gas: C ₄ F ₈ / CO / Ar / O ₂ (2
When the main portions 903 and 909 of the interlayer insulating film are etched under the conditions of pressure: 20 mTorr and RF power: 2 kW, the etching rate ratio to the etching stopper layers 902 and 908, that is, the selectivity is about 5. The hole 906 and the wiring groove 912 can be formed.

[0015]

SUMMARY OF THE INVENTION However, FIGS.
When the etching treatment of the organic interlayer insulating film as shown in FIG. 8 is performed, the selectivity with the photoresist cannot be increased, and
There is a problem that it is difficult to form holes having a high aspect ratio.

A main object of the present invention is to solve the above-mentioned problems in the conventional method of etching an organic interlayer insulating film, to increase the etching selectivity, and to favorably form even a shape having a high aspect ratio. It is to provide an etching method.

[0017]

Means for Solving the Problems The present inventor has solved the above-mentioned problems in the conventional method for etching an organic interlayer insulating film and has made intensive efforts to achieve the above object, and as a result, has reached the present invention. That is, the present invention provides a step of forming an inorganic film on an organic interlayer insulating film, a step of forming a photoresist pattern on the inorganic film, and a step of etching the inorganic film using the photoresist pattern as a mask. ,
A method of etching an organic interlayer insulating film, comprising: a step of etching the organic interlayer insulating film using the etched inorganic film as a mask; and a step of removing the inorganic film.

By using the present invention, it is possible to increase the etching selectivity with respect to the mask, and to provide an etching method capable of forming a shape having a high aspect ratio.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for etching an organic interlayer insulating film according to the present invention will be described with reference to FIGS. 101 is a base element region, 102 is a first etching stopper layer, 10
3 is a main part of the first interlayer insulating film, 104 is a first inorganic film,
Reference numeral 105 denotes a photoresist for forming a via hole, 106 denotes a hole, 107 denotes a metal for a plug, 108 denotes a second etching stopper layer, 109 denotes a main part of a second interlayer insulating film,
110 is a second inorganic film, 111 is a photoresist for forming a groove, 112 is a wiring groove, and 113 is a metal for wiring.

The forming process is as follows. As shown in FIG. 1, first, (i) a first etching stopper layer 102 and a first main portion 103 of an interlayer insulating film are sequentially formed on an FET element region 101. Next, (ii) after forming the first inorganic film 104, a photoresist 105 for forming a via hole is applied and patterned by pre-bake-exposure-development-rinse-post-bake. (Iii) The hole portion 106 is formed by etching the first inorganic film 104 and the first interlayer insulating film main portion 103 sequentially using the photoresist 105 for via hole formation as a mask. Further, as shown in FIG. 2, (iv) the first etching stopper layer 102 is etched. (V) Plug metal 107
Is formed. (Vi) The plug metal 107 other than the hole 106 is removed by CMP or etch-back method to form a plug. Next, as shown in FIG. 3, (vii) a second etching stopper layer 108 and a second main portion 109 of the interlayer insulating film are sequentially formed. (viii) Second inorganic film 110
Is formed, and a photoresist 111 for forming a wiring groove is applied, and patterned by pre-bake-exposure-development-rinse-bost bake. (Ix) The wiring groove 112 is formed by sequentially etching the second inorganic film 110 and the second main part 109 of the second interlayer insulating film using the wiring groove forming photoresist 111 as a mask. Further, as shown in FIG. 4, (x) the second etching stopper layer 108 is etched. (Xi) The wiring metal 113 is formed. (Xi
i) The wiring groove 112 is formed by CMP or an etch back method.
The wiring metal 113 other than that is removed to form a wiring.

More specifically, for example, Al—Si films as the inorganic films 104 and 110, the etching stopper layers 102 and
8 as polyaryl ether, main part of interlayer insulating film 10
Using a copolymer of cycloperfluorocarbon polymer and siloxane as 109 and using a magnetron RIE device as an etching device, substrate temperature: 25 ° C. gas: C ₄ F ₈ / CO / Ar / O ₂ (2
0/200/300/10 sccm) Pressure: 20 mTorr RF power: 2 kW When etching the main parts 103 and 109 of the interlayer insulating film, the etching rate ratio with respect to the inorganic films 104 and 110, that is, the selection ratio becomes 10 V or more. As a result, it is possible to form good via holes 106 and wiring grooves 112.

The inorganic film used in the method for etching an organic interlayer insulating film of the present invention includes Al, Ti, V,
Metal films containing at least one selected from the group consisting of Cr, Ni, Mo, Ta, W, Au, Pt, or alloy films thereof, and amorphous films containing at least one of Si and C as main components Any film such as a film, a polycrystal film or a single crystal film, an oxide film of Si, Al, Ta, Ti, and Cr, a nitride film, or a carbide film can be used as long as the etching selectivity of the organic interlayer insulating film can be made large. is there. Specifically, pure Al, AlSi, AlCu, AlS
iCu, AlO, AlC, pure Ti, TiN, TiSi,
TiW, TiO, TiC, pure Ta, TaN, TaSi,
TaW, TaO, TaC, pure Cr, AlCr, CrS
i, CrO, CrC, pure Ni, AlNi, NiCr, N
iSi, pure Mo, MoSi, MoW, pure W, WSi, W
N, pure Pt, PtSi, a-Si, poly-Si, a
-SiC, poly-SiC, aC, poly-C SiO, SiN, SiCON, SiON and the like. These compositions may or may not satisfy the stoichiometric ratio.

As the photoresist used in the method for etching an organic interlayer insulating film of the present invention, generally used novolak-based resist, cyclized rubber-based resist, methacrylate-based resist, styrene-based resist,
An imide-based resist, a chemically amplified resist, a fullerene-dispersed resist, or the like can be applied as long as the etching selectivity of the inorganic film can be increased.

As the organic interlayer insulating film used in the method for etching an organic interlayer insulating film of the present invention, an organic ether polymer such as polyaryl ether or a fluorinated product thereof, an aromatic compound polymer such as polystyrene, polyxylene, polynaphthalene or the like. The fluorinated product, polyethylene, polypropene, aliphatic compound polymer such as polybutylene or fluorinated product thereof, polycyclobutene, alicyclic compound polymer such as polycyclopentene or fluorinated product thereof, polyimide compound or fluorinated product thereof,
Polysilicon compounds or their fluorinated products, alkoxysilane compound polymers or their fluorinated products, fullerene-dispersed polymers or their fluorinated products, etc., can be used as long as their relative dielectric constant is 2.5 or less, more preferably 2.0 or less It is.

An etching apparatus used in the method for etching an organic interlayer insulating film of the present invention is a generally used parallel plate type (CCP: Capacitively Coupled Plasm).
a), magnetron RIE type (Reactive Ion Etching),
Inductively coupled plasma (ICP),
Electron cyclotron resonance type (ECR: Electron Cyclotr)
on Resonance), Helicon Wave type (HWP: Helicon Wave)
Plasma), surface wave type (SWP: Surface-Wave Plasm)
a), surface wave interference type (SIP: Surface-Wave-Interfered)
Plasma) is also applicable.

The edge used in the etching method of the present invention is
As the gas for chining, F_Two , CF _Four , CH_Two F_Two , C
_Two F₆ , C_Four F₈ , CF_Two Cl_Two . SF₆ , NF_Three , C
l_Two, CCl_Four , CH_Two Cl_Two , C_Two Cl₆ , BCl
_Three , HBr, O_Two , O_Three , H_TwoO, H_Two , NO, N_Two 
O, NO_Two , CO_Two , CO, Ar, He, Ne, Xe,
A single gas such as Kr or a mixture of
Combined gas is applicable.

In particular, the gas used for etching the inorganic film preferably contains a halogen atom, and the gas used for the organic interlayer insulating film preferably contains an oxygen or hydrogen atom.

In the method of etching an organic interlayer insulating film according to the present invention, the pressure in the reactor at the time of performing the etching is set to 0.1.
It can be selected from the range of 1 mTorr to 1 Torr, more preferably the range of 2 mTorr to 50 mTorr.

[0029]

EXAMPLES Hereinafter, the method for etching an organic interlayer insulating film of the present invention will be described more specifically with reference to examples, but the present invention is not limited to these examples.

Embodiment 1 A method for etching an organic interlayer insulating film of the present invention using an Al film as an inorganic film will be described with reference to FIGS.

In the figure, 101 is a base MOS-FET element region, 102 is a polyaryl ether as a first etching stopper layer, 103 is a cycloperfluorocarbon polymer-siloxane copolymer as a first interlayer insulating film, and 104 is Al film which is a first inorganic film, 105 is a via hole forming photoresist, 106 is a via hole portion,
107 is Cu for a plug, 108 is a polyaryl ether as a second etching stopper layer, 109 is a cycloperfluorocarbon polymer-siloxane copolymer as a second interlayer insulating film, and 110 is Al as a second inorganic film.
A film, 111 is a photoresist for forming a groove, 112 is a wiring groove, and 113 is Cu for wiring.

The forming process is as follows. First,
(I) First etching stopper layer 102 and first interlayer insulating film 103 on base MOS-FET element region 101
Are sequentially formed by a coating method. Next, (ii) a via hole forming photoresist 105 is applied after forming the first inorganic film 104 by a sputtering method, and is patterned by pre-bake-exposure-development-rinse-post-bake. (Iii) Via hole forming photoresist 105
Is used as a mask to form a first inorganic film 104 under the following conditions: etching apparatus: ECR etcher substrate temperature: 25 ° C. gas: BCl ₃ (100 sccm) pressure: 30 mTorr MW power: 1.5 kW RF power: 0.3 kW One interlayer insulating film 103 is etched using an etching device: magnetron RIE, a substrate temperature: 25 ° C., a gas: C ₄ F ₈ / CO / Ar / O ₂ (1
0/80/150/20 sccm) Pressure: 20 mTorr RF power: 1.5 kW The via hole 106 is formed by etching in order.

Further, as shown in FIG. 2, (iv) the first etching stopper layer 102 is formed by using an etching apparatus: ICP plasma etcher substrate temperature: 25 ° C. gas: O ₂ (150 sccm) pressure: 30 mTorr RF power: 2.0 kW Etching is performed under the condition of bias power: 0.2 kW. At this time, the via hole forming photoresist 105 shown in FIG. 1 is also ashed and removed by oxygen plasma. (V) Metal for plug 10
7 is formed by a plating method. (Vi) The plug metal 107 other than the via hole 106 is removed by CMP to form a plug.

Next, as shown in FIG. 3, (vii) a second etching stopper layer 108 and a second interlayer insulating film 109 are sequentially formed by a coating method. (Viii) Second inorganic film 110
Is formed by a sputtering method, and a photoresist 111 for forming a wiring groove is applied, and is patterned by prebaking-exposure-developing-rinsing-postbaking. (I
x) Using the photoresist 111 for forming the wiring groove as a mask, the second inorganic film 110 is etched using an etching apparatus: ECR etcher Substrate temperature: 25 ° C. Gas: BCl ₃ (100 sccm) Pressure: ₃ mTorr MW power: 1.5 kW RF power: Under the condition of 0.3 kW, the first interlayer insulating film 109 is further etched by an etching apparatus: magnetron RIE, a substrate temperature: 25 ° C., a gas: C ₄ F ₈ / CO / Ar / O ₂ (1
0/80/150/20 sccm) Pressure: 20 mTorr RF power: 1.5 kW Under the condition of etching, the wiring groove portion 11 is etched in order.
Form 2

Further, as shown in FIG. 4, (x) the second etching stopper layer 108 is formed by etching the following: an etching apparatus: ICP plasma etcher substrate temperature: 25 ° C. gas: O ₂ (150 sccm) pressure: 30 mTorr RF power: 2.0 kW Etching is performed under the condition of bias power: 0.2 kW. At this time, the wiring forming photoresist 111 shown in FIG. 3 is also ashed and removed by oxygen plasma. (Xi) The wiring metal 113 is formed by plating. (Xii) By CMP, the wiring groove 1
The wiring metal 113 other than 12 is removed to form a wiring.

The selectivity of the organic interlayer insulating film to the inorganic film was 14, and finally a buried wiring and a buried via hole having a good shape were formed.

Embodiment 2 A method for etching an organic interlayer insulating film of the present invention using an a-Si film as an inorganic film will be described with reference to FIGS.

In the drawing, 101 is a base MOS-FET element region, 102 is a polyaryl ether as a first etching stopper layer, 103 is a cycloperfluorocarbon polymer-siloxane copolymer as a first interlayer insulating film, and 104 is A-Si film which is a first inorganic film, 105 is a photoresist for forming a via hole, 106 is a via hole, 107 is Cu for a plug, 108 is a polyaryl ether which is a second etching stopper layer, and 109 is a second A cycloperfluorocarbon polymer-siloxane copolymer as an interlayer insulating film, 110 is a second inorganic film a
-Si film, 111 is a photoresist for forming a groove, 112 is a wiring groove, and 113 is Cu for wiring. The formation process is as follows. First, (i) a first etching stopper layer 102 is formed on a base MOS-FET element region 101;
The first interlayer insulating film 103 is sequentially formed by a coating method. Next, (ii) a first inorganic film 104 is formed by a sputtering method, and a photoresist 1 for forming a via hole is formed.
05 is applied and patterned by pre-bake-exposure-develop-rinse-post-bake. (Iii) The first inorganic film 104 is etched using the via hole forming photoresist 105 as a mask. Etching apparatus: magnetron RIE Substrate temperature: 25 ° C. Gas: Cl ₂ (100 sccm) Pressure: 30 mTorr RF power: 2.0 kW RF power: Under the condition of 0.3 kW, the first interlayer insulating film 103 is further etched by an etching apparatus: magnetron RIE, a substrate temperature: 25 ° C., a gas: C ₄ F ₈ / CO / Ar / O ₂ (1
0/80/150/20 sccm) Pressure: 20 mTorr RF power: 1.5 kW The via hole 106 is formed by etching in order.

Further, as shown in FIG. 2, (iv) the first etching stopper layer 102 is formed by etching an etching apparatus: ICP plasma etcher substrate temperature: 25 ° C. gas: O ₂ (150 sccm) pressure: 30 mTorr MW power: 2.0 kW Etching is performed under the condition of RF power: 0.2 kW. At this time, the via hole forming photoresist 105 shown in FIG. 1 is also ashed and removed by oxygen plasma. (V) Metal for plug 10
7 is formed by a plating method. (Vi) The plug metal 107 other than the via hole 106 is removed by CMP to form a plug.

Next, as shown in FIG. 3, (vii) a second etching stopper layer 108 and a second interlayer insulating film 109 are sequentially formed by a coating method. (Viii) Second inorganic film 110
Is formed by a sputtering method, and a photoresist 111 for forming a wiring groove is applied, and is patterned by prebaking-exposure-developing-rinsing-postbaking. (I
x) The second inorganic film 110 is etched using the wiring groove forming photoresist 111 as a mask. Etching apparatus: magnetron RIE Substrate temperature: 25 ° C. Gas: Cl ₂ (100 sccm) Pressure: 30 mTorr MW power: 1.5 kW RF power: Under the condition of 0.3 kW, the second interlayer insulating film 109 is further etched by an etching apparatus: magnetron RIE, a substrate temperature: 25 ° C., a gas: C ₄ F ₈ / CO / Ar / O ₂ (1
0/80/150/20 sccm) Pressure: 20 mTorr RF power: 1.5 kW Under the condition of etching, the wiring groove portion 11 is etched in order.
Form 2

Further, as shown in FIG. 4, (x) the second etching stopper layer 108 is formed by using an etching device: IC
P plasma etcher Substrate temperature: 25 ° C. Gas: O ₂ (150 sccm) Pressure: 30 mTorr RF power: 2.0 kW Bias power: 0.2 kW At this time, the wiring forming photoresist 111 shown in FIG. 3 is also ashed and removed by oxygen plasma. (Xi) The wiring metal 113 is formed by plating. (Xii) By CMP, the wiring groove 1
The wiring metal 113 other than 12 is removed to form a wiring.

The selectivity of the organic interlayer insulating film to the inorganic film was 16, and finally, a buried wiring and a buried via hole having a good shape were formed.

Embodiment 3 A method for etching an organic interlayer insulating film of the present invention using a SiN film as an inorganic film will be described with reference to FIGS.

In the figure, 101 is a base MOS-FET element region, 102 is a polyarylether as a first etching stopper layer, 103 is a cycloperfluorocarbon polymer-siloxane copolymer as a first interlayer insulating film, and 104 is SiN film as a first inorganic film; 105, a photoresist for forming a via hole; 106, a via hole; 107, Cu for a plug; 108, a polyaryl ether as a second etching stopper layer; The film is a cycloperfluorocarbon polymer-siloxane copolymer, 110 is a second inorganic film S
An iN film, 111 is a photoresist for forming a groove, 112 is a wiring groove, and 113 is Cu for wiring.

The forming process is as follows. First,
(I) First etching stopper layer 102 and first interlayer insulating film 103 on base MOS-FET element region 101
Are sequentially formed by a coating method. Next, (ii) a via hole forming photoresist 105 is applied after forming the first inorganic film 104 by a sputtering method, and is patterned by pre-bake-exposure-development-rinse-post-bake. (Iii) Via hole forming photoresist 105
Is used as a mask to etch the first inorganic film 104. Etching apparatus: magnetron RIE Substrate temperature: 25 ° C. Gas: C ₄ F ₈ / CO / Ar (50/2)
0/150 sccm) Pressure: 30 mTorr RF power: 2.0 kW, further etching the first interlayer insulating film 103, Etching apparatus: Magnetron RIE Substrate temperature: 25 ° C. Gas: C ₄ F ₈ / CO / Ar / O ₂ (1
0/80/150/20 sccm) Pressure: 20 mTorr RF power: 1.5 kW The via hole 106 is formed by etching in order.

Further, as shown in FIG. 2, (iv) the first etching stopper layer 102 is formed by etching an etching apparatus: ICP plasma etcher, a substrate temperature: 25 ° C., a gas: O ₂ (150 sccm), a pressure: 30 mTorr, and a MW power: 2.0 kW. Etching is performed under the condition of RF power: 0.2 kW. At this time, the via hole forming photoresist 105 shown in FIG. 1 is also ashed and removed by oxygen plasma. (V) Metal for plug 10
7 is formed by a plating method. (Vi) The plug metal 107 other than the via hole 106 is removed by CMP to form a plug.

Next, as shown in FIG. 3, (vii) a second etching stopper layer 108 and a second interlayer insulating film 109 are sequentially formed by a coating method. (Viii) Second inorganic film 110
Is formed by a sputtering method, and a photoresist 111 for forming a wiring groove is applied, and is patterned by prebaking-exposure-developing-rinsing-postbaking. (I
x) The second inorganic film 110 is etched using the wiring groove forming photoresist 111 as a mask. Etching apparatus: magnetron RIE Substrate temperature: 25 ° C. Gas: C ₄ F ₈ / CO / Ar (50/2)
0/150 sccm) Pressure: 30 mTorr RF power: 2.0 kW, further etching the second interlayer insulating film 109, Etching apparatus: Magnetron RIE Substrate temperature: 25 ° C. Gas: C ₄ F ₈ / CO / Ar / O ₂ (1
0/80/150/20 sccm) Pressure: 20 mTorr RF power: 1.5 kW Under the condition of etching, the wiring groove portion 11 is etched in order.
Form 2

Further, as shown in FIG. 4, (x) the second etching stopper layer 108 is formed by etching an etching apparatus: ICP plasma etcher substrate temperature: 25 ° C. gas: O ₂ (150 sccm) pressure: 30 mTorr RF power: 2.0 kW Etching is performed under the condition of bias power: 0.2 kW. At this time, the wiring forming photoresist 111 shown in FIG. 3 is also ashed and removed by oxygen plasma. (Xi) The wiring metal 113 is formed by plating. (Xii) By CMP, the wiring groove 1
The wiring metal 113 other than 12 is removed to form a wiring.

The selectivity of the organic interlayer insulating film to the inorganic film was 11, and finally a buried wiring and a buried via hole having a good shape were formed.

[0050]

As described above in detail, according to the method for etching an organic interlayer insulating film of the present invention, by performing etching through an inorganic film, a wiring groove or a via hole is formed on the insulating film. It can be formed favorably at an angle close to vertical.

[Brief description of the drawings]

FIG. 1 is a diagram showing the first three steps (i) to (iii) in a process chart for explaining an etching method of the present invention.

FIG. 2 is a view showing three steps (iv) to (vi) subsequent to FIG. 1;

FIG. 3 is a view showing three steps (vii) to (ix) subsequent to FIG. 2;

FIG. 4 is a view showing last three steps (x) to (xii) following FIG. 3;

FIG. 5 is a view showing the first three steps (i) to (iii) in a process chart for explaining a conventional etching method.

FIG. 6 is a view showing three steps (iv) to (vi) subsequent to FIG. 5;

FIG. 7 is a view showing the last three steps (vii) to (ix) subsequent to FIG.

FIG. 8 is a view showing last three steps (x) to (xii) following FIG. 7;

[Explanation of symbols]

 101, 109 Underlying element region 102, 902 First etching stopper layer 103, 903 First interlayer insulating film main portion 104 First inorganic film 105, 905 Via hole forming photoresist 106, 906 Via hole portion 107, 907 For plug Metal 108, 908 Second etching stopper layer 109, 909 Second interlayer insulating film main part 110 Second inorganic film 111, 911 Wiring groove forming photoresist 112, 912 Wiring groove 113, 913 Wiring metal

Continued on the front page F term (reference) 5F004 AA02 AA16 BA04 BA09 BA13 BA14 BA20 BB11 DA00 DA01 DA02 DA04 DA05 DA06 DA11 DA15 DA17 DA18 DA22 DA23 DA24 DA26 DA27 DA28 DB02 DB03 DB07 DB08 DB09 DB10 DB12 DB23 DB25 EA05 EA06 EA07 EA28 EB01

Claims (18)

[Claims] A step of forming an inorganic film on the organic interlayer insulating film, a step of forming a photoresist pattern on the inorganic film, and a step of etching the inorganic film using the photoresist pattern as a mask. A method of etching the organic interlayer insulating film using the etched inorganic film as a mask, and a step of removing the inorganic film. 2. The etching method according to claim 1, wherein the organic interlayer insulating film is an organic ether polymer or a fluoride thereof. 3. The etching method according to claim 2, wherein the organic ether polymer is a polyaryl ether. 4. The etching method according to claim 1, wherein the organic interlayer insulating film is an aromatic compound polymer or a fluoride thereof. 5. The aromatic compound polymer is polystyrene, polyxylene or polynaphthalene.
3. The etching method according to 1. 6. The etching method according to claim 1, wherein the organic interlayer insulating film is an aliphatic compound polymer or a fluoride thereof. 7. The etching method according to claim 6, wherein the aliphatic compound polymer is polyethylene, polypropene or polybutylene. 8. The etching method according to claim 1, wherein the organic interlayer insulating film is an alicyclic compound polymer or a fluorinated compound thereof. 9. The etching method according to claim 8, wherein the alicyclic compound polymer is polycyclobutene or polycyclopentene. 10. The etching method according to claim 1, wherein the organic interlayer insulating film is a polyimide compound or a fluoride thereof. 11. The etching method according to claim 1, wherein the organic interlayer insulating film is a polysiloxane compound or a fluorinated compound thereof. 12. The etching method according to claim 1, wherein the organic interlayer insulating film is an alkoxysilane compound polymer or a fluorinated product thereof. 13. The etching method according to claim 1, wherein the organic interlayer insulating film is a fullerene-dispersed polymer or a fluorinated product thereof. 14. The etching method according to claim 1, wherein the inorganic film is a metal film or an alloy film. 15. The method according to claim 15, wherein the metal film or the alloy film is made of Al, T
i, V, Cr, Ni, Mo, Ta. W, Au and Pt
The etching method according to claim 14, wherein the film is a film containing at least one member selected from the group consisting of: 16. The method according to claim 16, wherein the inorganic film is an amorphous film, a polycrystal film, or a single crystal film containing at least one of Si and C as a main component.
14. The etching method according to claim 1. 17. The method according to claim 17, wherein the inorganic film is made of Si, Al, Ta, T
14. The etching method according to claim 1, wherein the etching method is an oxide film, a nitride film, or a carbide film of i or Cr. 18. The gas used for etching the inorganic film contains a halogen atom, and the gas used for etching the organic interlayer insulating film contains oxygen or hydrogen atoms. 18. The method for etching an organic interlayer insulating film according to item 17.