JP2000149598A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce cost of a test for, and improve the reliability of, a dynamic RAM or the like which comprises a plurality of banks and an interface circuit. SOLUTION: A dynamic RAM or the like comprises a plurality of banks, main amplifiers MAU and MAL of a predetermined number for simultaneously performing a writing or readout operation of stored data for memory cells of a predetermined number in a specified bank, and an interface circuit IF for transmitting and receiving in parallel the stored data between the MAU and MAL. An ECC circuit ECC is further provided for detecting and correcting a bit error in the stored data M0-M127 of, for example, 128 bits to be transmitted and received between the main amplifiers MAU and MAL, and the interface circuit IF. Test output signals TD, each being of 1 bit and indicating that syndromes S0-S8 of, for example, 9 bits to be generated from the ECC circuits ECC, or all of their bits, exhibit a logical value of '0', are stored in the interface circuit IF in total of, e.g. 128 bits, and are output via, e.g. 16 data input/ output terminals in a packet style of 16×8 bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic RAM having a plurality of banks and interface circuits, and a technique particularly effective for reducing test costs and improving reliability thereof. It is.

[0002]

2. Description of the Related Art A plurality of banks capable of independently selecting word lines, a predetermined number of main amplifiers capable of simultaneously writing or reading storage data to or from a predetermined number of memory cells in a designated bank; A dynamic RAM having an interface circuit for transmitting and receiving stored data in parallel with these main amplifiers
(Random access memory).

On the other hand, a bit error of stored data is detected and detected based on a linear code such as a Hamming code having a syndrome.
Correcting ECC (Error Correcting)
Code) circuit. Further, as one means for efficiently performing a functional test of a dynamic RAM or the like with a large capacity, test data is simultaneously written or read to a plurality of memory cells in a selected state, and comparison and collation are performed. There is a so-called reduction test (multi-bit test) in which results are output from a predetermined number of external terminals.

[0004]

Prior to the present invention, the inventors of the present invention have proposed a dynamic RA having a plurality of banks and interface circuits and having the above-described reduction test function.
While trying to develop M, I noticed the following problems.
That is, this dynamic RAM is, for example, shown in FIG.
As shown in the figure, 16 data input / output terminals DQA0
To DQA7 and DQB0 to DQB7, the internal read data M0 to M127 of a total of 128 bits output from a main amplifier (not shown) are once taken into shift registers SR0 to SR15 of the interface circuit IF, and then output to the output data selection circuit ODSL. By 2
Each byte, that is, 16 bits, is selected, and data input / output terminals DQA0 to DQA0 are output from data output buffers OB0 to OB15.
It is output in a predetermined packet format via DQA7 and DQB0 to DQB7.

The dynamic RAM further includes a reduction test circuit MTC for realizing a reduction test function, and the internal read data M0 to M127 stores the reduction test circuit MTC.
Are compared and collated on an 8-bit basis by the corresponding NAND gates NA0 to NA15. Output signals of NAND gates NA0 to NA15 of reduction test circuit MTC are supplied to shift register SR via corresponding transfer gates G0 to G15.
0 to SR15, respectively, and are fetched while being shifted in each shift register.
It becomes an 8-bit contraction test output signal MD0 to MD127. Then, as illustrated in FIG. 11, the data input / output terminals DQA0 to DQA are sequentially selected in units of 16 bits in synchronization with the fall and rise of the clock signal CLK.
The signal is output to an external test apparatus via A7 and DQB0 to DQB7.

However, in the above-mentioned contraction test, contraction test output signals MD0-MD output as one packet are output.
Although 127 corresponds to a total of 1024 bits, that is, 128 bytes of memory cells, the reduction rate is 128 /
It is only 1024, that is, 1/8. The reduction test by the reduction test circuit MTC includes NAND gates NA0 to N
The test data pattern is all-bit logic "0" or all-bit logic "1" in order that all 8-bit storage data input to A15 be at the same logic level.
Is restricted to either. As a result, the dynamic type R
The AM test cost cannot be sufficiently reduced, and the failure detection rate of the function test decreases due to the restriction of the test data pattern, and the reliability of the dynamic RAM decreases.

An object of the present invention is to reduce the test cost and improve the reliability of a dynamic RAM or the like having a plurality of banks and interface circuits.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a plurality of banks, a predetermined number of main amplifiers for simultaneously writing or reading storage data to or from a predetermined number of memory cells in the designated bank, and storage data are transferred between these main amplifiers in parallel. In a dynamic RAM or the like having an interface circuit, an ECC circuit for detecting and correcting a bit error of, for example, 128-bit storage data transmitted and received between the main amplifier and the interface circuit is provided, and for example, 9-bit data generated by the ECC circuit. The interface circuit accumulates, for example, 128 bits of a test output signal indicating that all of the syndromes or all the bits are logic "0", and outputs them in a packet format via a data input / output terminal.

According to the above means, the dynamic type R
The reduction rate at the time of a functional test such as AM can be increased to, for example, 1/128, and when a syndrome generated by, for example, an ECC circuit is directly output to a test device, an address having a bit error identified by an external test device is identified. It is also possible to do. Further, since the function test by the ECC circuit can be performed regardless of the logical level of the data, the restriction on the test data pattern can be resolved, and the function test can be performed with an arbitrary pattern. As a result, the test cost of the dynamic RAM and the like can be reduced, the failure detection rate of the function test can be increased, and the reliability of the dynamic RAM and the like can be improved.

[0011]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, a well-known MOSFET (Metal Oxide Semiconductor Field Effect Transistor. In this specification, a MOSFET is referred to as an insulated gate field effect transistor. Is formed on one semiconductor substrate surface such as single crystal silicon by an integrated circuit manufacturing technique.
FIG. 1 shows a block configuration of a dynamic RAM in a layout form on a semiconductor substrate surface, and the positional relationship of each block will be described with reference to the top, bottom, left, and right of the figure.

In FIG. 1, the dynamic RAM of this embodiment is not particularly limited, but includes 16 banks BA.
NK0 to BANKF (here, an additional number of more than 9 banks and the like may be indicated by alphabets. The same applies hereinafter).
And an interface circuit IF and an ECC circuit ECC provided commonly to these banks.

The interface circuit IF sends and receives a start control signal, an address signal, input data and output data, etc., to and from an external access device.
0 to BANKF and a main amplifier M described later
Transmit to AU and MAL. ECC circuit ECC
Is based on a predetermined linear code having a syndrome and the interface circuit IF and the banks BANK0 to BANK.
F, that is, 9 bits of check bits are added to p bits, ie, 128 bits of write data transmitted / received in parallel between the main amplifiers MAU and MAL, and the normality of read data including the check bits is checked and corrected. .

In this embodiment, storage data that is exchanged between an external access device and an interface circuit IF of a dynamic RAM, that is, input / output data is q
× r, that is, a packet format of 16 × 8 bits, and q is input or output during a continuous r, ie, 8 cycles via q data input / output terminals DQA0 to DQA7 and DQB0 to DQB7. Therefore, the interface circuit IF receives data input / output terminals DQA0 to DQA7 and DQA from an external access device as described later.
A total of 128 bits of write data input through QB0 to DQB7 are sequentially taken in by 16 bits, that is, 2 bytes, and the main amplifier MA is converted into 128 bits in parallel.
A data register for transmitting to the U and MAL, or simultaneously taking in read data output in 128 bits in parallel from the main amplifiers MAU and MAL, and outputting 16 bits at a time to the access device.

On the other hand, in this embodiment, the ECC circuit E
Although the linear code used in CC is not particularly limited, a so-called modified Hamming code (Modified Hamming code) is used.
ING Code), which is a so-called SEC capable of detecting and correcting a 1-bit error and detecting an error of 2 bits or more.
・ DED (Single Error Correct)
ion Double Error Detectio
n) sign. The specific configuration and operation of the interface circuit IF and the ECC circuit ECC, and the characteristics thereof will be described later in detail.

Banks BANK0 to BANKF are, as typified by banks BANK0 and BANKF, memory arrays ARYU0 and ARYL0 to ARYUF to ARYUF and ARYLF, which are vertically paired, and sense elements disposed at both ends or in the middle of these memory arrays. Amplifiers SAU0 and SAL0 to SAUG and SALG, respectively. The dynamic RAM is of a so-called "depending" type and has sense amplifiers SAU1 except for two at both ends.
To SAUF and SAL1 to SALF are shared by a pair of memory arrays arranged on both sides thereof.

A pair of column address decoders CDU and CDL are provided at the left ends of the banks BANK0 to BANKF, and a pair of row address decoders RDU and RDL are provided at the center in the vertical direction. Among them, the column address decoders CDU and CDL decode a predetermined bit Y address signal supplied from the interface circuit IF when the dynamic RAM is in a column cycle, and supply the sense amplifiers SAU0 to SAUG and SAL0 to SALG. The corresponding bit of the bit line selection signal is alternatively set to an effective level. The row address decoders RDU and RDL decode a predetermined bit of the X address signal supplied from the interface circuit IF when the dynamic RAM is in a row cycle, so that the memory arrays ARYU0 to ARYUF.
In addition, the word lines corresponding to ARYL0 to ARYLF are alternatively set to the selected level.

In this embodiment, the memory arrays ARYU0 to ARYUF and ARYL0 to ARYL are used.
The word lines constituting F are hierarchized as main word lines and sub-word lines, and
YUF and ARYL0 to ARYLF are also divided and arranged corresponding to each sub-word line. The row address decoders RDU and RDL are connected to the banks BANK0 to BANK.
KF, each divided into 16
0 to BANKF can independently perform a word line selecting operation. Further, the row address decoders RDU and RDL decode the row bank address signal or the column bank address signal supplied from the interface circuit IF, and decode the corresponding banks BANK0 to BANK0.
It includes a row bank address decoder and a column bank address decoder (not shown) for selectively activating BANKF.

Next, the main amplifiers MAU and MAL are:
It includes a total of 137 unit main amplifiers provided corresponding to the 128-bit storage data and the 9 check bits, and each of these unit main amplifiers includes one write amplifier and one read amplifier. Of these, the write amplifier of each unit main amplifier is connected to an interface circuit IF and ECC from an external access device.
After the write data or check bit input through the circuit ECC or generated by the ECC circuit ECC is converted into a predetermined complementary write signal, the data is simultaneously written to a total of 137 memory cells in the selected state of the designated bank. The read amplifier of each unit main amplifier amplifies read signals output from a total of 137 memory cells in the selected state of the designated bank, and then transmits the amplified read signals to the interface circuit IF via the ECC circuit ECC. These read data are, as described above, 16 ×
It is output to an external access device in the form of an 8-bit packet.

The nine check bits output from the read amplifiers of the corresponding nine unit main amplifiers of the main amplifiers MAU and MAL are normally used for detecting and correcting bit errors by the ECC circuit ECC.
The dynamic RAM of this embodiment also has a function of outputting these check bits as they are as part of the test data to an external test apparatus in a predetermined test mode. The dynamic RAM according to the present embodiment has a function of outputting a 9-bit syndrome generated in the process of detecting and correcting a bit error of the ECC circuit ECC or processing information thereof to a test apparatus in another predetermined test mode. , Which will be described later in detail. Further, each of the unit main amplifiers of the main amplifiers MAU and MAL includes one write amplifier and one read amplifier as described above. However, in the following description, description will be made focusing only on the read operation using the read amplifier. .

FIG. 2 is a block diagram showing one embodiment of the ECC circuit ECC included in the dynamic RAM of FIG. 1. FIG. 3 is a block diagram of one of the syndrome trees ST included in the ECC circuit ECC of FIG. A partial circuit diagram of the embodiment is shown. 4 and 5 show logical condition diagrams of an embodiment of the syndrome decoder SD included in the ECC circuit ECC of FIG. 2, and FIG. 6 is a partial circuit diagram of the embodiment. It is shown. Furthermore, FIG.
Test circuit T included in the ECC circuit ECC
A circuit diagram of one embodiment of C is shown. Based on these figures, E included in the dynamic RAM of this embodiment is
The specific configuration and operation of the CC circuit ECC will be described. In FIGS. 2 and 3, a symbol “+” inside the symbol indicates a so-called exclusive OR (Exclusive).
OR) circuit.

In FIG. 2, the ECC circuit ECC includes a syndrome tree ST, a syndrome decoder SD, a syndrome test circuit TC, and a data correction circuit DC. Among them, the syndrome tree ST includes p corresponding to the read data, that is, the 128-bit internal read signals M0 to M127 from the read amplifiers of 137 unit main amplifiers of the main amplifiers MAU and MAL.
And 9-bit internal read signals MC0 to MC8 corresponding to the check bits. Further, the syndrome decoder SD and the syndrome test circuit TC supply the output signal s, ie, 9 from the syndrome tree ST.
Bit syndromes S0 to S8 are commonly supplied.
Further, the data correction circuit DC includes a main amplifier MAU.
And MAL are supplied with internal read signals M0 to M127 and MC0 to MC8, and a total of 137-bit data correction signals C0 to C127 and CC0 to CC8 as output signals from the syndrome decoder SD.
Is supplied.

The output signal of the syndrome test circuit TC is
The test output signal TD is supplied to the interface circuit IF, and the output signal of the data correction circuit DC is the internal read data R0 to R127 corresponding to the read data or the internal read data RC corresponding to the check bit.
0 to RC8 are supplied to the interface circuit IF. As described above, the internal read data RC0 to RC8 corresponding to the check bits are
When the AM is set to a predetermined test mode, the signal is selectively output from the interface circuit IF to an external test apparatus,
The test output signal TD is selectively output from the interface circuit IF to an external access device when the dynamic RAM is set to another predetermined test mode.

ECC circuit ECC syndrome tree S
Although T is not particularly limited, as shown in FIG. 3, a total of 114 4-input exclusive OR circuits E11 to E17 are provided.
2, E21 to E233 and E31 to E39.
Among them, the first stage exclusive OR circuits E11 to E17
2 is connected to the main amplifier MA.
The internal read signals M0 to M127 and MC0 to MC8 are supplied in predetermined combinations from U and MAL, respectively, and the first to fourth input terminals of the exclusive OR circuits E21 to E233 of the second stage are connected to the first input terminals. The output signals of the exclusive OR circuits E11 to E172 at the stages are supplied in predetermined combinations. Further, the first to fourth input terminals of the third exclusive OR circuits E31 to E39 are supplied with the output signals of the second exclusive OR circuits E21 to E233 in a predetermined combination. The output signals are the syndromes S0 to S8, respectively.

In this embodiment, the ECC circuit ECC
Performs detection and correction of a bit error in accordance with the modified Hamming code as described above, and supplies the internal signals supplied to the first to fourth input terminals of the exclusive OR circuits E11 to E172 in the first stage of the syndrome tree ST. Read signals M0 to M1
The combination of 27 and MC0 to MC8 is based on the parity check matrix of the modified Hamming code. Therefore, the third of the syndrome tree ST
Syndromes S0 to S8 obtained as output signals of the exclusive OR circuits E31 to E39 at the stage, for example, as shown in FIG. Internal read signals M0 to M1 output from a total of 137 memory cells in the selected state
27 and MC0 to MC8 have no bit error.

On the other hand, when only one bit of the syndromes S0 to S8 becomes logic "1", it indicates that any one of the internal read signals MC0 to MC8 corresponding to the check bit has a single error. Become. Further, when the syndromes S0 to S8 become logic "1" for two or more bits in a combination not marked with-or * in FIG. 5, it is determined that any one of the internal read signals M0 to M127 has a single error. When two or more bits are logic "1" in the combination marked with * in FIG. 5, a double error, that is, an error of two bits or more, occurs in the internal read signals M0 to M127 and MC0 to MC8. It shows that there was. Needless to say, the internal read signals M0 to M0
The single error of M127 and MC0 to MC8 is caused by the data correction signal C0 as the output signal of the syndrome decoder SD.
ＣC127 and CC0 to CC8, but double errors cannot be corrected by detection alone.

The syndrome decoder SD is not particularly limited, but as shown in FIG.
To C127 and CC0 to CC8, a total of 137 9-input NOR gates NO0 to NO0
NO127 and NOC0 to NOC8. These NOR gates NO0 to NO127 and NOC0 to N
The first to ninth input terminals of the OC8 are supplied with syndromes S0 to S8, which are output signals of the syndrome tree ST, or inverted signals of the inverters V0 to V8 in a combination of FIGS. 4 and 5, respectively. Are corresponding data correction signals C0 to C127 and CC0 to CC8.

Thus, the NOR gates NO0-NO127 and NOC0-NO of the syndrome decoder SD
The data correction signals C0 to C127 and CC0 to CC8, which are output signals of C8, are output from the first to ninth signals of each NOR gate.
When all of the syndromes S0 to S8 or their inverted signals supplied in a combination corresponding to the input terminals are set to a low level, they are selectively set to a high level.

It should be noted that, although not particularly limited, in the syndrome decoder SD, the syndromes S0 to S8 become logic "1" for 2 bits or more in a combination marked with * in FIG. 5, and the internal read signals M0 to M127 and MC0 to MC0
When it is detected that the MC8 has a double error, an error signal (not shown) for the interface circuit IF is selectively set to a valid level. This error signal is output to the external access device as status information, whereby the external access device can identify that a double error has been detected at the specified address of the specified bank.

As shown in FIG. 2, the data correction circuit DC includes internal read signals M0 to M127 and MC0.
ＭＣMC8 are provided for 137 two-input exclusive OR circuits. One input terminal of these exclusive OR circuits has corresponding internal read signals M0 to M127 or MC0 to MC0 from the main amplifiers MAU and MAL.
MC8 is supplied respectively. A corresponding data correction signal C0 to C127 or CC0 to CC8 is supplied from the syndrome decoder SD to the other input terminal, and the output signal is the internal read data R
It is supplied to the interface circuit IF as 0 to R127 or RC0 to RC8.

Thus, the main amplifiers MAU and MA
The internal read signals M0 to M127 and MC0 to MC8 output from L correspond to the corresponding data correction signals C0 to C0.
When C127 or CC0 to CC8 is set to a low level, that is, logic "0", the internal read data R0 to R1 are not changed, that is, the logic level is not corrected.
27 or RC0 to RC8 to the interface circuit IF and the corresponding data correction signals C0 to C1
27 or when CC0 to CC8 are at a high level, that is, logic "1", after the logic level is inverted, in other words, after the logic level is corrected,
Internal read data R0 to R127 or RC0 to R
It is transmitted to the interface circuit IF as C8.

As a result, the bit errors of the internal read signals M0 to M127 and MC0 to MC8 output from the designated address of the designated bank of the dynamic RAM are detected and corrected by the ECC circuit ECC. The reliability of the dynamic RAM can be improved.

Next, although not particularly limited, the syndrome test circuit TC includes one 9-input NOR gate NOT as shown in FIG. The first of this NOR gate NOT
The syndromes S0 to S8 are supplied from the syndrome tree ST to the ninth input terminal, respectively, and the output signals are supplied to the interface circuit IF as output signals of the syndrome test circuit TC, that is, test output signals TD.

Thus, the test output signal TD, which is the output signal of the syndrome test circuit TC, is selectively output when the syndromes S0 to S8 supplied from the syndrome tree ST are all at a low level, that is, logic "0". That is, the test output signal TD is set to the high level, that is, the logic “1”. The test output signal TD is supplied to the
After 8 bits are collected as one packet, the data input / output terminals DQA0 to DQA7 and DQB0 to DQB
The data is output to an external test device via the external device 7.

As apparent from FIGS. 4 and 5, the fact that the syndromes S0 to S8 are all logic "0" means that the internal read signals M0 to M127 and MC0 to MC8 output from the main amplifiers MAU and MAL. Indicates that there was no 1-bit error. Therefore, the external test apparatus can determine the presence or absence of a bit error regarding the 128-bit read data that is output in parallel using one bit of the test output signal TD, and the test output signal T of one packet, that is, 128 bits can be determined.
With D, it is possible to determine the presence or absence of a bit error relating to a total of 128 × 128, that is, 2048 bytes of read data, and the reduction rate of the function test for the normal read mode is 1/128. As a result, the function test of the dynamic RAM can be efficiently performed, and the test cost of the dynamic RAM can be significantly reduced.

On the other hand, the detection and correction of bit errors by the syndromes S0 to S8 are performed by the internal read signals M0 to M127 and M, which are output from the main amplifiers MAU and MAL, as apparent from the principle of the modified Hamming code.
This is performed regardless of the logic levels of C0 to MC8. Therefore, in the function test using the test output signal TD of the syndrome test circuit TC, there is no restriction on the test data pattern, and the function test can be performed with an arbitrary data pattern. As a result, the function test of the dynamic RAM can be performed more efficiently, the test cost can be further reduced, and the failure detection rate of the function test can be further increased.

In this embodiment, the syndrome S0
Only the test output signal TD indicating that the processing information of S8 to S8, that is, the syndromes S0 to S8 are all bit logic "0", is output to an external test apparatus, but the entire 9-bit syndromes S0 to S8 are left as they are. You may make it possible to output to a test apparatus. In this case, the external test apparatus can also determine the presence or absence and the position of a bit error regarding the stored data read based on the given syndromes S0 to S8, thereby detecting the failure of the dynamic RAM. The rate can be further increased.

FIG. 8 is a partial circuit block diagram of an embodiment of the interface circuit IF included in the dynamic RAM of FIG. 1, and FIG. 9 is a diagram showing signals of the embodiment in the test mode. Waveform diagrams are shown. The specific configuration and operation of the interface circuit IF included in the dynamic RAM of this embodiment and the features thereof will be described with reference to both figures. FIG. 8 shows two shift registers SR0 out of 16 shift registers SR0 to SR15 provided in the interface circuit IF.
And only the SR15 and its related parts are illustrated. Also,
The interface circuit IF actually includes a circuit for outputting check bits, that is, internal read data RC0 to RC8, but is omitted in FIG. In FIG. 8, a MOSFE in which an arrow is attached to the channel (back gate) portion.
T is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

Referring to FIG. 8, an interface circuit IF
Are respectively r, that is, 8 bits, q, that is, 16 shift registers SR0 to SR15, 16 transfer gates G0 to G15 provided corresponding to these shift registers, and commonly provided to these shift registers. One output data selection circuit ODSL, data input / output terminals DQA0-DQA7 and DQB0-D
It includes 16 data output buffers OB0 to OB15 provided corresponding to QB7.

The data input terminal of each bit of the shift registers SR0 to SR15 constituting the interface circuit IF is provided with a corresponding output signal of the data correction circuit DC of the ECC circuit ECC, that is, internal read data R0 to R127.
And RC0 to RC8, respectively. Also,
An output signal of the syndrome test circuit TC, that is, a test output signal TD is commonly supplied to the first bit of each shift register via transfer gates G0 to G15, and a control terminal of each shift register is provided with an interface circuit I
F, a latch control signal LC, a shift clock signal SCK, and a test enable signal T from a control circuit (not shown).
EN2 is commonly supplied. Transfer gate G0
The test enable signal TEN1 is commonly supplied to the gates of the N-channel MOSFETs constituting the G15.
An inverted signal from the inverter VG is commonly supplied to the gate of the channel MOSFET.

The test enable signals TEN1 and T
EN2 is set to a high level at a predetermined timing when the dynamic RAM is set to a predetermined test mode, that is, when a predetermined function test using a test output signal TD is performed by an external test apparatus. When the test enable signal TEN1 is set to a high level, all output terminals of the data correction circuit DC corresponding to the internal read data R0 to R127 and RC0 to RC8 are set to a high impedance state.

On the other hand, the first of the output data selection circuit ODSL is
The 128th data input terminal has a shift register SR
Output signals ST0 to ST127 of respective bits 0 to SR15
Are respectively supplied to the address input terminals thereof, and i + 1-bit selection address signals SA0 to SAi are supplied from an address buffer (not shown). Further, the data input terminals of the data output buffers OB0 to OB15 have
The corresponding output signal SO0 of the output data selection circuit ODSL
To SO15, and an output control signal OC is commonly supplied to its control terminal.

By the way, the dynamic type R of this embodiment
AM is synchronously operated according to a clock signal CLK having a relatively high frequency, as shown in FIG. When the dynamic RAM is set to the normal read mode, the main amplifier MA is connected to the interface circuit IF.
Internal read data R0 to R127 output from U and MAL via the ECC circuit ECC are latch control signals L
According to C, the bits are taken in parallel by the corresponding bits of the shift registers SR0 to SR15 and held. These internal read data are selected by the output data selection circuit ODSL in accordance with the selected address signals SA0 to SAi in 2 bytes, that is, 16 bits at a time.
Data output buffers OB0 to OB corresponding to SO15
It is transmitted to B15. Data output buffer OB0-OB
Numeral 15 selectively operates in response to the high level of the output control signal OC, and outputs 16-bit read data transmitted from the output data selection circuit ODSL via the data input / output terminals DQA0 to DQA7 and DQB0 to DQB7. Output to the access device.

On the other hand, the dynamic RAM is set to a predetermined test mode, and a test output signal T
When a predetermined functional test using D is performed, a row address input terminal RA and a column address input terminal CA are provided with an address for a maximum of 2048 bytes that can be tested by one access, as shown in FIG. Up to 12 for etc
Eight test packets TRCP0 to TRCP127 are supplied corresponding to four cycles of the clock signal CLK, and the data input / output terminals DQA0 to DQA7 and DQB0
When a predetermined time tCDRP has elapsed since the last test packet TRCP127 was input to DQB7, the output signals of the syndrome test circuits TC corresponding to the test packets TRCP0 to TRCP127, that is, the test output signals TD are sequentially transmitted to the interface circuit IF. Is entered.

In the interface circuit IF, the shift registers SR0 to SR15 output the test enable signal TEN
In response to the high level of 2, the shift operation according to the shift clock signal SCK is performed. Therefore, first, the test output signal TD corresponding to the first test packet TRCP0 is fetched as the test output signal TD0 into the first bit of the shift register SR0 via the transfer gate G0, and is transmitted to the subsequent seven test packets TRCP1 to TRCP7. The corresponding test output signals TD are the test output signals TD1 to TD7
Are sequentially taken into the second to eighth bits.

Thereafter, the test output signal TD is sequentially taken into the first to eighth bits of the shift registers SR1 to SR15 by the same shift operation, and the test output signal TD8
To TD127. Further, these test output signals TD
As shown in FIG. 9, 0 to TD127 are sequentially selected by the output data selection circuit ODSL for 2 bytes, that is, 16 bits, and thereafter, during 4 cycles of the clock signal CLK, 8 clocks are synchronized with the rise and fall of the clock signal CLK.
The data is divided and output from data input / output terminals DQA0 to DQA7 and DQB0 to DQB7 to an external test apparatus.

As described above, the test output signals TD0 to TD
One bit of 127 corresponds to the test result of the 128-bit internal read signals M0 to M127 output simultaneously via the main amplifiers MAU and MAL. Therefore, the external test apparatus determines that one of the test output signals TD0 to TD127
The presence / absence of a bit error related to 128-bit read data can be determined based on the bits, so that one packet, that is, 12 bits
With the 8-bit test output signals TD0 to TD127, it is possible to determine the presence or absence of a bit error related to a total of p × q × r, that is, 2048 bytes of read data. As a result, the function test of the dynamic RAM can be efficiently performed, and the test cost of the dynamic RAM can be significantly reduced.

The operation and effect obtained from the above embodiment are as follows. That is, (1) a plurality of banks, a predetermined number of main amplifiers for simultaneously writing or reading storage data to and from a predetermined number of memory cells of a designated bank, and parallel storage data between these main amplifiers. And an ECC circuit for detecting and correcting a bit error of, for example, 128-bit storage data transmitted and received between the main amplifier and the interface circuit.
For example, a 9-bit syndrome generated by the circuit or a 1-bit test output signal indicating that all the bits are logic “0” is output to the interface circuit by, for example, 12 bits.
By accumulating 8 bits and outputting the data in a 16 × 8 bit packet format through, for example, 16 data input / output terminals, the reduction rate at the time of a function test of a dynamic RAM having a plurality of banks can be reduced to 1 / 128 can be obtained. (2) According to the above item (1), it is possible to obtain an effect that the function test of the dynamic RAM or the like can be made more efficient and the test cost can be reduced.

(3) According to the above item (1), the effect is obtained that the restriction on the test data pattern can be solved and the functional test can be performed with an arbitrary pattern. (4) According to the above item (3), the effect that the failure detection rate of the function test can be increased and the reliability of the dynamic RAM or the like can be increased.

(5) In the above items (1) to (4), by outputting the syndrome generated by, for example, the ECC circuit to the test device as it is, the address at which a bit error has occurred by the external test device can also be identified. The effect that it can be obtained is obtained. (6) According to the above item (5), the effect that the test cost of the dynamic RAM can be further reduced, the failure detection rate of the function test can be further increased, and the reliability of the dynamic RAM and the like can be further improved can be obtained. .

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the dynamic RAM can include an arbitrary number of banks, and the memory arrays ARYU0 to ARYUF and ARYL0 constituting each bank can be provided.
ARYLF can include any number of redundant elements. Further, the dynamic RAM can be a so-called independent type in which a sense amplifier is exclusively used by each bank, and its block configuration can take various embodiments.

In FIG. 2, the ECC circuit ECC may detect and correct a bit error in stored data according to an arbitrary linear code having a syndrome. The ECC circuit ECC, that is, the interface circuit IF
The number of bits of storage data transmitted and received between the main amplifiers MAU and MAL can be set arbitrarily, and the number of check bits added by the ECC circuit ECC also changes according to the number of bits of storage data. As described above, the syndrome test circuit TC includes all the syndromes S0 to S0.
S8 can be output. When the linear code used in the ECC circuit ECC is a normal extended Hamming code, for example, the first bit S0 of the syndrome is used.
And a test output signal indicating that all of the other syndromes S1 to S8 have the logical value “0”. In the case of the former, PX in one access
Since a function test is performed on the memory cell of q × r / s, that is, 2048/9 bytes, the reduction rate is s / 128
That is, it is 9/128. In the latter case, since a functional test is performed on a memory cell of p × q × r / 2, that is, 2048/2 bytes in one access, the reduction rate is 2/128, that is, 1/64. Further, the syndromes S0 to S8 and the processing information thereof may be output other than in the test mode.

In FIG. 3, FIG. 6, FIG. 7 and FIG.
The specific configuration of the syndrome tree ST, the syndrome decoder SD, the syndrome test circuit TC, and the interface circuit IF of the ECC circuit ECC does not limit the gist of the present invention. 4 and 5, the logical conditions for the syndromes S0 to S8 of the syndrome decoder SD are merely examples, and various combinations can be taken. In FIG. 9, the specific time and level relationship between the clock signal CLK, each address signal, and the test output signal are not limited by the present embodiment. Further, in the present embodiment, 128 test packets T
RCP0 to TRCP127 are input, and functional tests for these test packets are performed simultaneously. However, an arbitrary number of test packets are input to the dynamic RAM, and partial functional tests for these test packets are performed. It is also possible.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the application field of the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices having a dynamic RAM as a basic configuration, and logic integrated circuit devices including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor memory device having an ECC circuit and a device or system including the same.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of banks, a predetermined number of main amplifiers for simultaneously writing or reading storage data to or from a predetermined number of memory cells in the designated bank, and storage data are transferred between these main amplifiers in parallel. In a dynamic RAM or the like having an interface circuit, an ECC circuit for detecting and correcting a bit error of, for example, 128-bit storage data transmitted and received between the main amplifier and the interface circuit is provided. A 9-bit syndrome or a 1-bit test output signal indicating that all the bits are logic "0" is accumulated in the interface circuit for, for example, 128 bits, and output in a packet format via the data input / output terminal. For functional tests of dynamic RAMs, etc. It is possible to enlarge the contraction rate, for example, in 1/128, eg when outputting the syndrome generated by the ECC circuit directly to the test apparatus, it is possible to identify the address generated bit error by an external testing device. Also, ECC
Since the functional test by the circuit can be performed irrespective of the logic level of the data, the restriction on the test data pattern can be resolved and the functional test can be performed with an arbitrary pattern. As a result, the test cost of the dynamic RAM and the like can be reduced, the failure detection rate of the function test can be increased, and the reliability of the dynamic RAM and the like can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is an ECC included in the dynamic RAM of FIG. 1;
FIG. 3 is a block diagram illustrating an example of a circuit.

FIG. 3 is a partial circuit diagram showing one embodiment of a syndrome tree included in the ECC circuit of FIG. 2;

FIG. 4 is a logical condition diagram showing one embodiment of a syndrome decoder included in the ECC circuit of FIG. 2;

FIG. 5 is a logic condition diagram showing one embodiment of the syndrome decoder included in the ECC circuit of FIG. 2 when a single error occurs.

FIG. 6 is a partial circuit diagram showing one embodiment of a syndrome decoder included in the ECC circuit of FIG. 2;

FIG. 7 is a circuit diagram showing one embodiment of a syndrome test circuit included in the ECC circuit of FIG. 2;

FIG. 8 is a partial circuit block diagram showing one embodiment of an interface circuit included in the dynamic RAM of FIG. 1;

FIG. 9 is a signal waveform diagram showing one embodiment during a read operation of the dynamic RAM of FIG. 1;

FIG. 10 is a partial circuit diagram showing an example of an interface circuit and a reduction test circuit of a dynamic RAM developed by the present inventors prior to the present invention.

11 is a signal waveform diagram showing an example of a read operation of the dynamic RAM of FIG. 10;

[Explanation of symbols]

IF: Interface circuit, ECC: ECC circuit, BANK0-BANKF: Bank, ARYU0
ARYUF, ARYL0 to ARYLF ... memory array, SAU0 to SAUG, SAL0 to SALG ... sense amplifier, RDU, RDL ... row address decoder,
MAU, MAL ... Main amplifier, CDU, CDL ...
Column address decoder. ST: Syndrome tree, SD: Syndrome decoder, TC: Syndrome test circuit, TD: Test output signal, DC: Data correction circuit, M0 to M127 ... Internal read signal (data), MC0 to MC8 ... Internal read signal (check bit), S0 to S8, syndrome, C0 to C12
7 Data correction signal (for data correction), CC0 to CC
8 Data correction signal (for check bit correction), R0
.About.R127... Internal read data (data), RC0
.About.RC8... Internal read data (check bit).
E11 to E172: first stage exclusive OR circuit, E21
To E233: second stage exclusive OR circuit, E31 to E3
9: Third stage exclusive OR circuit V0-V8... Inverter, NO0-NO127, NOC0-NOC8, NO
T: NOR gate. TEN1 ~ TEN2 ...
Test enable signal, LC ... Latch control signal, SCK
... Shift clock signal, G0 to G15 ... Transfer gate, VG ... Inverter, SR0 to SR15 ...
Shift register, LC ... Latch control signal, SCK ...
Shift clock signal, TD0 to TD127 ... test output signal, ST0 to ST127 ... shift register output signal, ODSL ... output data selection circuit, SA0 to SAi
... Selection address signal, SO0-SO15 output data selection circuit output signal, OB0-OB15 data output buffer, OC output control signal, DQA0-DQA
7, DQB0 to DQB7 ... data input / output terminals. CLK
…… Clock signal, RA …… Row address signal, CA…
... column address signal, DQA, DQB ... data input / output terminals, TRCP0-TRCP127, TRC0-TR
C7: Test packet. NA0 to NA15 ... NAND gate, MD, MD0 to MD127 ... contraction test output signal. MTC: Reduction test circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA07 5B018 GA02 GA03 HA01 JA11 NA02 QA13 5B024 AA15 BA29 CA16 EA01 EA07 5L106 AA01 AA15 BB12 DD01 FF01 GG00 GG02 9A001 BB05 JJ48 KK54 LL05

Claims (6)

[Claims] An ECC circuit for detecting and correcting a bit error of stored data based on a linear code having a syndrome, and having a configuration capable of outputting the syndrome or its processing information to the outside. A semiconductor memory device characterized by the following. 2. The method according to claim 1, wherein the linear code is a Hamming code, and the processing information of the syndrome can indicate that all bits of the syndrome are logic “0”. A semiconductor memory device characterized by the following. 3. The semiconductor memory device according to claim 1, wherein the syndrome or its processing information is output to an external test device in a predetermined test mode. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises: a plurality of banks each capable of independently performing a word line selecting operation; A predetermined number of main amplifiers for writing or reading storage data to or from a predetermined number of memory cells to be coupled; and an interface circuit for transmitting and receiving storage data in parallel between the predetermined number of main amplifiers. A semiconductor device, wherein the ECC circuit adds a predetermined number of check bits to stored data transmitted between the main amplifier and the interface circuit, or detects and corrects a bit error thereof. Storage device. 5. The semiconductor memory device according to claim 4, wherein the number of bits of the storage data transmitted and received between the main amplifier and the interface circuit is p bits. And q data input buffers and data output buffers provided corresponding to the input / output terminals, wherein the interface circuit inputs or outputs in a packet format via the q data input / output terminals. Q × r
A semiconductor memory device comprising q r-bit-length shift registers for replacing bit storage data with p-bit parallel data. 6. The syndrome according to claim 4, wherein the syndrome comprises s bits, and the syndrome or the processed data thereof comprises the q × r bits via the q data input / output terminals. The test mode is p × q × r / s or p × q × r
A semiconductor memory device which is in a reduced test mode in which a write or read test operation of storage data to or from a memory cell can be performed by one access.