JP2000031481A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance threshold controllability in the case of manufacturing a MOSFET by providing a carbon doped layer at a position isolated from a silicon substrate surface, thereby suppressing inactivation of impurities. SOLUTION: A carbon doped layer 2 is formed at a position of a depth of 50 nm from a surface with a thickness of 50 nm in a silicon layer 1, and a channel impurity layer 3 for controlling a threshold formed in a depth of about 150 nm. Further, a gate insulating film 4 of 5 nm, a gate electrode 5 having a height of 200 nm and a gate length of 0.18 m and sidewall insulating films 6 of 70 nm at both sides of the electrode 5 are formed on a silicon substrate surface. A source extended part 7 in which an arsenic is implanted, a drain extended part 9, and a source 8 and a drain 10 in which an arsenic is implanted are formed. Thus, a short channel effect of a MOSFET can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure and a method of manufacturing a semiconductor device, and more particularly to a structure and a method of manufacturing a MOSFET.

[0002]

2. Description of the Related Art It is known that impurities are diffused by heat treatment during the manufacture of MOSFETs to deteriorate the characteristics such as a short channel effect. When a defect (interstitial silicon) is present in the crystal, the degree of diffusion of the impurity is orders of magnitude greater than when there is no defect (enhanced diffusion). It is said that the reason for this is that interstitial silicon diffuses by pairing with impurities such as boron. Therefore, it can be seen that the impurities in the channel of the MOSFET diffuse more than the designed distribution, and the threshold value largely deviates from the originally intended threshold value. Also source,
The distribution of the impurity used for the drain deviates from the originally targeted distribution due to the enhanced diffusion, resulting in a deeper junction depth and a large lateral diffusion, which is much shorter than the targeted channel length. Are known.

Attempts have been made to suppress the diffusion of such impurities as much as possible and to design the characteristics of the MOSFET. FIG. 6 shows a technique for suppressing the enhanced diffusion of impurities in a channel (GG Shahidi et al.
VLSI Symposium, June 1993, 93-94
page). The structure is almost the same as that of a normal MOSFET, but the type of impurity doped in the channel impurity layer 82 is different. Normally, the impurities in this layer are n-type MOSFE
T uses boron, and p-type MOSFET uses phosphorus or arsenic. In this case, n-type MOSFET uses indium and p-type MOSFET uses antimony. Indium and antimony have a larger radius and a smaller degree of diffusion than other atoms. Therefore, there is little accelerated diffusion associated with the interstitial silicon described above, and an impurity distribution close to the design can be obtained.

FIG. 7 shows another technique for suppressing the enhanced diffusion in the prior art (Ibrahim Ban et al., IEEE).
Transaction on Electron
Devices, Vol. 44, 1997, 15
44-1551). This utilizes the effect of suppressing the accelerated diffusion of impurities associated with crystal defects by doping carbon. It is not yet clear why carbon doping can suppress the accelerated diffusion of impurities, but it is thought that lattice defects are trapped in the presence of carbon, and the effect of diffusion suppression has been reported as experimental facts. ing. In FIG. 7, the structure is almost the same as that of a normal MOSFET, except that the channel impurity and the carbon-doped layer 92 are different.
Are different. Normally, this layer is doped only with channel impurities, but here, both channel impurities of boron and carbon are doped. This technique can suppress the accelerated diffusion of the channel impurity and obtain a channel impurity distribution close to the design.

[0005]

However, in the above-mentioned MOSFET, although the distribution of impurities is close to the design due to the suppression of diffusion, the activation rate of impurities is low. Have the following problems. For example, when antimony or indium is used as an impurity, the activation rate is about one-third that of arsenic or boron.
Has fallen. When carbon is simultaneously doped,
The activation rate depends on the doping amount of carbon, but falls from half to one-tenth. For this reason, threshold shift and increase in parasitic resistance due to inactivation of impurities have been observed. Also,
The low activation rate is due to the large activation energy, and there is a problem that the number of carriers changes depending on the operating temperature of the element, and the characteristics change.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the threshold controllability in manufacturing a MOSFET by solving the above-mentioned problems in the prior art, realizing an impurity distribution close to the design, and suppressing the inactivation of impurities. It is to provide a way to do it.

[0007]

According to the present invention, there is provided a gate electrode formed on a silicon substrate with a gate insulating film interposed therebetween, and a region immediately below the gate electrode. A channel impurity layer, a source region and a drain region formed adjacent to the channel impurity layer, and a carbon doped layer at a position separated from the silicon substrate surface. Provided.

Since the semiconductor device of the present invention includes the carbon doped layer for preventing the accelerated diffusion of the impurity, the distribution of the channel impurity layer and the source / drain regions and the impurity concentration are precisely controlled. Therefore, variation in characteristics is reduced as compared with the conventional device, and the reliability of the element is improved. In addition, since the carbon-doped layer having such an effect is provided at a position separated from the surface of the silicon substrate, inactivation of impurities does not occur, and problems such as threshold shift and increase in parasitic resistance are avoided. can do.

Further, according to the present invention, the following method for manufacturing a semiconductor device is provided. Any of these methods is capable of manufacturing the semiconductor device.

That is, according to the present invention, a step of forming a carbon-doped layer by ion-implanting carbon into a silicon substrate and growing a silicon layer thereon, a step of forming an element isolation region, A method of manufacturing a semiconductor device, comprising: forming a gate electrode through a gate insulating film; and forming a source region and a drain region by ion implantation.

Further, according to the present invention, a step of forming an element isolation region after growing a carbon-doped silicon layer and a silicon layer in this order on a silicon substrate, and a step of forming a gate insulating film on the silicon layer Forming a gate electrode and forming a source region and a drain region by ion implantation.

Further, according to the present invention, after forming an element isolation layer on a silicon substrate, a carbon-doped silicon layer and a silicon layer are grown on the silicon substrate in this order, and a gate insulating layer is formed on the silicon layer. There is provided a method for manufacturing a semiconductor device, comprising a step of forming a gate electrode through a film and a step of forming a source region and a drain region by ion implantation.

Further, according to the present invention, after forming an element isolation layer on a silicon substrate, the exposed surface of the silicon substrate is removed by etching, and carbon is ion-implanted into the silicon substrate to form a carbon doped layer. Thereafter, a step of growing a silicon layer thereon, a step of forming a gate electrode on the silicon layer via a gate insulating film, and a step of forming source and drain regions by ion implantation And a method of manufacturing a semiconductor device characterized by the following.

In the above-described method of manufacturing a semiconductor device,
"Silicon layer" refers to a silicon layer having a carbon concentration of a certain value or less. It is preferable that the non-doped silicon layer is undoped with carbon, but 1 × 10 ¹⁷ or less of carbon may be doped. This is because in this range, inactivation of impurities by carbon doping does not occur.

In the above-described method of manufacturing a semiconductor device, a silicon layer which is not doped with carbon or has a carbon concentration equal to or lower than a predetermined value is disposed above and below the carbon-doped layer. In this silicon layer, the activation rate of the impurity due to carbon does not decrease, and the impurity is sufficiently activated. Therefore, according to the present invention, by realizing an impurity distribution close to the design and suppressing the inactivation of impurities, the MOS
A method is provided for improving threshold controllability in manufacturing a FET.

According to the present invention, there is provided a silicon substrate having a carbon-doped layer at a position separated from the surface.

By using the silicon substrate of the present invention, it is possible to easily obtain a semiconductor device in which the distribution and impurity concentration of the channel impurity layer and the source / drain regions are precisely controlled and the activity ratio of the impurity is maintained at a high level. be able to.

Hereinafter, the operation of the present invention will be described in detail.

First, the effect on the channel impurity distribution will be described. If the thickness of the carbon-doped layer is smaller than the thickness of the channel, the influence of the carbon-doped layer is reduced when the activation of impurities in the entire channel layer is observed. Therefore, the influence of the inactivation of the impurities on the threshold shift can be reduced as compared with the case where the conventional method is used. On the other hand, the shift of the channel impurity distribution due to the accelerated diffusion of the impurity is reduced by using the method of the present invention for the following reason. The carbon doped layer is at a certain depth over the entire MOSFET region. For this reason, the interstitial silicon in the middle of diffusion near the position of interstitial silicon generated by ion implantation or the like is immediately trapped by the carbon-doped layer. Impurities are accelerated and diffused by the interaction with the interstitial silicon,
If the interstitial silicon is trapped immediately and does not move, the accelerated diffusion of impurities is also suppressed. Thereby, MOSF
Redistribution of impurities due to heat treatment during ET manufacturing is reduced,
A channel impurity distribution substantially close to the design is achieved. Thereby, the threshold value can be almost as designed.

Next, the effect on the source / drain impurity distribution will be described. What is demanded as the impurity distribution of the source / drain is to be as thin as possible and have a high carrier concentration. For this purpose, it is necessary that the impurity concentration is high and the activation rate is as high as possible. Further, it is preferable that the layer containing impurities is localized on the surface of the silicon substrate as much as possible. In the present invention, the outermost surface layer of the silicon substrate is not doped with carbon that lowers the activation rate of impurities. Therefore, the carrier concentration in the surface layer of the source / drain can be kept high. Also, it is usually difficult for the impurity to diffuse at high speed due to the influence of interstitial silicon and localize it on the surface of the silicon substrate. However, localization is possible with this method. This is because the carbon-doped layer traps interstitial silicon, thereby suppressing the accelerated diffusion of the impurity in the source / drain surface layer that diffuses in association with the silicon.

Thus, according to the present invention, the MOSFE
It is possible to suppress the diffusion of the channel impurity and the source / drain impurity of T and a reduction in the activation rate thereof.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, it is preferable that a carbon-doped layer is provided so as to include at least one of a channel impurity layer, a source region and a drain region. Thereby, the above-described trapping effect of interstitial silicon is enhanced, and accelerated diffusion of impurities can be more effectively prevented.

In the present invention, a carbon doped layer is formed.
Position is preferably 5 to 100 nm from the substrate surface,
More preferably, it is 30 to 60 nm. Where carbon
The position where the doped layer is formed is the upper surface of the carbon doped layer
And the distance between the substrate and the substrate surface. Also, the carbon dope layer
The thickness is preferably 5 to 100 nm, more preferably
30 to 100 nm. Also, the carbon concentration of the carbon doped layer
Is preferably 1 × 10¹⁸cm^-3~ 1 × 10^{twenty one}cm^-3,
More preferably, 1 × 10¹⁹cm^-3~ 1 × 10 ²⁰cm^-3
And As described above, the interstitial silicon
The lapping effect prevents impurity diffusion
The activity rate of the product can be maintained at a high level.

In the present invention, the layers disposed above and below the carbon-doped layer are preferably not doped with carbon, but may be doped with carbon of 1 × 10 ¹⁷ or less. Good. This is because in this range, inactivation of impurities by carbon doping does not occur.

[0025]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 shows a first embodiment of the present invention.
1 is a cross-sectional view illustrating a structure of a MOSFET. Silico
Concentration of 1 × 10²⁰cm^-3Of the carbon doped layer 2
Formed at a depth of 50 nm from the surface with a thickness of 50 nm
I have. The channel impurity layer 3 for controlling the threshold has a depth of 1
Boron concentration 1 × 10 at about 50 nm¹⁷cm^-3Formed by
ing. 5nm gate insulating film on silicon substrate surface
4. A gate with a height of 200 nm and a gate length of 0.18 μm
Electrode 5 and sidewall insulating films 6 formed on both sides thereof to a thickness of 70 nm.
Have been. As for the source and drain, arsenic is doped.
Dose 5 × 10¹⁴cm^-2Source extension 7 introduced in
And drain extension 9, arsenic dose 5 × 10^Fifteencm
^-2Source 8 and drain 10 introduced at
ing.

Here, the carbon-doped layer 2 is formed over the entire area shown in the figure, but may be formed only in the channel impurity layer 3 and the source extension 7 and the drain extension 10. The depth from the surface of the carbon-doped layer may be in the range of 5 to 100 nm, and its thickness is 5 to 10 nm.
The range may be 0 nm. The carbon concentration is 1 × 10 ²⁰ cm
^Although it was set to ^-3 , it may be a value in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

Although the present invention has been described with reference to an n-type MOSFET, it goes without saying that the type of impurity may be changed for a p-type MOSFET.

In this embodiment, the source and the drain have a two-layer structure with the extension, but the source and the drain may have a single-layered structure extending to the extension.

The well and element isolation are not shown because they are not directly related to the features of the present invention.

(Embodiment 2) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a diagram showing a method of manufacturing a MOSFET as a semiconductor device. FIG.
(A) As shown in FIG.¹⁴cm^-3About
1 × 10 in the p-type silicon layer 21²⁰cm^-3Concentration of
The carbon doped layer 22 having a thickness of 50 nm from the surface by 50 nm
A silicon substrate formed at a depth of is prepared. Next, FIG.
Element isolation 23, well (not shown) as shown in FIG.
To form Next, as shown in FIG.
Dose of boron at an acceleration energy of 50 keV
1 × 10 ¹³cm^-2And the channel impurity layer 24 is
Form. Then, a 5 nm thick gate made of silicon oxide was used.
A gate insulating film 25 and a polysilicon film are formed at a thickness of 200 nm.
And then etching through resist coating, exposure and development processes
To form the gate electrode 26. Next, the acceleration energy
-10 keV and dose 5 × 10¹⁴cm^-2Arsenic in Io
Injection. Thereby, the source extension 28, the drain
An extension 30 is formed. Next, an insulating film having a thickness of 70
nm gate sidewall insulating film 27 is formed, and acceleration energy
Dose 5 × 10 at 30 keV^Fifteencm^-2Arsenic ions
It is implanted and heat-treated at 1000 ° C. for several tens of seconds. This allows
A source 29 and a drain 31 are formed.

(Embodiment 3) FIG. 3 is a view showing a method of manufacturing a MOSFET as a third embodiment of the present invention. FIG.
As shown in (a), an element isolation 42 is formed on a p-type silicon silicon substrate 41 having an impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ .
A well (not shown) is formed. Next, as shown in FIG. 3B, a silicon layer is selectively epitaxially grown on silicon other than the element isolation 42. During this growth,
The carbon-doped epi layer 43 grown while doping with carbon is
0 nm thick, and a non-doped epi layer 4
4 is provided with a thickness of 50 nm. Next, as shown in FIG. 3 (c), boron is implanted with an acceleration energy of 50
The channel impurity layer 45 is formed by doping with keV at a dose of 1 × 10 ¹³ cm ⁻² . Then, a 5 nm thick gate insulating film 46 made of silicon oxide and a polysilicon film
After being formed to a thickness of 00 nm, the gate electrode 47 is formed by etching after passing through resist coating, exposure and development steps. Next, at an acceleration energy of 10 keV and a dose of 5 × 10 ¹⁴ c
Arsenic of m ⁻² is ion-implanted. Thus, a source extension 49 and a drain extension 51 are formed. Next, a gate sidewall insulating film 48 having a thickness of 70 nm is formed using an insulating film, and a dose of 5 × 10 ¹⁵ c at an acceleration energy of 30 keV.
Arsenic of m ⁻² is ion-implanted and heat-treated at 1000 ° C. for several tens of seconds. Thus, a source 50 and a drain 52 are formed.

(Embodiment 4) The fourth embodiment of the present invention relates to the third embodiment.
Is a part of the embodiment of FIG. In the third embodiment, only the step shown in FIG. 3B is changed as follows. Carbon is ion-implanted at a dose of 1 × 10 ¹⁵ cm ⁻² at 5 keV into the entire surface of the silicon substrate or a region other than the element isolation 42, and then heat-treated at 1000 ° C. for 30 seconds to form a silicon layer having a thickness of 50 nm. It grows epitaxially.
Thereafter, the steps described in the third embodiment with reference to FIG.

(Embodiment 5) FIG. 4 is a diagram showing a method of manufacturing a MOSFET as a fifth embodiment of the present invention. FIG.
As shown in FIG. 2A, an element isolation 62 is formed on a p-type silicon substrate 61 having an impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ .
A well (not shown) is formed. Next, as shown in FIG. 4B, the silicon layer other than the element isolation 62 is removed by etching to a thickness of, for example, 100 nm (etched removal layer 63). Next, as shown in FIG. 4C, a silicon layer is selectively epitaxially grown on the etched portion. At the time of this growth, a carbon-doped epi layer 64 that grows while doping with carbon is provided with a thickness of 50 nm, and a non-doped epi layer 65 is provided with a thickness of 50 nm on the uppermost surface.
Next, as shown in FIG. 4D, boron is ion-implanted and accelerated at an energy of 50 keV and a dose of 1 × 10 ¹³ c.
The channel impurity layer 66 is formed by doping with m ⁻² . Then, a 5 nm-thick gate insulating film 6 made of silicon oxide
7. After forming a polysilicon film with a thickness of 200 nm, the gate electrode 68 is formed by etching after passing through resist coating, exposure and development steps. Next, the acceleration energy is 10 keV
Arsenic is ion-implanted at a dose of 5 × 10 ¹⁴ cm ⁻² .
Thus, a source extension 70 and a drain extension 72 are formed. Next, a gate sidewall insulating film 69 having a thickness of 70 nm is formed by an insulating film, and arsenic having a dose of 5 × 10 ¹⁵ cm ⁻² is ion-implanted at an acceleration energy of 30 keV.
Heat treatment at 00 ° C. for several tens of seconds. Thereby, the source 71,
A drain 73 is formed.

In the second, third and fourth embodiments, the n-type MOSFET has been described.
For a FET, the type of impurity may be reversed so that the conductivity type of the generated carrier is reversed (for example, arsenic may be changed to boron and boron may be changed to arsenic). Further, the thickness of the carbon-doped layer is 50 nm in the embodiment, but may be changed in the range of 5 to 100 nm. Further, the depth of the carbon-doped layer was set to 50 nm in the embodiment, but was
It may be changed in the range of 00 nm.

(Embodiment 6) The sixth embodiment of the present invention relates to the fifth embodiment.
Is a part of the embodiment of FIG. In the fifth embodiment, only the step shown in FIG. 4C is changed as follows. Carbon is ion-implanted at a dose of 1 × 10 ¹⁵ cm ⁻² at 5 keV into the entire surface of the silicon substrate or a region other than the element isolation 62, and then heat-treated at 1000 ° C. for 30 seconds to form a silicon layer with a thickness of 50 nm. It grows epitaxially.
Thereafter, the step described with reference to FIG.

(Embodiment 7) FIG. 5 is a view showing a structure of a semiconductor silicon substrate as a seventh embodiment of the present invention. The structure is such that the carbon-doped layer 2 is embedded in the silicon layer 1, and the carbon-doped silicon layer has a thickness of 50 nm and a depth from the surface of 50 nm.

To manufacture this semiconductor silicon substrate,
Silicon The silicon substrate is accelerated with 5 keV acceleration energy.
Ion implantation of carbon at a dose of × 10 ¹⁵ cm ^-2
After heat treatment at 00 ° C. for about 1 hour, the silicon layer is
It can be manufactured by epitaxial growth with a thickness of m. Another method is to use 1 × 10 ²⁰ c
It can be manufactured by epitaxially growing a carbon-doped silicon layer having a concentration of m ⁻³ at 50 nm, followed by a non-doped silicon layer at 50 nm.

Here, the thickness of the carbon-doped silicon layer is 50 nm, but may be 5 to 100 nm. The depth from the surface is set to 50 nm.
To 100 nm. The carbon concentration is 1 × 10 ²⁰
cm ⁻³ , but 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm
A value in the range of ^-3 may be used.

[0040]

According to the structure and the manufacturing method of the semiconductor device of the present invention, the short channel effect of the MOSFET can be suppressed, and the threshold shift due to the decrease in the activation rate of impurities, which has been a problem in the past, can be prevented. An increase in parasitic resistance can be suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a structure of a semiconductor device of the present invention.

FIG. 2 is a schematic sectional view of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a schematic sectional view of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a schematic cross-sectional view of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a schematic cross-sectional view of the structure of the silicon substrate of the present invention.

FIG. 6 is a schematic cross-sectional view of a structure of a conventional semiconductor device.

FIG. 7 is a schematic sectional view of a structure of a conventional semiconductor device.

[Explanation of symbols]

 1, 21 silicon layer 2, 22 carbon doped layer 3, 24, 45, 82 channel impurity layer 4, 25, 46, 83 gate insulating film 5, 26, 47, 84 gate electrode 6, 27, 48, 85 gate sidewall insulation Membrane 7, 28, 49, 86 Source extension 8, 29, 50, 87 Source 9, 30, 51, 88 Drain extension 10, 31, 52, 89 Drain 23 Element isolation 41, 81 Silicon silicon substrate 42 Element isolation 43 Carbon doped epi layer 44 Non-doped epi layer 92 Channel impurity and carbon doped layer

Claims (17)

[Claims] A gate electrode provided on a silicon substrate via a gate insulating film, a channel impurity layer formed to include a region immediately below the gate electrode, and a channel impurity layer formed adjacent to the channel impurity layer. A semiconductor region, comprising: a source region and a drain region; and a carbon doped layer at a position separated from the surface of the silicon substrate. 2. The method according to claim 2, wherein the carbon-doped layer is one of the channel impurity layer, the source region, and the drain region.
The semiconductor device according to claim 1, wherein the semiconductor device is provided so as to include at least one of them. 3. The semiconductor device according to claim 1, wherein the carbon-doped layer is provided at a position separated from the surface of the silicon substrate by 5 to 100 nm. 4. The carbon doped layer has a thickness of 5 to 100 n.
4. The method of manufacturing a semiconductor device according to claim 1, wherein m is m. 5. The carbon concentration of the carbon doped layer is 1 × 1
The semiconductor device according to claim 1, wherein the semiconductor device has a size of 0 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . 6. A step of forming a carbon doped layer by ion-implanting carbon into a silicon substrate and growing a silicon layer thereon, a step of forming an element isolation region, and forming a gate insulating layer on the silicon layer. A method for manufacturing a semiconductor device, comprising: a step of forming a gate electrode through a film; and a step of forming a source region and a drain region by ion implantation. 7. A step of growing a carbon-doped silicon layer and a silicon layer on a silicon substrate in this order, forming an element isolation region, and forming a gate electrode on the silicon layer via a gate insulating film. And a step of forming a source region and a drain region by ion implantation. 8. A step of forming an element isolation layer on a silicon substrate, growing a carbon-doped silicon layer and a silicon layer on the silicon substrate in this order, and forming a gate on the silicon layer via a gate insulating film. A method for manufacturing a semiconductor device, comprising: a step of forming an electrode; and a step of forming a source region and a drain region by ion implantation. 9. A step of removing an exposed surface of the silicon substrate by etching after forming an element isolation layer on the silicon substrate, and forming a carbon doped layer by ion-implanting carbon into the silicon substrate. A semiconductor having a step of growing a silicon layer, a step of forming a gate electrode on the silicon layer via a gate insulating film, and a step of forming source and drain regions by ion implantation Device manufacturing method. 10. The method for manufacturing a semiconductor device according to claim 6, wherein said silicon layer is a non-doped silicon layer. 11. The silicon layer has a thickness of 5 to 100 n.
The method of manufacturing a semiconductor device according to claim 6, wherein m is m. 12. The carbon doped layer has a thickness of 5 to 100.
12. The method of manufacturing a semiconductor device according to claim 6, wherein 13. The carbon-doped layer has a carbon concentration of 1 × 1
13. The method for manufacturing a semiconductor device according to claim 6, wherein the pressure is set to 0 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . 14. A silicon substrate having a carbon-doped layer at a position separated from the surface. 15. The carbon concentration of the carbon doped layer is 1 ×
15. The silicon substrate according to claim 14, wherein the thickness is 10 < ¹⁸ > to 1 * 10 < ²¹ > cm < ^-3 >. 16. The method according to claim 16, wherein the carbon-doped layer is 5 to
The silicon substrate according to claim 14, wherein the silicon substrate is provided at a position separated by 100 nm. 17. The thickness of the carbon-doped layer is 5 to 100.
The silicon substrate according to claim 14, wherein the thickness of the silicon substrate is nm.