JP2000029721A - Microcomputer - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To speed up a task execution switching process. SOLUTION: First control means (3) for storing register identification information indicating a register actually used among a plurality of registers in the storage means is provided, and based on the register identification information, first control means (3) is provided. Second control means (3) for saving the held information of the registered register in the stack area. Accordingly, it is possible to avoid wasting the information held in the registers that are not actually used among the plurality of registers in the stack area, thereby speeding up the task execution switching process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for performing a predetermined arithmetic processing by executing a series of instructions constituting a program, and is applied to, for example, a one-chip microcomputer (single-chip microcomputer). Regarding effective technology.

[0002]

2. Description of the Related Art A single-chip microcomputer includes a CPU (central processing unit) and necessary peripheral circuits contained in a single semiconductor substrate, and a program ROM (read-only memory) having an operation program for the semiconductor ROM. ) Built-in. On the other hand, a multichip microcomputer does not include a ROM for storing the operation program, and a necessary operation program is obtained from an external memory (ROM) arranged outside the multichip microcomputer. .

Switching of execution of a task in a multitask control OS (operating system) is to interrupt a task being executed and switch to execution of another task. The OS sets the environment of the task to be executed next after saving all the operating environments (registers and stack states) of the currently executed task when switching the execution of the task. The OS saves the entire operation environment of the task so that the execution may be switched at any timing.

[0004]

However, as described above, when the execution of a task is switched, the conventional method of saving all registers and the stack state as the task execution environment takes a long time to switch the task. Would. In particular, if the amount of information handled with the advancement of microcomputers increases, the time required for task switching must be reduced in order to save all registers and stack states as a task execution environment. It has been found that it greatly affects the processing time.

An object of the present invention is to speed up a task execution switching process.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

More specifically, a plurality of registers (PC, SR, SP, R0 to Rn) for holding information and a stack area (7) for saving the contents held by the plurality of registers.
And a storage means (RSR) for recording the identification information of the register actually used when the microcomputer is formed, and the identification information of the register actually used for each instruction execution. First control means (3) for writing to the means, and second control means (3) for saving the storage information of the storage means and the storage information of the register specified based on the storage information in the stack area. Are provided.

According to the above-mentioned means, the first control means stores register use information indicating a register actually used among the plurality of registers in the storage means, and the second control means makes the determination. Based on the information, the information held in the register actually used is saved in the stack area. This avoids wasteful saving of information held in registers that are not actually used among the plurality of registers in the stack area, and achieves high-speed task execution switching processing.

At this time, after the storage information of the storage means and the storage information of the register specified based on the storage information are saved in the stack area by the second control means, the storage means is initialized. The third control means (3) can be provided.

When the interrupted task is resumed, the storage state of the corresponding storage means and the storage state of the corresponding register are restored based on the register use information saved in the stack area and the held information of the plurality of registers. Control means (3) can be provided.

[0011]

FIG. 5 shows a configuration example of a single-chip microcomputer according to the present invention. The single-chip microcomputer 1 is formed on a single semiconductor substrate such as a single-crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique, although not particularly limited.

Single-chip microcomputer 1
Are a CPU (Central Processing Unit) 3, a ROM (Read Only Memory) 5, a RAM (Random Access Memory) 7, a timer 9, a serial communication interface (SCI) 11, an A / D converter 13, an interrupt controller 15, and first to ninth ports 21 to 29
And the like, which are connected to each other via an internal address bus 31 and an internal data bus 33 so that signals can be exchanged with each other.

The main storage devices of the single-chip microcomputer 1 are the RAM 7 and the ROM 5, and the RAM 7 is used as a work area of the CPU 3 or a temporary storage area of data. The ROM 5 holds an operation program of the CPU 3, although not particularly limited. Although not particularly limited, the ROM 5 is an EPROM (electrically programmable read only memory) in which information can be written from outside the microcomputer by an EPROM writer.

On the peripheral edge of the semiconductor substrate, for example, a large number of bonding pads are arranged as electrode pads. For example, bonding pads P10 to P17 coupled to the input / output terminals of the first to ninth ports 21 to 29,
P20 to P24, P30 to P37, P40 to P47, P
50 to P57, P60 to P63, P70 to P77, P8
0 to P87, P90 to P97, and a bonding pad XTA coupled to the input terminal of the clock generator 17.
L, EXTAL, etc. are arranged. An oscillator (not shown) is connected to the bonding pads XTAL and EXTAL, or an external clock is supplied.

In the assembling process, the single-chip microcomputer 1 configured as a chip or a pellet as described above is die-bonded to the mounting portion of the package, and is sealed after the bonding pads are wire-bonded to the lead terminals of the package. You.

Single-chip microcomputer 1
Interface with the outside through various ports. The port function can be specified by setting the operation mode, and the operation mode that outputs an address signal to the outside to access an external memory or a peripheral device is also supported.

FIG. 1 shows a configuration example of the CPU 3.

Reference numeral 109 denotes an instruction register. The instruction register 109 is connected to the internal bus 103 and holds an instruction code transmitted through the internal bus 103. At the subsequent stage of the instruction register 109, an instruction decoder 110 for decoding the instruction held by the instruction register 109 to decode the instruction is arranged. This instruction decode result is input to the control unit 111 arranged at the subsequent stage. The control unit 111 sends appropriate control signals to the inside and outside of the CPU 3 to
The required operation specified by the instruction decoded in 10 is
Perform in several steps.

Arithmetic Logic Unit (ALU) 107
Is a hardware unit for performing necessary numerical and logical operations on data. Numerical operations include addition, subtraction, multiplication, division, etc.
There is a logical product operation, which is executed based on a binary addition circuit. A flag flip-flop 106 for holding various states occurring during the operation is coupled to such an ALU 107. Further, a temporary register 105 for temporarily holding data for operation in the ALU 107 and various register groups 116 are coupled to the internal bus 103.

Although not particularly limited, the various register groups 116 include a program counter P which is a register for storing an address of an instruction to be executed next by the CPU 3.
C, a status register SR for storing a status of an instruction execution result, general-purpose registers R0 to Rn appropriately used for various arithmetic processes, a stack pointer SP as a register for indicating a task stack area, and
A register use information holding unit RSR for holding register use information indicating a register actually used is included. The task stack area is not particularly limited.
M7 is formed. This register use information holding unit RSR
The memory contents can be referred to and set by an instruction like other registers.

As shown in FIG. 2, the register use information holding unit RSR has a plurality of storage areas RSR1 to RSRn corresponding to the various registers in order to store the use status of the various registers.

Each time an instruction in the ROM 5 is fetched by the CPU 3, a register used by the instruction is obtained.
Immediately after the execution of the instruction, a flag is set in a storage area corresponding to a register used in the execution of the instruction. In other words, since the operands included in the instruction are addresses and numerical values that are symmetrical to the operation,
By checking this operand, the address of a register actually used in the execution of the instruction can be grasped, and information for determining the register is set in a later task stack. For example, when the general-purpose register Rn is used by the arithmetic processing, a flag of the logical value “1” is set by the control unit 111 in the storage area RSR4 corresponding to the general-purpose register Rn. It is said.

Next, the operation of the present embodiment will be described.

FIG. 3 shows a flowchart of the process when the task execution is interrupted.

In order for the OS to use the register use information for switching the execution of a task, at the start of execution of the task,
The contents stored in the register use information storage unit RSR are cleared (step S31).

It is assumed that processing 1 (instruction) of the task is executed and the general-purpose registers R1 and R2 are used in the processing 1. After execution of the instruction, the registers R1,
The flag of the register use information corresponding to R2 is
1 is set to the logical value "1" (step S3).
2).

When the execution of the task is interrupted, the OS is executed to save the operating environment at the time of the interruption of the task execution, and the control unit 111 is operated to acquire the flag of the register use information ( Step S33).

Then, the control unit 111 is operated by the OS, and the storage state of the minimum necessary registers is stored in the task stack area 39 formed in the RAM 7 (step S34). For example, among the general-purpose registers R0 to Rn,
Since it is clear from the register use information that the general-purpose registers R1 and R2 are used in the above process 1, the storage information of the general-purpose registers R1 and R2 is stored in the task stack area 39. Since the status register SR and the program counter PC are naturally used, they are also stored in the task stack area 39. Further, the execution of the task is interrupted, and the register use information is saved in the task stack area 39 as discrimination information of the saved register.

Then, since the execution of the task is suspended, the register use information of the task is cleared (step S35), and the task is prepared for processing of another task.

FIG. 4 shows a flowchart of a process at the time of resuming task execution.

At the time of resuming the execution of the previously interrupted task, the control unit 111 is operated by the execution of the OS, and the register use information saved at the time of the interruption is acquired from the task stack area 39 (step S41). Then, the contents stored in the register use information storage unit RSR are restored to the contents at the time of the interruption of the process (step S42). Then, register information corresponding to the recovered register use information flag is obtained, and the stored information of the registers R1 and R2, the program counter PC, and the status register SR is restored (step S42). By returning as such, the operating environment of the interrupted task is restored,
Execution of the task is resumed (step S43).

FIG. 6 shows a configuration example of a computer system to which the single-chip microcomputer 1 is applied.

This computer system has a bus BUS
Through the single-chip microcomputer 1, S
RAM (static random access memory)
133, a ROM (Read Only Memory) 134, a peripheral device control unit 135, a display control system 136, etc., are connected to each other so as to be able to exchange signals, and are configured as a computer system that performs predetermined data processing according to a predetermined program. Is done. The single-chip microcomputer 1 is the logical core of the present system. S
The RAM 133 and the ROM 134 are positioned as internal storage devices. And SDRAM 132 or SR
The AM 133 stores application programs and data necessary for calculation and control in the single-chip microcomputer 1. The peripheral device control unit 135 controls the operation of the external storage device 138 and the keyboard 139.
Information input control is performed. The display control system 136 controls information display on the CRT display 140.

According to the above example, the following functions and effects can be obtained.

(1) The control unit 111 includes a plurality of registers P
Of the C, SR, SP, and R0 to Rn, register use information indicating a register actually used is stored in the register use information storage unit RSR, and the control unit 111 uses the register use information based on the register use information. The held information of the registered register is saved in the stack area. For this reason, it is possible to avoid wasteful saving of the held information of the register that is not actually used among the plurality of registers to the stack area, so that the task execution switching process can be speeded up accordingly. .

(2) Because of the effect of the above (1), the speed of the task execution switching process can be increased.
, The speed of data processing in a computer system including a computer can be increased.

Although the invention made by the inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer with a built-in program ROM, which is the field of application, has been described, but the present invention is not limited to this. Instead, the present invention can be applied to a microcomputer that can be generally used without having the program ROM 5.

The present invention can be applied on condition that at least a plurality of registers for holding information are provided.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the first control means stores the register use information indicating the register actually used among the plurality of registers in the storage means, and the second control means stores the register use information based on the register use information. Saves the held information of the register used in the stack area. Accordingly, it is possible to avoid wasting the information held in the registers that are not actually used among the plurality of registers in the stack area, thereby speeding up the task execution switching process.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a CPU included in a microcomputer according to the present invention.

FIG. 2 is an explanatory diagram of a register use information storage unit included in the CPU.

FIG. 3 is a flowchart showing a process when the task execution is interrupted in the CPU.

FIG. 4 is a flowchart showing processing at the time of resuming task execution in the CPU.

FIG. 5 is a block diagram illustrating a configuration example of a single-chip microcomputer including the CPU.

FIG. 6 is a block diagram illustrating a configuration example of a computer system including the single-chip microcomputer.

[Explanation of symbols]

 3 CPU 39 Task stack area 104 Accumulator 105 Temporary register 106 Flag flip-flop 107 ALU 109 Instruction register 110 Instruction decoder 111 Control unit 116 Register group PC program counter SR Stack pointer R0-Rn General-purpose register SP Stack pointer RSR Register usage information storage unit

Claims (3)

[Claims] 1. A microcomputer including a plurality of registers for holding information and a stack area for saving contents held by the plurality of registers, wherein a register actually used among the plurality of registers is Storage means for recording the register use information shown, first control means for writing the register use information to the storage means each time an instruction is executed, and identification based on the storage information of the storage means and the storage information. And a second control unit for saving the storage information of the register to be stored in the stack area. 2. The information stored in the storage means and the storage information in a register specified based on the storage information are stored in the second storage unit.
2. The microcomputer according to claim 1, further comprising third control means for initializing said storage means after being evacuated to said stack area by control means. 3. When the interrupted task is restarted, the storage state of the corresponding storage means and the storage state of the corresponding register are respectively determined based on the register use information saved in the stack area and the held information of the plurality of registers. 3. The microcomputer according to claim 2, further comprising a fourth control unit for returning.