JP2000012809A - Non volatile semiconductor memory and electron pull out method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent hot holes implanted in gate insulating films from forming electron capture centers by avoiding a high electric field to be applied between a source and a p-well, when charges are pulled out of a floating gate. SOLUTION: An n-well 2 and a p-well 3 are formed on a p-type silicon substrate 1, and a memory cell having a floating gate 6, a control gate 8, a source region 9 and a drain region 10 are formed, on the p-well 3. Next, a p+-type region is formed on the p-well 3, and a p-type region 11 is connected to a power supply switch 14 which controls the connection/disconnection to and from a ground live. In order to implant charges in this memory cell, the p-well 3 is grounded, the source region 9 and the drain region 10 is respectively impressed with a ground potential and a power supply potential (e.g. 5V), and a control gate 8 is impressed with a positive high potential. When charges are pulled out, the p-well is turned into floating, then the source region 9 and the control gate 8 are respectively impressed with the power supply potential and a negative high potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device having a memory cell having a floating gate and a control gate, and a method for extracting electrons from the floating gate of the memory cell.

[0002]

2. Description of the Related Art A determination of a written state and an erased state of information in a memory cell of a semiconductor memory device of this kind is based on a change in threshold voltage of a memory cell transistor caused by the presence or absence of charges (electrons) stored in a floating gate. This is done by identifying. However, depending on the configuration of the memory operation, a state where charges are accumulated in the floating gate may be referred to as a write state, and a state where charges are not accumulated in the floating gate may be referred to as a write state. Therefore, in this specification, the term “drawing and injection of charges (child)” will be referred to without using the terms “writing” and “erasing”. In a non-volatile semiconductor storage device, transistors constituting a peripheral circuit are integrated on the same semiconductor substrate in addition to a memory cell.
Usually, the peripheral circuit is constituted by CMOS. FIG.
FIG. 11 is a cross-sectional view showing a conventional nonvolatile semiconductor memory device having a transistor for a peripheral circuit.

As shown in FIG. 6, on a p-type silicon substrate 101, a first p-well 103a for forming a memory cell and an n-well 102 for forming a p-channel MOS transistor of a peripheral circuit are provided. And n of the peripheral circuit
A second p-well 103b for forming a channel type MOS transistor is formed, and each well is separated by a separation insulating film 104. First p-well 103
A floating gate 106 is formed on a through a first gate insulating film 105, and a control gate 108 is formed on the floating gate 106 via a second gate insulating film 107.
A source region 109 and a drain region 110 are formed in the surface region of the p-well 103a on both sides of the stacked gate electrode. Further, a p ⁺ type region 111 is formed in the surface region of the first p well 103a,
P well 103a is grounded through this region.

An n-well 102 and a second p-well 103b
Gate electrodes 116 and 120 are respectively formed thereon via a gate insulating film 115, and source regions 117 and 121 are formed in the surface regions of the wells on both sides of each gate electrode.
Drain regions 118 and 122 are formed. An n ⁺ -type region 1 for fixing the potential of each well is provided in the surface regions of the n-well 102 and the second p-well 103b.
19, a p ⁺ type region 123 is formed, the n ⁺ type region 119 is connected to the _VDD power supply together with the source region 117, and the p ⁺ type region 123 is grounded together with the source region 121.

[0005] The injection / extraction and reading of charges from / to the memory cells of this nonvolatile semiconductor memory device are performed, for example, as follows. When injecting electric charges, for example, the source region 109 is grounded (0 V), a high voltage of 12 V is applied to the control gate 108, and a power supply voltage of 5 V is applied to the drain region 110.
V is applied for about 10 μsec. As a result, hot electrons are generated in the channel region, and the hot electrons are generated in the first gate insulating film 1 which is a tunnel oxide film.
05 is injected into the floating gate 106. On the other hand, reading is performed by, for example, grounding the source region 109, applying 5 V to the control gate 108, and applying approximately 1 V to the drain region 110, and detecting whether or not current flows through this memory cell. At the time of charge extraction, a high voltage of 0 V is applied to the control gate 108 and a high voltage of 10 V is applied to the source region 109, and the FN (Fowler) between the floating gate and the source region is applied.
-Nordheim) The electrons accumulated in the floating gate 106 are extracted to the source side through the first gate insulating film 105 by a tunnel phenomenon. At this time, a negative high voltage may be applied to the control gate 108. Further, instead of applying a high voltage to the source region, a high voltage may be applied to the drain region to extract electrons to the drain region side.

[0006]

As shown in FIG. 6, usually, a first p-well 10 in which a memory cell is formed is provided.
3a is not electrically separated from the second p-well 103b in which the n-channel MOS transistor of the peripheral circuit is formed. Usually, the second p-well in which the n-channel transistor forming the peripheral circuit is formed is grounded to guarantee the operation of the peripheral circuit. Therefore, the first p well in which the memory cell is formed is necessarily grounded. Hereinafter, the inconvenience of using this method will be described, taking as an example the case of extracting electrons to the source region side. When a high voltage of, for example, 10 V is applied to the source region as described above and the p-well is grounded, a depletion layer expands between the source region and the p-well, and a high electric field is applied between them. Electron-hole pairs are generated in the depletion layer. Electrons are extracted to the source region side and holes are extracted to the ground line, but the holes are accelerated by the electric field of the depletion layer and become hot carriers. Holes having higher energy than the energy barrier of the inner tunnel oxide film (first gate insulating film 105) of the holes are injected into the first gate insulating film 105 and create a defect called a charge trapping center. Part of the charge flowing through the first gate insulating film during charge injection and extraction operations is captured by the charge capture center. Therefore, there is a problem that the gate insulating film is charged and the injection and extraction characteristics (writing and erasing characteristics) fluctuate. In addition, a problem arises in that the electrons accumulated in the floating gate leak to the outside via the capture center, and the stored contents fluctuate.

In order to solve this problem, conventionally, the value of the negative voltage applied to the control gate at the time of extracting the electric charge is increased,
By reducing the voltage applied to the source by that amount, a method of reducing the electric field intensity in the depletion layer between the source and the substrate and suppressing the acceleration of the hole current is used. However, even by using such a method, injection of holes into the first gate insulating film cannot be eliminated at all. An object of the present invention is to solve the above-described problems of the conventional example, and an object of the present invention is to prevent holes from being generated as hot carriers, thereby preventing charge trapping in the tunnel oxide film. Is not to be formed.

[0008]

According to the present invention, there is provided, in accordance with the present invention, a first p-well in which a nonvolatile memory cell having a floating gate and a control gate is formed;
A second p-well in which an n-channel MOS transistor other than the memory cell is formed, is electrically isolated;
In addition, there is provided a nonvolatile semiconductor memory device characterized in that the first well is provided with a power supply switching means capable of switching the first p well between a floating state and a potential applied state. You.

According to the present invention, there is provided a method of extracting electrons from a floating gate of a nonvolatile memory cell having a floating gate and a control gate formed in a p-well, wherein the p-well is maintained in a floating state. In addition, there is provided an electron extraction method for a nonvolatile semiconductor memory device, wherein a positive voltage is applied to a source region and / or a drain region of a nonvolatile memory cell.

[0010]

In the present invention, the p-well in which the memory cell is formed is placed in a floating state when a positive voltage is applied to the source region (or the drain region) to extract electrons from the floating gate. Therefore, a high electric field is not applied to the depletion layer between the source region and the p-well, so that generation of electron-hole pairs due to the high electric field is eliminated, and injection of hot carriers into the gate insulating film is also eliminated. Therefore, it is possible to avoid generation of a trapping center due to injection of hot carriers into the gate insulating film, change in charge injection / extraction characteristics due to charging of the first gate insulating film, and leakage of charges from the floating gate. Of the threshold voltage can be suppressed.

[0011]

1 (a) to 1 (d) and FIG. 2 are cross-sectional views for explaining an embodiment of the present invention. In the nonvolatile semiconductor memory device of the present invention, for example, FIGS.
The well configuration shown in (d) is adopted. As shown in FIG. 1A, the p of the peripheral circuit is provided in the surface region of the p-type silicon substrate 1.
A first n-well 2a and a second n-well 2b for forming a channel type MOS transistor are formed, and a first n-well for forming a nonvolatile memory cell is formed in a surface region of the second n-well 2b. And a second p-well 3b for forming an n-channel MOS transistor of the peripheral circuit. Alternatively, as shown in FIG. 1B, an n-well 2 for forming a p-channel MOS transistor of a peripheral circuit is formed in a surface region of a p-type silicon substrate 1, and the surface region of the n-well 2 is formed. A first p-well 3a for forming a non-volatile memory cell is formed therein. Then, a second p-well 3 b for forming an n-channel MOS transistor of the peripheral circuit is formed in the surface region of the p-type silicon substrate 1.

Alternatively, as shown in FIG. 1C, a first n-well 2a for forming a p-channel MOS transistor of a peripheral circuit in a surface region of a p-type silicon substrate 1, and a peripheral circuit A second p-well 3b for forming an n-channel type MOS transistor and a second n-well 2b are formed, and in a surface region of the second n-well 2b,
First p-well 3 for forming a non-volatile memory cell
a is formed. Alternatively, as shown in FIG.
Well 2 for forming a p-channel MOS transistor of a peripheral circuit in a surface region of type silicon substrate 1a.
Then, a first p-well 3a for forming a non-volatile memory cell and a second p-well 3b for forming an n-channel MOS transistor of a peripheral circuit are formed.

As shown in FIG. 2, the nonvolatile memory cell of the present invention is formed on a p-well 3 formed in a surface region of an n-well formed in a surface region of a p-type silicon substrate 1, for example. Is done. Each well is isolated by an isolation insulating film 4. The isolation insulating film 4 can be formed by filling the inside of the trench with an insulator or by the LOCOS method. A floating gate 6 is formed on the p well 3 with a first gate insulating film 5 interposed therebetween.
A control gate 8 is formed thereon via a second gate insulating film 7.
Are formed. P on both sides of the stacked gate electrode
The source region 9 and the drain region 1 are formed in the surface region of the well 3.
0 is formed. A p ⁺ -type region 11 for applying a potential to the well is formed in the surface region of the p-well 3, and the p ⁺ -type region 11 can switch connection / disconnection to a ground line. It is connected to the power switch 14. The p-type silicon substrate 1 and the n-well 2 are grounded.

When charges are injected into the floating gate of this memory cell, a ground potential is applied to the p-well 3 via a power supply switch 14. Then, a ground potential is applied to the source region 9, a power supply voltage (for example, 5 V) is applied to the drain region 10, and a positive high voltage is applied to the control gate 8. As a result, hot electrons are generated in the channel and injected into the floating gate 6 via the first gate insulating film 5. In the memory cell into which the charge has been injected, the threshold voltage of the transistor increases. When reading is performed, a ground potential is applied to the source region 9, a positive low voltage is applied to the drain region 10, and a power supply voltage is applied to the control gate 8 while keeping the p-well at the ground potential. At this time,
A current flows in a transistor into which charge has not been injected, but does not flow in a cell into which charge has been injected.
When the electric charge is to be extracted, the power supply switch 14 is operated to the open state to bring the p-well 3 into a floating state. Then, a power supply voltage is applied to the source region 9 or the drain region 10 and a negative high voltage is applied to the control gate 8. The control gate may be floating or at ground potential. However, in this case, the voltage applied to the source or drain region is made high.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Will be explained. FIG. 3 shows a first embodiment of the present invention.
It is sectional drawing. As shown in FIG.
A second n-well 102b in a surface area of the plate 101;
Form p-channel MOS transistors for peripheral circuits
N well 102a for the
Second p-well for forming a multi-type MOS transistor.
Is formed to form a memory cell.
The first p-well 103a is a table of the second n-well 102b.
It is formed in the surface area. Separation insulating film 1 between each well
04. On the first p-well 103a
To the floating gate 10 via the first gate insulating film 105.
6 is formed thereon, and the second gate insulating film 1 is formed thereon.
The control gate 108 is formed via the reference numeral 07. That
Surface area of p-well 103a on both sides of stacked gate electrode
Source region 109 and drain region 110 are formed in the region
Have been. Also, the surface region of the first p-well 103a
Has p ⁺ A mold region 111 is formed, and p⁺ Mold area 1
11 is a power supply that can select between a grounded state and a released state.
It is connected to a source switch 114.

Gate electrodes 116 and 120 are formed on the first n-well 102a and the second p-well 103b with a gate insulating film 115 interposed therebetween, and are formed in the surface regions of the wells on both sides of each gate electrode. Is the source region 117,
121 and drain regions 118 and 122 are formed. The first n-well 102a, and n ⁺ region 119, p ⁺ -type region 123 for the surface area of the second p-well 103b for fixing the potential of each well is formed, n ⁺ -type region 119 Is V _DD together with the source region 117
The p ⁺ type region 123 is connected to a power supply,
And grounded. Also, the p-type silicon substrate 10
The first and second n-wells 102b are grounded via p ⁺ -type regions 113 and n ⁺ -type regions 112, respectively.

The charge injection / extraction and reading of the memory cells of the nonvolatile semiconductor memory device are performed, for example, as follows. When injecting electrons into the floating gate 106, the source region 109 is grounded (0 V), a high voltage of 10 V is applied to the control gate 108, and a power supply voltage of 5 V is applied to the drain region 110 for about 10 μsec. This allows
Hot electrons are generated in the channel region, and the hot electrons are injected into the floating gate 106 via the first gate insulating film 105 which is a tunnel oxide film. In a memory cell into which electrons have been injected, the threshold voltage of the transistor increases. On the other hand, in reading, the source region 109 is grounded, and 5 V is applied to the control gate 108 and about 1 V is applied to the drain region 110 to detect whether or not a current flows through this memory cell (under this bias condition, the charge is The current does not flow in the implanted memory cell, and the current flows in the non-implanted cell). At the time of charge extraction, -10 V is applied to the control gate 108 and 5 V is applied to the source region 109, so that FN (Fowler-Nord) between the floating gate and the source region is applied.
heim) The electrons accumulated in the floating gate 106 are drawn out to the source side through the first gate insulating film 105 by a tunnel phenomenon.

FIG. 4 is a graph for explaining the effect of the present invention in comparison with the conventional example. FIG. 4 is a graph showing the variation of the threshold value of the memory cell after charge injection and extraction are repeated. Is shown. The horizontal axis represents the number of repetitions, and the vertical axis represents the threshold value of the memory cell after electron injection and electron extraction into the floating gate. The two upper curves in the figure show the characteristics at the time of electron injection, and the lower two curves show the characteristics at the time of electron extraction. The black circles in the figure indicate the case where the electron injection and extraction were performed on the memory cell shown in FIG. 3 under the conditions in the embodiment, and the squares indicate the case of the conventional example. The driving conditions of the conventional example are the same as those of the embodiment except that the p-well is grounded at the time of extracting the electric charge.

According to the conventional method, as the number of repetitions increases, the threshold voltage at the time of electron injection decreases, the threshold voltage at the time of electron extraction increases, and the threshold voltage at the time of charge injection and the charge extraction. The difference from the threshold voltage at the time is small, and the margin for identifying the two states is reduced. This is because, as the number of times of rewriting increases, electrons are trapped in the charge trapping centers formed in the first gate insulating film during electron extraction, so that it becomes difficult for the electrons to tunnel through the first gate insulating film, and the same bias condition is applied. This is because the amount of electrons pulled out by the above or the amount of electrons that can be injected under the same bias condition decreases. In a real device, injection,
The threshold voltage is monitored during the pull-out operation. If the threshold voltage does not reach a desired value, the bias application time is increased, so that the two-state identification margin does not decrease.
The injection and withdrawal time increases and the operation slows down. on the other hand,
When the charge extraction method of the present invention is used, the threshold voltage hardly changes even when the number of repetitions increases.

[Second Embodiment] FIG. 5 is a sectional view showing a second embodiment of the present invention. In the figure, parts that are the same as the parts of the first embodiment shown in FIG. 3 are given the same reference numerals, and duplicate descriptions are omitted. In this embodiment, a first p-well 103a for forming a memory cell and a p-channel MOS transistor of a peripheral circuit are formed on a common n-well 102.
For the nonvolatile semiconductor memory device configured as described above,
The same result was obtained by performing charge injection / extraction under the same conditions as in the first embodiment.

[0021]

As described above, the present invention provides a first p-well for forming a memory cell and a second p-well for forming an n-channel MOS transistor of a peripheral circuit.
Since the first p-well is in a floating state when the charge is extracted from the floating gate of the memory cell by electrically separating the well from the well, the depletion between the source region (or the drain region) and the p-well when the charge is extracted. Application of a high electric field to the layer can be avoided, and deterioration of the gate insulating film due to injection of hot holes generated by application of the high electric field into the first gate insulating film (tunnel oxide film) can be prevented. be able to. Therefore, according to the present invention, it is possible to suppress a change in threshold voltage caused by repeated writing / erasing, and to provide a memory cell that operates stably for a long time.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a well for describing an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 3 is a sectional view showing a first embodiment of the present invention.

FIG. 4 is a characteristic curve diagram for explaining the effect of the present invention.

FIG. 5 is a sectional view showing a second embodiment of the present invention.

FIG. 6 is a sectional view of a conventional example.

[Explanation of symbols]

Reference Signs List 1 p-type silicon substrate 1a n-type silicon substrate 2 n-well 3 p-well 4 isolation insulating film 5 first gate insulating film 6 floating gate 7 second gate insulating film 8 control gate 9 source region 10 drain region 11, 13 p ⁺ Type region 12 n ⁺ type region 14 power switch 101 p-type silicon substrate 102 n-well 102 a first n-well 102 b second n-well 103 a first p-well 103 b second p-well 104 isolation insulating film 105 1 gate insulating film 106 floating gate 107 second gate insulating film 108 control gate 109, 117, 121 source region 110, 118, 122 drain region 111, 113, 123 p ⁺ region 112, 119 n ⁺ region 114 power supply Changeover switch 115 Gate insulating film 116, 120 Gate electrode

Claims (5)

[Claims] 1. A first p-well in which a nonvolatile memory cell having a floating gate and a control gate is formed, and a second p-well in which an n-channel MOS transistor other than the memory cell is formed. , And
The non-volatile semiconductor memory device according to claim 1, wherein the first well is provided with power supply switching means capable of switching the first p-well between a floating state and a potential applied state. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said first p-well is formed in an n-well. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said second p-well is also formed in said n-well. 4. A method for extracting electrons from a floating gate of a nonvolatile memory cell having a floating gate and a control gate formed in a p-well, the method comprising: Source area and / or
Alternatively, a positive voltage is applied to the drain region, wherein the method for extracting electrons from the nonvolatile semiconductor memory device is performed. 5. The method according to claim 4, wherein a negative or zero voltage is applied to the control gate or the control gate is in a floating state.