JP2000011692A - Memory testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a memory testing apparatus which reduces the number of a plurality of pattern generators required to give a start address (a fundamental address) and a burst address to a fail memory when double-data-rate(DDR) memory is tested. SOLUTION: When a memory 6 to be tested is operated in a burst mode, an address generation part 3d which computes all burst addresses by using a start address to be input from a pattern generator 2 is installed inside a fail analysis memory 3. For example, the address generation part 3d is installed at every memory block 3-i in the fail analysis part 3. When the memory 6 to be tested is operated in the DDR mode, even-numbered addresses A0, A2, A4,... which are changed by every test cycle by the pattern generator 2 are input to the address generation part 3d. The address generation part 3d in every memory block computes odd-numbered addresses A1, A3, A5,... as required from an input address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory test device.

[0002]

2. Description of the Related Art FIG. 8 shows a basic configuration of an entire conventional memory test apparatus. The memory test device is a timing generator 1, a pattern generator 2, a failure analysis memory (fail memory)
3, a waveform shaper 4 and a logic comparator 5 for testing a memory under test (MUT) 6.

In accordance with a reference clock CLK generated by a timing generator 1, a pattern generator 2 supplies an address signal A, a test data signal D, and a control signal C to a memory under test 6.
Output TL. These signals are applied to a waveform shaper 4, where they are shaped into a waveform required for a test and applied to a memory under test 6. In the memory under test 6, the control signal CTL
Thus, writing and reading of the test data D are controlled. The test data D read from the memory under test 6 is given to the logical comparator 5, where it is compared with the expected value data EXP output from the pattern generator 2, and its coincidence is determined.
The quality of the memory under test 6 is determined based on the mismatch. If they do not match, the failure information F is stored in the failure analysis memory 3.

A conventional failure analysis memory 3 shown in FIG. 9 is accessed from a pattern generator 2 by an address signal A, and an address selection section 3a can arbitrarily select an address signal A. The lower address Ab is sent to the memory 3c.
Supplied to The memory control unit 3b receives the upper address Aa from the address selection unit 3a,
, A write signal W is supplied to the memory unit 3c. The memory unit 3c stores the lower address Ab
Fail information F is stored in the cell No.

The failure analysis memory 3 is composed of the above-mentioned address selection section 3a, memory control section 3b and memory section 3c. The number of memory blocks 3-1 to 3-n is substantially equal to the number of simultaneously measured memory test devices. You. After the test, the address of the fail cell in the memory under test 6 can be detected by checking the address of the fail data F stored in the failure analysis memory 3.

Conventional FPM (Fast Page Mode), E
DRAM represented by DO (Extend Data Out) is shown in FIG.
The two types of clocks RAS (Row Address St
The read / write timing is controlled by a robe (giving a timing to fetch a row address) and a CAS (Column Address Strobe; giving a timing to fetch a column address). These DRAMs are used as a main memory of a computer system, and have a function called a page mode (called a hyper page mode in EDO) in order to improve a data transfer speed to a CPU. By inputting an address, data for one row (row) can be output at high speed.

However, SDRAM (synchronous DRA)
In a DRAM represented by M), timing control is performed by one type of clock CLK as shown in FIG. In the conventional SDRAM, read / write control is performed in synchronization with the rising edge of the clock CLK.
There is a function similar to the page mode described above called a burst mode. In the burst mode, a row (row) address and a column (column) address are input only once to the SDRAM, and thereafter, an address is generated internally without inputting a column (column) address (this is called a burst address). , Data can be continuously output in synchronization with the rising edge of the clock. As a result, the SDRAM becomes F
Data can be output at a higher speed than the PM and EDO DRAMs. FIG. 11 shows a case where the latency (the number of output delay cycles) with respect to the clock CAS is 3.

In the burst mode, data is output in synchronization with the rising edge of the clock. Recently, as shown in FIG. 12, data is output in synchronization with both the rising edge and the falling edge of the clock. There is a DDR (Double Data Rate) memory to output. DDR-SDRAM and Rumbus D are typical memories.
There are RAM, SLDRAM, etc., and the data transfer speed is twice as high as that of the memory synchronized only with the rising edge without increasing the frequency of the synchronized clock.

[0009]

SUMMARY OF THE INVENTION A DDR (Double Data)
Rate) To perform a high-speed burst read test of the memory,
The test apparatus may be operated at the same cycle as the DDR, but if the entire test apparatus does not operate at high speed, a method as shown in FIGS. 13 and 14 is employed. As a simple example, a case where the test apparatus is operated at twice the period of DDR is shown.

In this case, two strobes (strb1, strb2) are prepared in the operation cycle of the test apparatus, and two output data Q from the memory 6 under test are prepared in the operation cycle of the test apparatus.
0 and Q1 are two strobe points (strb1, strb
In step 2), the comparison is made. To store the strb1 fail and strb2 fail generated by this, 2
Two failure analysis memory blocks 3-1 and 3-2 are required. In this case, two failure analysis memory blocks 3-
Since the address values of strb1 fail and strb2 fail taken into 1, 3-2 are different, two pattern generators 2-
The addresses A-1 and A-2 must be provided to the failure analysis memory blocks 3-1 and 3-2.

Therefore, when testing a DDR memory device that is many times faster than the operating frequency of the test apparatus, the memory block of the memory block of the failure analysis memory 3 is used only for the address (corresponding to the burst address described above). The same number of pattern generators 2 are required. But,
The address A and the data D given to the memory under test 6 can be generated from one pattern generator. Therefore, the cost of the test apparatus increases, and the address generation is performed by a plurality of pattern generators, so that the control of the pattern generators becomes difficult.

A memory test apparatus having a plurality of pattern generators can store fail data in a DDR memory test. However, a memory test apparatus having a plurality of pattern generators can store a fail data in a DDR memory test. If the number of pattern generators is small, storage is not possible. This invention is a DDR
(Double Data Rate) DDR-SD represented by memory
It is an object of the present invention to reduce the number of a plurality of pattern generators conventionally required in a high-speed burst read test of a RAM or a Rumbus DRAM.

[0013]

According to a first aspect of the present invention, a test pattern signal is supplied from a pattern generator to a memory under test in synchronization with a clock of a timing generator, and a response output of the memory under test and The expected value pattern output from the pattern generator is compared with the logic comparator at the timing of the strobe signal of the timing generator, and when a mismatch is detected, the fail memory is replaced with the same address as the address of the memory under test where the mismatch occurred. The present invention relates to a memory test device for writing fail data.

In the present invention, when the memory under test operates in the burst mode, an address generator for calculating all burst addresses using a start address (also referred to as a basic address) input from a pattern generator is provided. This is provided in the fail memory. (2) In the second aspect of the present invention, in the above (1), the address generator is provided for each memory block of the fail memory.

(3) In the invention according to claim 3, in the above (1), when the memory under test operates in the double data rate (DDR) mode, an even-numbered address that changes every test cycle from the pattern generator. A0, A2, A4, ...
Is input to the address generation unit, and the address generation unit calculates odd-numbered addresses A1, A2, A3,... From the input address.

(4) In the invention according to claim 4, in (1), the address generator comprises a row (row) address generator and a column (column) address generator, and the row address generator and the column address are generated. The generator includes an offset register that stores an offset value, and an adder that adds an output of the offset register and a start address input from the pattern generator.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to solve the drawbacks of the prior art, a burst address given to a failure analysis memory is not generated by a pattern generator but is generated in a failure analysis memory from a start address from one pattern generator. To solve it. This example is shown in FIG. The generation of the burst address in the memory under test 6 is basically as shown in FIG. 2, and the address is added (subtracted) every test cycle DDR using the start address A0 applied to the memory under test 6 as a basic address. To go. The example of FIG. 2 shows a case where the operation cycle T of the test apparatus is twice as long as DDR. The generation of the burst address in the fail memory 3 is performed by the pattern generator 2.
This is performed by adding (subtracting) an arbitrary offset value to the start address (base address) from. First,
A0, A2, A4, and A6, which are addresses in the first cycle of DDR (this is a basic address), are generated by the pattern generator 2. Where A0, A2, A4, A
6 is input to the failure analysis memory 3, but since the memory block 3-1 that takes in the failure of strb1 uses this address as it is, the added value is "# 0". #
Means hexadecimal. The memory block 3-2 that takes in the failure of strb2 stores the address values A0, A2, A
The address generator 3d adds "# 1" to the addresses 4, A6 to generate burst addresses A1, A3, A5, A7, and fetches fail data using the burst addresses.

FIG. 3 shows details of the address generator 3d. The address generator 3d includes an adder 11, an offset register 12 storing an offset value at the time of address addition from the pattern generator 2, execution of offset addition (when data # 1 is stored), and non-execution (when data # 0 is stored). Addition register 13, which stores the value of “when stored”, R / W Mode
The OR gate 14 which takes the logical sum of the signal and the output from the addition execution register 13 makes the addition value the data in the offset register 12 according to the output from the OR gate 14 (when the output of the OR gate 14 is “# 0”) or the data “ # 0 "
(When the output of the OR gate 14 is “# 1”).

The offset register 12 can be set separately for each memory block 3-i in the failure analysis memory 3 and corresponds to a fail (strb1 fail, strb2 fail, etc.) taken in each memory block 3-i. Set each lever value. For example, in the above example, block 3-
In step 3, # 0 is set, and in block 3-2, # 1 is set. The R / W Mode signal reads the failure analysis memory 3 from the system controller 7 which controls the memory test apparatus.
It becomes "H" when writing, so that address offset addition is not performed. The address from the pattern generator 2 is a row address applied to the MUT (DRAM) 6 (referred to as an X address in the pattern generator 2).
And two addresses of column addresses (referred to as Y addresses in the pattern generator 2) are input to the failure analysis memory 3, so that the circuits 3d1 and 3d2 prepare X and Y addresses.

FIG. 4 shows the inside of the adder 11. FIG. 4 shows a case where the addition bit is 4 bits. The adder 11 controls the number of bits to be added by the 1-bit full adder FA and the bits to be added (that is, controls the carry output of each full adder), the carry output of each full adder, and the output of the carry control register. (The number of bits to be added minus one), and the output of the AND is connected to the carry input of each full adder for adding the upper bits. The bit for performing the address addition is controlled by the carry control register. A method of using the bit will be described with reference to the following example.

A burst address is generated based on the value of the offset register 12. In the present invention, since only the burst address of +1 is indicated, another generation method will be described. M
In a multi-bank DRAM of an interleaved configuration represented by a DRAM or the like, when performing a burst read between banks, the burst address becomes a bank address and a burst address at which an upper address is switched. In FIG. 5, the 21st to 23rd bits of the address are the bank address. In this case, the offset value of +1 can be dealt with by making the address value the same as the bank address (# 10000, "#" indicates hexadecimal notation).
Also, burst transfer like the interleave mode of the SDRAM (in FIG. 6, when the number of data to be read continuously (called the burst length) is 8, only the lower 3 bits of the address value are shown).
In some cases, the address value may be -1. In this case, the burst address value is represented by a complement (in FIG. 6, "#
The value (# 7) of the logical product of "# 7" is set to the inverted data of "1", and the carry control register C
Data # 3 is set in R. As a result, since the carry does not increase in the upper bits, only the lower 3 bits are added, and when # 7 is added to data # 7, the addition result becomes # 6, and a burst address as shown in FIG. 6 can be generated.

FIG. 7 shows an example of fail storage when the present invention is implemented. Fail from the above example (“# 0” in FIG. 7)
Indicates an address that is a pass, and “# 1” indicates an address that is a fail). In FIG. 7, the memory block 3-1 is stored at an even address, and the block 3-2 is stored at an odd address. This is indicated by underlining the address. When fail data is read to the tester controller at the end of the test, correct fail data can be read by reading the data of these two blocks by OR.

As described above, generating a burst address in the failure analysis memory 3 eliminates the need for a plurality of pattern generators 2 and can solve the conventional disadvantage.
1 and 2, A0, A2,... Are used as start addresses (basic addresses) from the pattern generator 2.
A6 is given to the fail memory 3 and the burst addresses A1, A3,... A7 are calculated in the fail memory 3, but the DDR-CDRAM (MUT
Similarly to the address given to 6), only the start address A0 is given from the pattern generator 2 to the fail memory 3,
If the fail memory 3 has burst addresses A1, A2, A
3,... A7 may be sequentially calculated.

[0024]

According to the present invention, the address generator 3d for generating a burst address based on the start address of the pattern generator 2 is provided in the fail memory 3.
It is not necessary to provide a plurality of pattern generators 2 as in the prior art, and the apparatus can be made more economical.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of a main part of FIG. 1;

FIG. 3 is a circuit diagram of an address generator 3d of FIG. 1;

FIG. 4 is a circuit diagram of an adder 11 shown in FIG. 3;

FIG. 5 is a diagram showing an example of burst reading of an MDRAM.

FIG. 6 is a diagram showing an example of burst reading in the interleave mode of the SDRAM.

FIG. 7 is a diagram showing an example of fail storage in the fail memory of FIG. 1;

FIG. 8 is a block diagram of a conventional memory test device.

FIG. 9 is a block diagram showing a configuration of the failure analysis memory 3 of FIG. 8;

FIG. 10 is a view showing read timing in a hyper page mode of the EDO DRAM.

FIG. 11 is a diagram showing a read timing in a burst mode of the SDRAM.

FIG. 12 is a diagram showing a read timing in a burst mode of the DDR-SDRAM.

FIG. 13 is a block diagram of a conventional apparatus for testing a DDR memory.

FIG. 14 is a timing chart of a main part of FIG. 13;

Claims (4)

[Claims] 1. A test pattern signal is supplied from a pattern generator to a memory under test in synchronization with a clock of a timing generator, and a response output of the memory under test and an expected value pattern output from the pattern generator are calculated. At the timing of the strobe signal of the timing generator, when a comparison is made by a logical comparator and a mismatch is detected, a fail test is performed in a memory test apparatus that writes fail data at the same address as the address of the memory under test where the mismatch occurred. When the memory operates in the burst mode, an address generator for calculating all burst addresses using a start address (also referred to as a basic address) input from the pattern generator is provided in the fail memory. Memory test equipment. 2. The memory test apparatus according to claim 1, wherein the address generator is provided for each memory block of the fail memory. 3. The method of claim 1, wherein the memory under test operates in a double data rate (DDR) mode.
The even numbered addresses A0, A2, A4,... Which change every test cycle from the pattern generator are input to the address generation section, and the address generation section has odd numbered addresses A1, A2, A3. A memory test apparatus, wherein: 4. The apparatus according to claim 1, wherein said address generator comprises a row (row) address generator and a column (column) address generator, and said row address generator and said column address generator respectively store offset values. A memory test apparatus, comprising: an offset register for performing the operation; and an adder for adding an output of the offset register and a start address input from the pattern generator.