JP2000078475A - Image pickup device and image pickup system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the numbers of temporary storage capacitors, stages of shift registers, common circuits, AGCs, and A/C converters by connecting a holding means shared by each photoelectric conversion part in a unit cell with a vertical output line and reading signals from the photoelectric conversion part to a signal holding means via the common circuit. SOLUTION: A signal storage structuring part 100 is provided with a capacitor Cs for storing the signal and a capacitor Cn for storing the noise, etc. The capacitor Cs for storing the signal and the capacitor Cn for storing the noise are provided to one vertical output line in parallel via transistors M1, M2. The signal stored in the capacitor Cs and the noise stored in the capacitor Cn are read on each horizontal output line by simultaneously turning transistors M3, M4 on by a horizontal shift register 13, and the signal is converted into a digital signal by removing the noise from it by a subtraction amplifier 10. Two kinds of capacitor Cn, Cs are provided per one vertical output line, two trains of photoelectric conversion signals are outputted by one vertical output line by a common amplifier and one capacitor is arranged per one train of photoelectric conversion parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus and an image pickup system using the same, and more particularly, to at least a plurality of photoelectric conversion units arranged in a row direction and signals from the plurality of photoelectric conversion units being input. The present invention relates to an imaging device in which unit cells each including a common circuit are arranged in a plurality of columns or an imaging device in which a plurality of photoelectric conversion pixels are arranged in a row direction and a column direction, and an imaging system using the same.

[0002]

2. Description of the Related Art As one of amplification type sensors, there is a CMOS area sensor in which an amplification amplifier composed of a CMOS circuit is provided in one pixel.

The CMOS area sensor is capable of random access to the CCD area sensor, and is superior in multifunctionality and low power consumption.

That is, since the CCD area sensor sequentially outputs photoelectrically converted signals and outputs the signals to the outside, random access is difficult and power consumption is large. However, the CMOS area sensor selects an arbitrary pixel. Therefore, the power consumption is low, the noise is low in mounting, and the mounting is easy.

[0005]

In the CMOS area sensor described above, when the characteristics of the pixel amplifier vary, it is required to add a memory to correct the variation. However, if a memory is provided for each pixel, there is a problem that the mounting area of the memory increases and the cost increases. Hereinafter, an example of an imaging device having a memory for correcting variations will be described. Variations in the characteristics of the pixel amplifier can be suppressed by reading a noise signal from the pixel and making a difference from the pixel signal.

FIGS. 17 to 19 are schematic circuit diagrams showing one example of a variation correction circuit of a conventional imaging apparatus. The configuration shown in FIG.
9 is disclosed, and the configuration shown in FIG. 19 is disclosed in JP-A-9-247546.

In FIG. 17, R1 pixel, G1 pixel, G2
The signal corresponding to the pixel, the signal corresponding to the B2 pixel, and the noise are read out to the capacitors C _S and C _N provided for each pixel. That is, eight capacitors for temporarily storing signals and noise are provided. R1 pixel, G2 pixel (G1 pixel, B2 pixel)
, And a noise signal are simultaneously read out and subjected to difference processing, and are subjected to AGC and analog-to-digital conversion by an A / D converter to become digital signals.

In FIG. 18, the difference between the noise and the signal is processed by the capacitance C _p and the reset means connected to the electrode of the capacitance C _p , and the signal R from which the noise has been removed is supplied to the capacitance C 1.
(G), the signal G from which noise has been removed
(B) is temporarily stored. To difference noise, and outputs the input electrode of the capacitor C _p in a state where the output electrode of the capacitor C _p noise and constant potential, an output electrode of the capacitor C _p after a floating state, capacitance C Input a signal to the input electrode side of _p . This way an input electrode of the capacitor C _p (signal - noise) component voltage is varied, also the output electrode of the capacitor C _p (signal - noise) because partial potential varies, noise canceled signal output Will be done. The R and G dot sequential signals and the G and B dot sequential signals are output to the horizontal output line every horizontal scanning. The signal is passed through a subtraction amplifier and AGC to A / D
The analog-to-digital conversion is performed by the converter to produce a digital signal. This digital signal is stored for each primary color signal in a plurality of line memories or frame memories, and image processing is performed. The memory method varies depending on the system.

[0009] In FIG. 19, the noise and the signal read out from each of the vertical output lines, for storing in the temporary storage capacitor C _S to remove noise from the signal. To remove the noise, after on-reset transistor Mt, the Mr, transfers the charge exceeding the channel potential φn of the transistor M _S by applying a negative pulse to the capacitor C _P noise output period to the capacitor C _S This charge is discharged by turning on the transistor Mt. Signal output period again, the channel potential of the transistor M _S by applying a negative pulse to the capacitor C _P .phi.s
Is transferred to the capacitor C _S. Here, the charge transferred to the capacitor C _S becomes C _P × (φs−φn), and becomes a signal from which noise has been removed.

In these imaging apparatuses, one pixel row (1
(At least two vertical output lines).
The value of the capacitance to be added is determined by the thickness of the dielectric layer and the area of the electrodes, but usually occupies several tens of percent of the chip area.

In particular, in the configuration example of FIG. 17, an amplifier for performing a difference process between noise and a signal is required for each pixel, and power consumption is increased. Further, if signals are read from a plurality of horizontal lines simultaneously to reduce the reading speed, the temporary storage capacity further increases, which leads to an increase in chip area.

In recent years, the power consumption has increased due to the increase in the number of pixels of a digital still camera to several million pixels, the number of shots has decreased, and the user has to bear a high battery cost.

[0013] Further, after the year 2000, the IMT-2000 infrastructure capable of high-speed data communication is prepared, and image communication becomes full-scale. In order to spread such mobile image communication, low power consumption sensors, peripheral ICs, and cost reduction are required.

[0014]

According to the present invention, there is provided an imaging apparatus comprising: a unit cell having at least a plurality of photoelectric conversion units arranged in a row direction and a common circuit to which signals from the plurality of photoelectric conversion units are input; In an imaging device in which a plurality of columns are arranged, a signal holding unit shared for each photoelectric conversion unit in the unit cell is connected to a vertical output line, and from the photoelectric conversion unit to the signal holding unit via the common circuit. It is characterized by reading a signal.

Further, in the image pickup apparatus of the present invention, a plurality of photoelectric conversion pixels are arranged in a row direction and a column direction, and signal holding means shared for at least two photoelectric conversion pixel columns is connected to a vertical output line. The holding unit includes an image signal holding unit that stores an image signal, and a noise holding unit that stores a noise component of the image signal, and reads a signal from each photoelectric conversion pixel to the signal holding unit, and reads the signal from the signal holding unit. The signal output operation is sequentially performed for each photoelectric conversion pixel in the column direction and the row direction of the at least two photoelectric conversion pixel columns.

An image pickup system according to the present invention includes the above image pickup apparatus according to the present invention, a lens for forming an image on the image pickup apparatus, and a signal processing circuit for processing an output signal from the image pickup apparatus. Is what you do.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment in which the present invention is applied to an image pickup apparatus which reads out signals from four photoelectric conversion units via one common amplifier (constituting a common circuit).

The photoelectric conversion cell (unit cell) S of this embodiment
Is composed of four photoelectric conversion units and one common amplifier. For example, the photoelectric conversion units a11, a12, a21, and a22 in FIG. 1 include color filters R1 (red), G1 (green), G2 (green),
B2 (blue) is provided, and the R1 signal, G1
The signal, the B2 signal, and the G2 signal are output from the common amplifier A1 via the vertical output line. The noise after reset is also output from the common amplifier A1 via the vertical output line.

Reference numeral 100 denotes a capacitor C _S for storing a signal, a capacitor C _N for storing a noise, and transistors M 1 and M M for switching a capacity.
2, and a signal storage component composed of signal output transistors M3 and M4. One vertical output line is provided with a signal storage capacitor _CS and a noise storage capacitor _CN in parallel via transistors M1 and M2. The signals stored in the capacitor C _S and the noise stored in the capacitor C _N are read out to the respective horizontal output lines by simultaneously turning on the transistors M 3 and M 4 controlled by the horizontal shift register (H · SR) 13. , The noise is removed from the signal by the subtraction amplifier 10, the AGC (auto gain control) 11, the A / D
The signal is converted into a digital signal via the converter 12. The horizontal output line is reset by a transistor M6 controlled by φHC.

In this embodiment, two capacitors are provided for one vertical output line. However, since signals of two columns of photoelectric conversion units are output by one vertical output line by a common amplifier, one capacitor is provided.
One capacitor may be arranged for each row of photoelectric conversion units.

FIG. 2 is a diagram showing the structure of the photoelectric conversion cell S. As shown in FIG. 2, the photoelectric conversion cell S includes four photoelectric conversion units (here, a ₁₁ , a ₁₂ , a ₂₁ ,
a ₂₂ ). Other photoelectric conversion cells have the same configuration. In this case, the common amplifier includes an amplifying unit MSF, a reset unit MRES, a selecting unit MSEL, and transfer units MTX1 to MTX4. The transfer means MTX1 to MTX4 control signals φGT1 to
φGT4 sequentially turns on, the photoelectric conversion units a ₁₁ , a ₁₂ ,
Signals are sequentially transferred from a ₂₁ and a ₂₂ to the input section (gate) of the amplification means MSF. When the selection means MSEL is turned on by the selection signal φSO, a signal corresponding to the signal charge transferred to the gate of the amplification means MSF is read out to the vertical output line. The signal from the photoelectric conversion unit is amplified by the amplification means MSF.
Reset signal φGC before being transferred to the input section (gate) of
The reset means MRES is turned on by L and the amplifying means M
The input section of SF is reset and sent as noise to the vertical output line via the selection means MSEL.

FIG. 3 is a timing chart for explaining the operation of the imaging apparatus. The reading of each color signal is sequentially performed in a time-division manner during one horizontal scanning period (R1 reading (period φR) → G1 reading (period φG) → B2 reading (period φB).
→ G2 reading (period φG ')), after reading the color signal,
Signals and noise are output from the temporary storage capacitors C _S and C _N.
The noise is removed from the signal by the subtraction amplifier 10 and the AGC 1
1. The signal is converted into a digital signal via the A / D converter 12, and the R1, G1, B1, and G2 signals are output (signal output out1).

In this embodiment, the output signal is a color line sequential signal. The digital signal after the A / D conversion is temporarily stored in a memory at a subsequent stage and image processing is performed. The noise removal method is not limited to the present embodiment, but may be a clamp type shown in FIG.
Various types such as the slice type shown in FIG. 9 can be applied.

FIG. 4 is a timing chart showing the timing within each color signal readout period.

In the R1 read period shown in FIG. 4, in the period T1, the signals .phi.TS, .phi.TN, and .phi.VL are set to the high level, the transistors M1, M2, and M5 are turned on, and the residual on the vertical output lines and the temporary storage capacitors CS and CN The charge is removed.

Next, in a period T2, the signals φGCL, φSO, φ
TN is set to a high level, the reset means MRES is turned on, and the common amplifier is reset.
L, the transistor M2 is turned on to read out the noise of the common amplifier and store the noise in the temporary storage capacitor CN.

Next, in the period T3, the signals φGT, φSO, φT
S is set to a high level, the transfer means MTX1 is turned on, a signal is transferred from the photoelectric conversion unit to the input unit (gate) of the common amplifier, the selection means MSEL and the transistor M1 are turned on, and the photoelectric conversion signal is read and temporarily stored. Capacity CS
The photoelectric conversion signal accumulation is performed. The same processing is performed in the G1, B2, and G2 read periods.

FIG. 5 shows an overall configuration diagram of the above-mentioned imaging apparatus.

Reset of each photoelectric conversion cell, readout of noise / signal, and control of photoelectric conversion are performed by vertical shift registers (V.
SR) 15 and control of the noise elimination / memory unit 14 composed of the signal accumulation / configuration unit 100 is performed by the horizontal shift register (H / SR) 13 and the subtraction amplifier 10
Then, the noise is removed from the signal, and the signal is converted into a digital signal via the AGC 11 and the A / D converter 12. The timing generator 16 is a vertical shift register (V / SR)
15, the operation of the horizontal shift register (H-SR) 13, the differential amplifier 10, the AGC 11, and the A / D converter 12 is controlled. Reference numeral 17 denotes an image sensor unit in which photoelectric conversion cells are arranged in a matrix.

Although the embodiment shown in FIG. 1 employs a method of dividing and reading out a unit cell of two rows and four pixels and outputting a signal, it is needless to say that a plurality of rows and a plurality of pixels may be further increased.

In the above embodiment, the common circuit portion A
1, A2,... Have been described as amplifiers.
Other signal processing circuits such as a D conversion circuit and a compression circuit may be used.

FIG. 6 is a schematic configuration diagram showing an embodiment of an image pickup apparatus when a single cell is constituted by one photoelectric conversion unit and one amplifier. FIG. 7 is a diagram showing a cell configuration.

In the case of this embodiment, the transfer switch means MTX
Are provided for each of the odd-numbered columns and the even-numbered columns, and the signals φGT1, φG
Control with T2. The noise read from the pixel R1 turns on the transistors M7 and M2 and is stored in the capacitor CN.
The image signal read out from is turned on and the transistors M7 and M1 are turned on and stored in the capacitor CS. Then, the signals are output from the capacitors CN and CS to the horizontal output line. Thereafter, the other pixels (G
1, G2, B2) and the image signal read out from the capacitors CN and CS are output to horizontal output lines.

The noise memory becomes unnecessary if the application where the noise of the amplifier can be ignored or the process technology is improved. In this case, the control line of the transfer switch MTX may not be provided separately for the odd columns and the even columns, and may be a common line. The pixel signal is read out to the vertical output line by φGT and temporarily stored. The transfer to the capacitor CS serving as the signal memory is controlled by φVT1 and φVT2.

FIG. 8 shows a schematic diagram of an imaging system. As shown in the figure, the image light incident through the optical system 71 and the stop 80 forms an image on the CMOS sensor 72. The optical information is converted into an electric signal by a pixel array arranged on the CMOS sensor 72, and is output after noise removal. The output signal is subjected to signal conversion processing by a signal processing circuit 73 by a predetermined method and output. The signal that has been subjected to the signal processing is recorded by a recording system and a communication system 74 by an information recording device, or information is transferred. The recorded or transferred signal is reproduced by the reproduction system 77.
The aperture 80, the CMOS sensor 72, and the signal processing circuit 73 are controlled by a timing control circuit 75, and the optical system 71,
The timing control circuit 75, the recording / communication system 74, and the reproduction system 77 are controlled by a system control circuit 76.

Next, a specific configuration of a unit cell which can be suitably used in the image pickup apparatus of the present invention will be described.

In the arrangement shown in FIG. 16, since the arrangement of the photoelectric conversion units 173 does not have the same pitch (a ₁ ≠ a ₂ ), the intervals of the light-related regions (light receiving units) in each pixel are equal. Instead, the following problem arises. That is, the non-equidistant arrangement of the same color partially causes the spatial frequency and the resolution to be unequal, thereby causing a decrease in resolution and defects such as moire fringes. In addition, the occurrence of moiré fringes is a very serious problem, and such an imaging device cannot be practically used as a product. This is also true when the number of pixels constituting the unit cell is other than four.

The present inventors have found that even in a CMOS sensor having amplifying means dispersed in a plurality of pixels, by keeping the pitch of the photoelectric conversion parts constant, the intervals between the respective light receiving parts become equal, and the resolution is reduced. We have found an imaging device that can prevent the occurrence of moiré fringes, improve the aperture ratio, and obtain good performance. Such an imaging device can be suitably used in the present invention.

FIG. 9 shows that the pixels in two rows and two columns are connected to the common amplifier 22.
It is a figure showing the example which shares. In FIG. 9, the shared common amplifier unit 22 is arranged at the center of the four pixels, and the four photoelectric conversion units (a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ ) are connected to the common amplifier unit 2.
2 are arranged. Here, the common amplifier section 22 includes transfer means MTX1 to MTX4 in addition to the amplification means MSF, reset means MSEL, and selection means MSEL of FIG.

Further, the light shielding portion 25 exists at a position symmetrical with the center of each pixel occupied by the common amplifier portion 22. Therefore, the center of gravity of the photoelectric conversion unit 21 in each pixel exists at the center of each pixel. Whereby said four photoelectric conversion unit (a ₁₁ ~a ₂₂₎ is longitudinally and can be placed at equal intervals a laterally.

In FIG. 10, the shared common amplifier unit 3
2 is arranged at the center of the four pixels in the horizontal direction, and the four photoelectric conversion units 31 (a ₁₁ , a ₁₂ , a ₂₁ , a ₂₂ ) are arranged so as to sandwich the common amplifier unit 32.

Further, the light-shielding portion 35 exists at a position symmetrical with the center of each pixel occupied by the common amplifier portion 32. Therefore, the center of gravity of the photoelectric conversion unit 31 in each pixel exists at the center of each pixel. Thus four photoelectric conversion unit (a ₁₁ ~a ₂₂₎ is longitudinally and can be placed at equal intervals a laterally.

The above-described embodiment shown in FIG. 10 is exactly the same even if the horizontal and vertical directions are exchanged.

FIG. 11 shows a specific pattern layout diagram of the first configuration example of the pixel array section of the CMOS sensor.

The CMOS sensor shown in FIG. 11 is formed on a single crystal substrate according to a layout rule of 0.4 μm, the size of a pixel is 8 μm square, and a source follower amplifier as amplifying means is a 4 × 2 matrix. Shared by pixel. Therefore, the repetition unit cell 8 shown by the dotted line area in FIG.
The size of 1 is 16 μm × 16 μm square, and a two-dimensional array is formed.

The photodiodes 82a, which are photoelectric conversion units,
Reference numerals 82b, 82c, and 82d are formed obliquely at the center of each pixel, and their shapes are substantially rotationally symmetric and mirror image symmetrical in up, down, left, and right directions. Further, these photodiodes 82a, 82
The centers of gravity g of b, 82c and 82d are designed to be the same for each pixel. Reference numeral 95 denotes a light shielding unit.

Reference numeral 88-a denotes a scanning line for controlling the upper left transfer gate 83-a, reference numeral 90 denotes a row selection line, and reference numeral 92 denotes a MOS gate 9.
3 is a reset line for controlling the reset line 3.

The signal charges stored in the photodiodes 82a to 82d pass through the transfer gates 83a to 83d and are transferred to the FDs.
It is led to 85. The MOS size of the gates 83a to 83d is L = 0.4 μm, W = 1.0 μm (L is a channel length,
W indicates the channel width. ).

The FD 85 is connected to an input gate 86 of a source follower by an Al wiring having a width of 0.4 μm.
The signal charge transferred to the FD 85 modulates the voltage of the input gate 86. The size of the MOS of the input gate 86 is L =
0.8 μm, W = 1.0 μm, and the sum of the capacitances of the FD 85 and the input gate 86 is about 5 fF. Q = because it is CV, input by the accumulation of 10 ⁵ electrons gates 86
Will change by 3.2V.

The current flowing from the V _DD terminal 91 is modulated by the input gate 86 and flows out to the vertical output line 87.
The current flowing out to the vertical output line 87 is signal-processed by a signal processing circuit (not shown), and finally becomes image information.

Thereafter, the photodiodes 82a to 82d,
FD85, the potential of input gate 86 to the V _DD predetermined value, MOS gate 9 is connected to a reset line 92
By opening 3 (the transfer gates 83a to 83d are also opened at this time), the photodiodes 82a to 82d, the FD 85, and the input gate 86 are short-circuited to the _VDD terminal.

Thereafter, by closing the transfer gates 83a to 83d, charge accumulation of the photodiodes 82a to 82d starts again.

It should be noted here that all of the wirings 88a to 88d, 90, and 92 penetrating in the horizontal direction are formed of a transparent conductor of ITO (Indium Tin Oxide) having a thickness of 1500 mm. Since light passes through the photodiodes 82a to 82d in the wiring portion, the center of gravity g of the photodiode coincides with the center of gravity of the light sensing area (light receiving portion).

According to this configuration example, it is possible to provide a CMOS sensor having a relatively high area ratio and a high aperture ratio in which the pixel pitch is equal.

FIG. 1 shows a specific pattern layout of the second example of the configuration of the pixel array section of the CMOS sensor of the present invention.
It is shown in FIG.

In FIG. 12, 102a to 102d are photodiodes, 103a to 103d are transfer gates,
5 is the FD, 106 is the input gate of the source follower, 10
7 is a vertical output line, 108a to 108d are scanning lines, 110
Is a row selection line, and 112 is a reset line for controlling the MOS gate 113.

In this configuration example, the wiring 1 running in the horizontal direction
Since 08a to 108d, 110, and 112 run three by three across the center of each pixel, even if the wiring is a metal wiring that blocks light incident on the photodiodes 102a to 102d, the light sensing area No shift of the center of gravity g occurs, and thus coincides with the center of the pixel.

According to this configuration example, since a normal (opaque) metal having a small electric resistance can be used, the time constant of the horizontal wiring is improved, and a higher-speed imaging device can be provided.

In the above configuration example, since the portion below the light shielding film is effectively used, a photodiode as a photoelectric conversion unit is formed up to the portion below the light shielding film as shown in FIG. It is also possible to function as.

In the above-described second configuration example, since the light crosses the center of the pixel having the highest light collection efficiency, there is a concern that the sensitivity of the image pickup apparatus may be reduced. A further improved third configuration example is shown in FIG.

In this configuration example, the transfer gates 123a to 123a
123d, FD125, source follower input gate 1
26, a wiring in which all the reset MOS gates 133 run in the horizontal direction (scanning lines 128a to 128d, row selection line 13
0, the reset line 132), the photodiodes 122a to 122d and the openings thereof can be maximized. In addition, the opening exists continuously at the center of each pixel. The light-shielding portions are formed in horizontal and vertical wiring portions.

In this embodiment, since the source follower and the reset MOS transistor, which are the amplifying means, are divided and arranged in the horizontal direction around each pixel, they can be compactly arranged below the horizontal wiring. ing.

Since an unused space still exists below the upper right pixel wiring, for example, a smart sensor
It is also possible to add new configurations.

According to this configuration example, since the photodiode area and the aperture ratio can be made large, it is possible to provide an imaging device with a wide dynamic range and high sensitivity.
Further, in the future, even if the size of the opening portion of the photodiode becomes about the wavelength of light, there is little possibility that light will not enter even if the size of the opening portion of the photodiode becomes about the wavelength of light, and the performance can be exhibited for a long time.

Further, in the above configuration example, the amplifying means is disposed at the center of the unit cell, and the center of gravity of the light sensing area coincides with the center of the pixel. However, the present invention is not limited to this.
A configuration in which the openings are translationally symmetric as shown in FIG. 15 may be used.

That is, since the openings are translationally symmetric, the light sensing regions have the same pitch.

[0068]

As described above in detail, according to the present invention, the number of temporary storage capacitors can be reduced, and the number of shift registers, the number of common circuits, the AGC, and the number of A / D converters can be reduced. Accordingly, the cost can be reduced by reducing the chip size.

Further, the power consumption is synergistically low, and as a result, there is an effect that mounting noise is reduced. Furthermore, the temporary storage means is reduced by the division drive. Therefore, the number of transfer switches connected to the horizontal output line can be reduced, and as a result, the parasitic capacitance of the horizontal output line decreases. Therefore, the readout gain from the temporary storage means to the horizontal output line can be increased. Alternatively, conversely, the temporary storage capacity can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating an example in which the present invention is applied to an imaging apparatus that reads out signals from four photoelectric conversion units via one common amplifier.

FIG. 2 is a diagram showing a configuration of a photoelectric conversion cell S.

FIG. 3 is a timing chart for explaining the operation of the imaging apparatus.

FIG. 4 is a timing chart showing timings in each color signal readout period.

FIG. 5 is an overall configuration diagram of the imaging device.

FIG. 6 is a schematic configuration diagram illustrating an embodiment of an imaging apparatus when a single cell is configured by one photoelectric conversion unit and one amplifier.

FIG. 7 is a diagram showing a cell configuration.

FIG. 8 is a schematic diagram of a system according to the present invention.

FIG. 9 is a diagram showing a layout of a unit cell according to the present invention.

FIG. 10 is a diagram showing a layout of a unit cell of the present invention.

FIG. 11 is a pattern layout diagram of one configuration example of the present invention.

FIG. 12 is a pattern layout diagram of one configuration example of the present invention.

FIG. 13 is a diagram illustrating a configuration example of the present invention.

FIG. 14 is a pattern layout diagram of one configuration example of the present invention.

FIG. 15 is a diagram illustrating a configuration example of the present invention.

FIG. 16 is a layout diagram of a unit cell of an example of an imaging device.

FIG. 17 is a schematic circuit diagram illustrating an example of a noise removal circuit of a conventional imaging apparatus.

FIG. 18 is a schematic circuit diagram illustrating an example of a noise removal circuit of a conventional imaging apparatus.

FIG. 19 is a schematic circuit configuration diagram illustrating an example of a noise removal circuit of a conventional imaging device.

[Explanation of symbols]

S photoelectric conversion cell (unit cell) a11, a12, a21, a22 photoelectric conversion section A1 common amplifier C _S signal storage capacity C _N noise storage capacity M1 to M8 transistor 10 subtraction amplifier 11 AGC (auto gain control) 12 A / D converter 13 Horizontal shift register (H / SR) 100 Signal storage component

Claims (15)

[Claims] 1. An imaging apparatus in which unit cells each having at least a plurality of photoelectric conversion units arranged in a row direction and a common circuit to which signals from the plurality of photoelectric conversion units are input are arranged in a plurality of columns. An imaging apparatus, wherein a signal holding unit shared for each photoelectric conversion unit in a unit cell is connected to a vertical output line, and a signal is read from the photoelectric conversion unit to the signal holding unit via the common circuit. 2. The imaging apparatus according to claim 1, wherein an operation of outputting a signal from the signal holding unit is sequentially performed for each photoelectric conversion unit. 3. A plurality of photoelectric conversion pixels are arranged in a row direction and a column direction, and a signal holding means shared for at least two photoelectric conversion pixel columns is connected to a vertical output line. And a noise holding unit that stores a noise component of the image signal. The operation of reading a signal from each photoelectric conversion pixel to the signal holding unit and outputting a signal from the signal holding unit is performed. An imaging apparatus configured to sequentially perform the operation for each of the photoelectric conversion pixels in the column direction and the row direction of the at least two columns of the photoelectric conversion pixel columns. 4. The signal holding means comprises: an image signal holding means for storing an image signal; and a noise holding means for storing a noise component of the image signal, and a means for differentiating the noise component from the image signal. The imaging device according to claim 2, wherein the imaging device has: 5. The imaging device according to claim 1, wherein a color filter is arranged in the photoelectric conversion unit. 6. The imaging device according to claim 3, wherein a color filter is arranged in the photoelectric conversion pixel. 7. The imaging device according to claim 3, wherein the photoelectric conversion pixel includes a photoelectric conversion unit and an amplifier to which a signal from the photoelectric conversion unit is input. 8. The imaging apparatus according to claim 1, wherein the common circuit includes an amplifying unit that amplifies a signal from the photoelectric conversion unit and a reset unit that resets the unit cell. 9. The imaging apparatus according to claim 7, wherein the amplifier has an amplifying unit that amplifies a signal from the photoelectric conversion unit and a reset unit that resets the unit cell. 10. The imaging device according to claim 1, wherein at least a pitch between the photoelectric conversion units is at least one direction in a vertical direction or a horizontal direction. An imaging apparatus, comprising: an adjusting unit for adjusting the pitch at a constant pitch. 11. An imaging apparatus according to claim 10, wherein said adjusting means is a light shielding film. 12. The method of claim 1, 2, 4, 5, 8, 10, 1.
The imaging device according to claim 1, wherein the common circuit is arranged at a center of a unit cell. 13. The imaging device according to claim 11, wherein the light shielding film is arranged between adjacent unit cells. 14. The imaging device according to claim 13, wherein the light-shielding film is arranged at least at a position which is line-symmetric with respect to a horizontal or vertical center line of the unit cell. . 15. The imaging device according to claim 1, a lens that forms an image on the imaging device, and a signal processing circuit that processes an output signal from the imaging device. An imaging system comprising: