JP2000068759A - Inverting amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate a refreshing circuit. SOLUTION: First and second inputting capacitances C1 and C2 are parallelly connected to the input of inverter circuits (MOS inverters I1 to I3), an input voltage is connected to the first capacitance C1 and a sample and hold circuit SH is connected to the second capacitance C2. A reference voltage Vref is inputted to the second capacitance C2 through a second switch S2 and at the same time, the reference voltage Vref is inputted to the first capacitance C1 through a third switch S3 to eliminate offset by an electric charge held by the circuit SH at this time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverting amplifier circuit, and more particularly to an input amplifier connected to an input voltage.
The present invention relates to an inverting amplifier circuit including an inverter circuit composed of odd-numbered series CMOS inverters connected to the output of the input capacitance and a feedback capacitance connecting the output of the inverter circuit to the input.

[0002]

2. Description of the Related Art Digital technology in computer science has been remarkably developed with the advance of microfabrication technology, but the amount of capital investment is increasing at an accelerating rate, and at present analog technology and analog / digital mixed technology are being developed. Is attracting attention. Accordingly, the applicant has filed an inverting amplifier circuit for transmitting an analog voltage input to a subsequent stage with sufficient linearity and driving capability (Japanese Patent Laid-Open No. 07-09495).
No. 7).

As shown in FIG. 4, the inverting amplifier circuit INVC proposed by the present applicant has CMOS inverters I1, I2,
I3 is connected in series, the input voltage Vin is input to the first-stage inverter I1 via the input capacitance C1, and the output of the last-stage inverter I3 is connected to the input of the first-stage inverter I1 via the feedback capacitance Co. Input voltage Vin due to the high gain due to the gain product of
Is generated with high linear characteristics and driving capability. A series circuit of a resistance RP and a capacitance CP is connected between the input and output of I2.
The phase compensation function prevents Vout from oscillating.

In the above inverting amplifier circuit, if the offset voltage of the CMOS inverter is Vb and the initial charge is Qo, the relationship of equation (1) is established,

(Equation 1) The right side of this equation (1) is

(Equation 2) Changes due to variations in Qo and offset voltage, the output accuracy is reduced. In order to secure this accuracy, a refresh circuit for erasing Qo and a V
An additional circuit for canceling b was required.

[0005]

SUMMARY OF THE INVENTION The present invention has been made under such a background, and has as its object to provide an inverting amplifier circuit having a higher output accuracy than the conventional one without providing a refresh circuit. .

[0006]

An inverting amplifier circuit according to the present invention has a second input capacitance connected to an input of the inverter circuit in parallel with a first input capacitance, and a sample hold circuit connected to the input of the second input capacitance. Circuit, a reference voltage is input to a second input capacitance via a second switch, and a reference voltage is simultaneously input to a first input capacitance via a third switch. Offset to eliminate the offset.

[0007]

Next, a first embodiment of the inverting amplifier circuit according to the present invention will be described with reference to the drawings.

[0008]

FIG. 1 shows an inverting amplifier circuit I of a first embodiment.
The NV includes an inverting amplifier circuit INVC similar to the conventional inverting amplifier circuit, and the circuit INV has an input capacitance C1 (referred to as “first input capacitance”) and a three-stage C.
An inverter circuit including MOS inverters I1 to I3,
And the feedback capacitance Co. A second input capacitance C2 is connected to the input of the inverter circuit in parallel with the first input capacitance C1,
A sample and hold circuit SH is connected between the input of the capacitance C2 and the output of the inverter circuit. A first switch S1 for connecting an input voltage Vin is connected to an input of the first input capacitance C1, and a second switch S2 for connecting a reference voltage Vref is connected to an input of the second input capacitance C2. Further, a third switch S3 for connecting the reference voltage Vref is connected to the input of the first input capacitance C1.

Before operating the inverting amplifier circuit INV, the switch S1 is opened so that no input voltage is applied,
Here, the switches S2 and S3 are closed. At this time, the output Vo of the inverting amplifier circuit INV is as shown in Expression (3), and the charge corresponding to the offset voltage Vb is held in the sample hold circuit SH.

(Equation 3) Next, the switches S2 and S3 are opened and S1 is closed to enter a normal operation state. The output voltage Vout at this time is as shown in Expression (4), and Expression (5) is obtained by substituting Expression (3) into Expression (4). Here, it is assumed that C2 = Co.

(Equation 4) As is apparent from the equation (5), it is found that the term of the offset voltage Vb is eliminated from the output voltage Vout, and thus the offset is eliminated.

As shown in FIG. 2, the sample-and-hold circuit SH includes a circuit in which circuits INVC1 and INVC2 similar to the conventional inverting amplifier circuit INVC are connected in series, and switches SWS1 and SWS2 are connected before and after the same. Can be used. When holding the sample,
WS1 is closed to open the subsequent SWS2, and for output, the preceding SWS1 is opened and the subsequent SWS2 is closed. This temporarily holds the input voltage SHi,
This can then be output as output voltage SHo.

FIG. 3 shows a second embodiment of the present invention, in which a capacitance C is used in place of the sample and hold circuit of the first embodiment.
ref is used. The capacitance Cref has one terminal connected to the input of the capacitance C2 via the switch S4, and the other terminal connected to the reference voltage Vref.
When the switches S2, S3, and S5 are closed, the capacitance Cref holds the charge corresponding to the offset voltage instead of the sample and hold circuit, and the above equation (3) is established. Here, the switches S2, S3, and S5 are opened, and the switches S1 and S4 are closed, thereby returning to a normal operation state. The output at this time is the same as in the above equation (4), and as a result, an output in which the offset shown in equation (5) is eliminated is obtained.

[0012]

As described above, in the inverting amplifier circuit according to the present invention, the input of the inverter circuit is connected to the second input capacitance in parallel with the first input capacitance, and the sample and hold is connected to the input of the second input capacitance. Circuit, a reference voltage is input to a second input capacitance via a second switch, and a reference voltage is simultaneously input to a first input capacitance via a third switch. Thus, since the offset is eliminated, there is an excellent effect that the output accuracy is higher than before without providing a refresh circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an inverting amplifier circuit according to the present invention.

FIG. 2 is a block diagram showing a sample and hold circuit of the embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional inverting amplifier circuit.

[Explanation of symbols]

INV, INVC. . . Inverting amplifier circuits I1, I2, I3. . . CMOS inverter C1, C2, Co, CP, Cref. . . Capacitance RP. . . Resistance S1 to S5, SWS1, SWS2. . . Switch Vin, Shi. . . Input voltage Vout, SHo. . . Output voltage Vref. . . Reference voltage Vb. . . Offset voltage.

Claims (3)

[Claims] A first input capacitance connected to the input voltage; an inverter circuit comprising an odd-numbered series CMOS inverter connected to the output of the input capacitance; and a feedback capacitance connecting the output of the inverter circuit to its input. A first switch connected between the input capacitance and the input voltage; a second input capacitance connected to the input of the inverter circuit in parallel with the input capacitance; A sample and hold circuit connected to an input of a second input capacitance; a second switch connecting a reference voltage to an input of the second input capacitance; a third switch capable of connecting the reference voltage to an input of the first input capacitance. And a switch; wherein the reference voltage is the CM
An inverting amplifier circuit, which is a threshold voltage of an OS inverter. 2. The inverting amplifier circuit according to claim 1, wherein the sample and hold circuit includes the inverter circuit according to claim 1 connected in two stages in series. 3. The sample-and-hold circuit has one terminal connected to the second terminal.
2. The inverting amplifier circuit according to claim 1, wherein the input terminal is connected to an input capacitance, and the other terminal is connected to a reference voltage.