JP2000068493A - Semiconductor element having quantum structure and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely manufacture a semiconductor element and uniformly manufacture a quantum structure with high reproducibility by forming a protrusion on the side of a semiconductor island in a semiconductor part and by constituting the side of the protrusion of a face, whose oxidation speed is faster than that of the side of a semiconductor island. SOLUTION: A semiconductor layer 12 is etched to oxidize a periphery of a pillar-like semiconductor at the center, and a protrusion 4 of the pillar-like semiconductor is isolated by an oxide film insulator 15, to form a semiconductor island 16 isolated from a semiconductor part of the protrusion 4 at a part of the center of the pillar-like semiconductor. At this time, due to the oxidation rate from the side of the protrusion 4 being fast, the oxidation on a small diameter part on the upper part of the protrusion 4 is caused to advance so as to go across the pillar-like semiconductor. The upper end of the protrusion 4 of the pillar-like semiconductor is pinched off by the oxide film insulator 15 to form a pinched-off part 15p. Thus a quantum structure can be manufactured with high reproducibly and uniformity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a quantum structure such as a single electron transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A single-electron transistor, that is, a single-electron transistor, is quantized by fine Si (silicon) semiconductor islands formed separately from a channel between a source and a drain via a tunnel oxide film. It functions as, for example, a transistor memory device that generates a potential change by trapping a single electron in this island portion (for example, Applied Physics Letters 70 (7) by Guo et al.
See 850 (1997). ).

As a method of manufacturing a quantum wire, for example, Si
Proposals have been made to form a quantum structure such as a quantum wire on a substrate by using an electron beam lithography method. However, in this method, there is a problem in that a sufficiently fine and uniform quantum wire is surely produced with good reproducibility.

[0004] Further, as another method for manufacturing a quantum wire,
For example, a VLS (Vapor Liquid Solid) method has been proposed (see EIGivargizov, J. Vac. Techno. B11 (2), p. 449). This is because gold (Au) is vapor-deposited on a Si substrate to form a molten alloy droplet of Si and Au on the surface of the Si substrate.
This is a method of growing Si quantum wires by supplying i source gas.

It has been proposed to use silicon chloride gas as a Si source gas used in the VLS method (Wagner et al., Applied Physics Letters 4, no.
9 (1964), Givargizov, J. Crystal Growth, 31, 20 (1975). ).

[0006]

SUMMARY OF THE INVENTION The present invention has a quantum structure in which semiconductor islands such as quantum wires and quantum dots are formed via a thin-film tunnel insulating film in, for example, a single-electron transistor memory element described above. It is an object of the present invention to provide a semiconductor device having a quantum structure and a method for manufacturing the same, which can surely and uniformly manufacture a semiconductor device with good reproducibility.

That is, in the present invention, the aforementioned V
An object of the present invention is to provide a semiconductor element having a quantum structure, which has a special structure by applying the LS method to some steps, and a manufacturing method capable of manufacturing the semiconductor element reliably and uniformly with good reproducibility.

[0008]

According to the present invention, there is provided a semiconductor device having a quantum structure, comprising a semiconductor island, an insulator covering the semiconductor island, and a semiconductor adjacent to one end of the semiconductor island. Having a structure. The semiconductor portion has a convex portion on the semiconductor island portion side, and the side surface of the convex portion has a structure including a surface having a higher oxidation rate than the side surface of the semiconductor island portion.

Further, according to the method of manufacturing a semiconductor device having a quantum structure according to the present invention, there is provided a step of forming a columnar semiconductor on a substrate, and oxidizing a periphery of the columnar semiconductor to cover the columnar semiconductor with an oxide insulator. An oxidation treatment step of forming a semiconductor island portion formed of a part of the columnar semiconductor. The columnar semiconductor formed by the columnar semiconductor forming process has a semiconductor portion having a convex portion that becomes wider toward the substrate side on the substrate side, and the side surface of the convex portion is smaller than the side surface of the columnar portion. And a surface formed by a surface including a surface having a high oxidation rate.

As described above, according to the present invention, a structure in which a convex portion having a side surface having a high oxidation rate is formed on a semiconductor;
By a simple method of separating a semiconductor island portion and a semiconductor portion having a convex portion by a thin-film oxide insulator by the progress of oxidation by a side surface having a high oxidation rate in the convex portion,
A semiconductor device having a quantum structure having a tunnel insulating film can be formed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device having a quantum structure according to the present invention is a quantum structure comprising a semiconductor island, an insulator covering the semiconductor island, and a semiconductor adjacent to one end of the semiconductor island. The semiconductor portion has a convex portion on the semiconductor island portion side, and the convex portion has a side surface having a faster oxidation rate than the side surface of the semiconductor island portion. It consists of a surface.

In the manufacturing method of the present invention, the VLS method can be applied. Further, the VLS method is applied to the application by the present applicant, Japanese Patent Application No. 8-325555, and Japanese Patent Application No. 9-256545. And the like.

An example of a semiconductor device having a quantum structure according to the present invention will be described with reference to the drawings together with an example of a manufacturing method according to the present invention, but the present invention is not limited to these examples.

First, a step of forming a columnar semiconductor 2 on a substrate 1 will be described with reference to FIG. The substrate 1 has, for example, a specific resistance ρ = 0.4Ω · cm, and one main surface 1a thereof.
However, a Si semiconductor substrate having a {111} crystal plane is used. One main surface 1a of the substrate 1 is polished, further washed with, for example, acetone, and etched with a mixed solution of nitric acid and hydrofluoric acid to remove a surface oxide film. In this way, the pre-processing for the substrate 1 is performed.

As shown in FIG. 1A, the main surface 1
On a, a molten alloy droplet with Si, which will be described later, is formed, and a metal serving as a catalyst for the growth of the columnar semiconductor, such as Au, is deposited to form a metal layer 5 having a thickness of about 0.6 nm. Thereafter, under heating of the substrate temperature of 300 ° C. to 700 ° C., for example, 520 ° C., the raw material gas of Si, particularly silane (Si _n H _{2n + 2} )
At least one of monosilane, disilane and trisilane is supplied to thermally decompose the raw material gas. In this case, the supply of the Si source gas is performed, for example, by supplying a partial pressure of 0.5 mTorr or more to 1
0 mmTorr. In this way, as shown in FIG. 1B, a molten alloy droplet 3 was formed, and subsequently, as shown in FIG. 1C, a convex portion 4 was formed on the substrate 1 side in a portion where the molten alloy droplet 3 was formed. The columnar semiconductor 2 grows. This columnar semiconductor 2
Is formed such that its axial direction is in the <111> direction. And the convex part 4 formed in the base side is formed in the shape which becomes wide toward the board | substrate 1 side, and the surrounding side surface 4s is
It is formed by a crystal plane having a high oxidation rate, for example, a plane containing (110) and (100), which is an inclined side face that is not orthogonal to {111}.

FIG. 2 is a SEM (Scanning Electron Microscope) photograph of the columnar semiconductor 2 formed in this manner.
Was formed in the <111> direction. FIG. 3 shows a TEM (Transmission Electron Microsco
pe: transmission electron microscope))
It is observed that the columnar semiconductor 2 has a columnar portion 2c having an almost uniform diameter and a convex portion 4 wider toward the substrate 1 at the substrate 1, that is, at the base.

When the growth time of the columnar semiconductor 2 is 1 hour, the length (height) h can be set to 1 μm, and the diameter can be formed to 10 nm to 100 nm. Then, the columnar semiconductor 2 formed by this method is formed in a uniform size and shape with good reproducibility.

The substrate 1 used in the method of the present invention may be composed of, for example, a semiconductor substrate or a semiconductor layer on an insulating substrate, as described above, according to the configuration of the semiconductor device having the target quantum structure. SOI formed with
A so-called SIMOX (Separate by Implante) formed by implanting oxygen to a predetermined depth of a substrate or a semiconductor substrate.
d Oxygen).

An example of a single-electron transistor memory device having a quantum structure according to the present invention will be described with reference to FIGS. 4 to 9 together with an example of a manufacturing method according to the present invention. FIG.
9, each of A ₁ and A ₂ is a schematic plan view of a main part in each step, and each of B ₁ and B ₂ is a schematic cross-sectional view of each of A ₁ and A ₂ .

In this example, the substrate 1 has the above-described SI
The MOX structure, that is, structurally, the Si substrate 10
This is a case in which a Si semiconductor layer 12 is formed thereon with an SiO ₂ insulating layer 11 interposed therebetween. As shown in FIGS. 4A ₁ and B ₁ , the columnar semiconductor 2 was formed on the semiconductor layer 12 by the method described with reference to FIG. Therefore, as described above, the columnar semiconductor 2 is formed with a semiconductor portion by the convex portion 4 which becomes wider toward the substrate 1 side, and the outer side surface 4 s of the convex portion is formed in the columnar portion of the columnar semiconductor 2. It is formed by a plane including a crystal plane having a higher oxidation rate than the side surface.

Next, as shown in FIGS. 4A ₂ and B ₂ ,
Liftoff mask material along one direction from obliquely above the columnar semiconductor 2 (shown with in Figure 4B ₂ arrows), eg flying deposited Al, for example, evaporation to form a lift-off mask layer 13. The lift-off mask layer 13 thus formed was partially blocked by the columnar semiconductor 2, that is, the columnar semiconductor 2 in the above-described oblique deposition.
A part of the side surface of the columnar semiconductor 2 which is shaded by
Along with this, and on the semiconductor layer 12, there is formed a notch region 13W which is not covered with the lift-off mask material and extends in one direction.

As shown in FIGS. 5A ₁ and B ₁ , the first etching mask layer 1 serving as an etching mask for the semiconductor layer 12 covering at least the notch region 13W.
4. For example, an Au layer is formed by vapor deposition over the entire surface.

As shown in FIGS. 5A ₂ and B ₂ , the lift-off mask layer 13 made of, for example, Al is lifted off by dissolving it with the etchant. In this manner, the etching mask layer 14 formed on the first lift-off mask layer 13 is removed, and the first mask layer 14 directly attached to the semiconductor layer 12 through the cutout region 13W of the lift-off mask layer 13 is removed. Is selectively left.

As shown in FIGS. 6A ₁ and B ₁ , FIG.
_The vapor deposition direction in the oblique vapor deposition described in ₂ and B ₂ means that the lift-off mask material such as Al described above is fly-deposited with a directionality obliquely upward from the opposite symmetric direction across the columnar semiconductor 2. For example, vapor deposition. Thus, the first etching mask layer 1 of the columnar semiconductor 2
A second lift-off in which a cut-off region 23W of the mask material for lift-off is formed in a portion of the columnar semiconductor 2 along one direction on the substrate from a side surface opposite to the side on which the substrate 4 is formed. The mask layer 23 is formed.

As shown in FIGS. 6A ₂ and B ₂ , the second lift-off mask layer 23 has at least the
For example, Au is vapor-deposited on the entire surface of the second etching mask layer 24 which also serves as an etching mask for the semiconductor layer 12 so as to cover 3W.

Then, as shown in FIGS. 7A ₁ and B ₁ , the second lift-off mask layer 23 is lifted off by the etchant. By doing so, only the second etching mask layer 24 that is formed directly on the semiconductor layer 12 through the cutout region 23W is left, and the other second etching mask layer 24 is It is removed together with the lift-off mask layer 23.

In this way, as shown in FIG. 7A ₁ , the columnar semiconductor 2 has a small width corresponding to the diameter of the columnar semiconductor 2. An etching mask is formed by the first and second etching mask layers 14 and 24 extending on the line.

Next, as shown in FIGS. 7A ₂ and B ₂ ,
Using the first and second etching masks 14 and 24 as masks, the semiconductor layer 12 is etched to form, for example, a columnar semiconductor 2 at the center and a linear pattern extending linearly on both sides with a width corresponding to the diameter. Is formed.

As shown in FIGS. 8A ₁ and B ₁ , the first and second etching masks 14 and 24 are etched away by, for example, aqua regia.

Further, as shown in FIGS. 8A ₂ and B ₂ , the molten alloy droplet 3 is removed by using, for example, an etching solution of HCl and HNO ₃ at a ratio of 3: 1.

Next, as shown in FIGS. 9A ₁ and B ₁ ,
Oxidation is performed to oxidize the periphery of the columnar semiconductor 2, and the protrusions 4 of the columnar semiconductor 2 are separated by the oxide insulator 15, and the semiconductor islands 1 separated from the semiconductor portions of the protrusions 4 are formed.
6 is formed at a part of the center of the columnar semiconductor 2. This oxidation is, 700 ° C. in O ₂ atmosphere of the example 500 Torr, 1
The heat treatment is performed for a long time. In this case, the side surface 4 of the projection 4
Due to the high oxidation rate from s, the oxidation progresses across the columnar semiconductor 2 at the small diameter portion above the projection 4, and the upper end of the projection 4 of the columnar semiconductor 2 Pinch off by Moreover, since the oxide insulator 15 is also formed on the peripheral surface of the columnar portion of the columnar semiconductor 2, the semiconductor island portion 16 covered with the oxide insulator 15 is formed on the columnar portion of the columnar semiconductor 2.

FIG. 10 is a view drawn based on a TEM photograph of the columnar semiconductor 2 after this oxidation treatment. As is clear from this, an oxide insulator 15 is formed along the peripheral surface of the columnar semiconductor 2. However, at the upper end of the convex portion 4, the oxide insulator 1
5 is a pinch-off portion 1 formed across the columnar semiconductor 2
5p results. The thickness d of the pinch-off portion 15p is 7
nm to 13 nm,
The oxide insulator in the pinch-off portion 15p can function as a tunnel insulating film. Above the area separated by the pinch-off portion 15p, a fine semiconductor island 16 covered by the oxide insulator 15 on the peripheral surface and the pinch-off portion 15p is formed. This semiconductor island 16
Can have a diameter of slightly less than 5 nm to 12 nm, whereby a quantum structure can be formed.

The thickness d of the pinch-off portion 15p
Alternatively, the diameter of the semiconductor island 16 can be selected by selecting the diameter of the columnar semiconductor 2, that is, the diameter of the molten alloy droplet 3, the oxidation treatment conditions, for example, the oxidation time.

As shown in FIGS. 9A ₂ and B ₂ , for example, Si covering the columnar semiconductor 2 on which the semiconductor island 16 is formed
An insulating layer 17 of O ₂ or the like is entirely formed, and high-concentration, for example, n-type source and drain regions are formed by, for example, ion implantation. Cover the entire surface with an insulating layer,
Patterning is performed by photolithography or the like so as to cover the columnar semiconductor portion so that the drain region is exposed.
Source and drain electrodes 18s and 18d and a gate electrode 18g of, for example, a polycrystalline Si semiconductor layer having a high impurity concentration, that is, a low specific resistance, are formed on the source / drain regions and on the insulating layer 17. In this way, the intended single-electron transistor memory element 19 having the quantum structure in which the semiconductor island 16 is formed is configured.

Although only one columnar semiconductor is shown in FIGS. 4 to 9, a plurality of columnar semiconductors are formed on a common substrate 1 so that a semiconductor element having a plurality of quantum structures can be simultaneously formed. It can be formed into an integrated circuit configuration.

In the example described with reference to FIG. 4, the metal layer 5 for forming the molten alloy droplet 3 is deposited on the entire surface of the substrate 1. In this case, the generated molten alloy droplet 3 The columnar semiconductor 2 is not necessarily formed at a target position. To avoid such inconvenience, the metal layer 5
The formation position of the molten alloy droplet 3 at the target position,
Therefore, a method of forming the columnar semiconductor 2 can be adopted. An example of this case will be described with reference to FIG.

In this case, as shown in FIG.
A position regulating film 31 is formed thereon. This position regulating film 31
Is formed by, for example, forming a SiO ₂ film to a thickness of about 100 nm, performing pattern etching by, for example, photolithography, finally forming a through hole 31a in a portion where the columnar semiconductor 2 is to be formed, and through these through holes 31a, Substrate 1
A limited part of the surface of the device is exposed to the outside. This opening has a diameter of, for example, 1 μm to 0.8 μm.

After the formation of the through holes 31a in the position regulating film 31, the substrate 1 is washed, dried, and heated to, for example, 700 ° C. to form a molten alloy droplet. Au is deposited to form a metal layer 5 having a thickness of, for example, 0.6 nm. At this time, the Au metal layer 5 is made of Si
The through holes 31 are not formed on the position regulating film 31 made of O _2.
a, the metal layer 5 is selectively formed only on the surface of the substrate 1, that is, only on the portion where the semiconductor is exposed.

Next, the aforementioned Si source gas, for example, S
iH ₄ is supplied, and a heat treatment similar to that described with reference to FIG. 1 is performed. In this way, as shown in FIG. 11B, the molten alloy droplets 3 of Si and Au are placed in the through holes 31a of the position regulating film 31.
Is formed. In this way, the position where the molten alloy droplet 3 is formed can be defined. Therefore, after that, if the above-described columnar semiconductor 2 is grown, the position where the columnar semiconductor 2 is formed is also defined at this position. Then, the position regulating film 31 can be removed by etching in an appropriate step.

Further, an example of a semiconductor device having another quantum structure according to the present invention and a manufacturing method according to the present invention will be described with reference to FIGS. In this example,
The figure shows a case where three single electron transistor memory elements are applied to an integrated circuit device formed simultaneously on a common, for example, single Si substrate 1. Even in this case, S
The main surface 1a of the i-substrate 1 is selected as {111},
The same preprocessing as in the above-described example is performed.

In this example, the position regulating film 31 having the through-hole 31a is formed on the substrate 1 at the position where the target memory element is to be formed by the method described with reference to FIG.
Was formed, and a metal layer 5 of, for example, Au was deposited to form a molten alloy droplet 3. The formation pitch of the molten alloy droplet 3 is:
For example, it can be selected to be 1.0 μm. Then, by supplying a Si source gas, the columnar semiconductor 2 is grown by the catalytic action of the molten alloy droplet 3 as shown in FIG. 12A. Also in this case, in the columnar semiconductor 2, a semiconductor portion, that is, a convex portion 4, which widens toward the substrate 1 and has an inclined side surface 4 s formed on the outer periphery, is formed on the substrate 1 side.

The axial direction of the columnar semiconductor 2 is <1.
11> direction. The convex portion 4 formed on the base side has a side surface 4 s formed by a plane including a crystal plane with a high oxidation rate, which is an inclined side surface that is not orthogonal to {111}.

After the formation of the columnar semiconductor 2, as shown in FIG. 12B, the position regulating film 31 is removed by etching.

Thereafter, an oxidation treatment is performed. In this way, as shown in FIG. 12C, the periphery of the columnar semiconductor 2 is oxidized, and the protrusion 4 of the columnar semiconductor 2 is
The semiconductor island part 16 separated from the semiconductor part of the convex part 4 by the step 5 is formed in a part of the center part of the columnar semiconductor 2. This oxidation is performed by a heat treatment at 700 ° C. for 1 hour in a 500 Torr O ₂ atmosphere, for example. In this case, the oxidation rate on the side surface 4s of the convex portion 4 is high,
The oxidation progresses across the columnar semiconductor 2, and the upper end of the convex portion 4 of the columnar semiconductor 2 is pinched off by the oxide insulator 15, and the pinch-off portion 15 p is generated. Moreover, since the oxide insulator 15 is also formed on the peripheral surface of the columnar portion of the columnar semiconductor 2, the semiconductor island portion 16 covered with the oxide insulator 15 is formed on the columnar portion of the columnar semiconductor 2. Also in this case, the semiconductor island portion 1 is selected by selecting the diameter of the columnar semiconductor 2 and the oxidation treatment conditions.
6 can be made sufficiently small to form a quantum level, and the thickness of the pinch-off portion 15 can be selected to be thin enough to function as a tunnel film.

Next, as shown in FIG. 12D, as shown by arrows a and b, the electrode conductors are formed obliquely from two directions symmetric with respect to each other across the semiconductor island portion 16 by fly deposition, for example, by vapor deposition, for example, by a metal layer. A layer 32 is applied. In this manner, the electrode conductive layer 32 is formed thick on the opposing side surfaces of the semiconductor island portion 16 covered by the oxide insulator 15, and the flat portion and the columnar portion having the semiconductor island portion 16 are formed. The electrode conductive layer 32 formed on the upper end is formed thin.

Therefore, thereafter, as shown in FIG. 13A, the entire surface of the conductive layer 32 is etched to remove the thin portion of the electrode conductor 32 formed on the flat portion, and then the upper end of the columnar portion and the flat portion are removed. The conductive layer 32 has been eliminated and FIG.
As shown in the plan view of FIG. 4, the conductive layer 32 is selectively left on both sides of the columnar portion, and a pair of source and drain electrodes 18s and 18d separated by the columnar portion.
Is formed.

Next, as shown in FIG. 13B, an insulating layer 33 made of, for example, SiO _{2 is} entirely formed by CVD (Chemical Vapor Deposition).
r Deposition) method, and then, as shown in FIG. 13C, the surface is subjected to, for example, chemical mechanical polishing (CM).
The insulating layer 33 is planarized by the P) method or the like.

On the flattened surface, as shown in FIG. 13D, a gate electrode 18g is formed on each semiconductor island portion 16. In this manner, each micro semiconductor island 16 is formed on the common substrate 1, and the oxide insulator 15 formed at the upper end of the projection 4, that is, the thin portion in the pinch-off portion 15 p is used as a single tunnel oxide film. A plurality of memory elements having an electronic transistor configuration are formed.

Also in this configuration, the semiconductor island portion 16 can be made sufficiently small and the pinch-off portion 15p can be made thin enough to function as a tunnel insulating film. For example, a memory element having a single-electron transistor configuration can be formed.

As described above, according to the present invention, a single-electron transistor memory element having a quantum structure in which semiconductor islands such as quantum wires and quantum dots are formed via a thin tunnel insulating film is formed. According to the manufacturing method of the present invention, by combining the steps of the VLS method and the oxidation, a method of manufacturing a semiconductor device having a target quantum structure with good reproducibility and uniformity was surely achieved. Things.

In the manufacturing method of the present invention, when the Si source gas used for growing the columnar semiconductor is a silane-based gas, the heat treatment temperature can be reduced as compared with the case where a silicon chloride gas is used as before. In addition, a columnar semiconductor having a small diameter can be easily manufactured.

In the above example, the molten alloy droplets 3 are formed under the supply of the Si raw material gas. However, the formation of the molten alloy droplets 3 of Si and Au is performed by And can also be formed.

The present invention is not limited to the above-described example, and various modifications can be made.

[0054]

As described above, according to the present invention, there is provided a single-electron transistor memory element having a quantum structure in which semiconductor islands such as quantum wires and quantum dots are formed via a thin tunnel insulating film. According to the manufacturing method of the present invention, a method of manufacturing a semiconductor device having a target quantum structure with good reproducibility and uniformity by combining a VLS method and an oxidation step. It was done.

In the manufacturing method of the present invention, when the Si source gas used for growing the columnar semiconductor is a silane-based gas, the heat treatment temperature can be lowered as compared with the case where a silicon chloride gas is used as before. In addition, a columnar semiconductor having a small diameter can be easily manufactured.

[Brief description of the drawings]

FIGS. 1A to 1C are schematic cross-sectional views in respective steps of an example of a method of forming a columnar semiconductor used for describing the present invention.

FIG. 2 is a diagram drawn based on a scanning electron micrograph of a columnar semiconductor.

FIG. 3 is a drawing drawn based on a transmission electron micrograph of a columnar semiconductor.

[4] A ₁ and A ₂ is a schematic plan view of the one step of one embodiment of the production method of the example of the present invention device. B ₁ and B ₂
Is a schematic cross-sectional view of A ₁ and A _2.

[5] A ₁ and A ₂ is a schematic plan view of the one step of one embodiment of the production method of the example of the present invention device. B ₁ and B ₂
Is a schematic cross-sectional view of A ₁ and A _2.

[6] A ₁ and A ₂ is a schematic plan view of the one step of one embodiment of the production method of the example of the present invention device. B ₁ and B ₂
Is a schematic cross-sectional view of A ₁ and A _2.

[7] A ₁ and A ₂ is a schematic plan view of the one step of one embodiment of the production method of the example of the present invention device. B ₁ and B ₂
Is a schematic cross-sectional view of A ₁ and A _2.

[8] A ₁ and A ₂ is a schematic plan view of the one step of one embodiment of the production method of the example of the present invention device. B ₁ and B ₂
Is a schematic cross-sectional view of A ₁ and A _2.

[9] A ₁ and A ₂ is a schematic plan view of the one step of one embodiment of the production method of the example of the present invention device. B ₁ and B ₂
Is a schematic cross-sectional view of A ₁ and A _2.

FIG. 10 is a diagram drawn based on a transmission electron micrograph of a columnar semiconductor after an oxidation treatment.

FIGS. 11A and 11B are schematic cross-sectional views in respective steps of another example of a method of forming a columnar semiconductor used for describing the present invention.

FIGS. 12A to 12D are schematic cross-sectional views each showing one step of a method of manufacturing an example of the device of the present invention.

FIGS. 13A to 13D are schematic cross-sectional views each showing one step of a manufacturing method of an example of the device of the present invention.

FIG. 14 is a schematic plan view of one step of a manufacturing method of an example of the element of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 1a ... Main surface, 2 ... Column-shaped semiconductor,
3 ... Molten alloy drop, 4 ... Side, 5 ... Metal layer,
DESCRIPTION OF SYMBOLS 10 ... Base, 11 ... Insulating layer, 12 ... Semiconductor layer, 13 ... 1st lift-off mask layer, 13W
..Emission region, 14... First etching mask layer,
15 ... oxide film insulator, 15 p ... pinch-off part,
16 ... semiconductor island part, 17 ... insulating layer, 18s ...
・ Source electrode, 18d ・ ・ ・ Drain electrode, 18g ・ ・
A gate electrode, 23 a second lift-off mask layer, 23 W a missing area, 24 a second etching mask layer, 31 a position regulating film, 31 a a through hole, 32 ... electrode conductive layer,

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hidetaka Hirano 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Setsuo Usui 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (9)

[Claims] 1. A semiconductor structure comprising: a semiconductor island portion; an insulator covering the semiconductor island portion; and a quantum structure including a semiconductor portion adjacent to one end of the semiconductor island portion; The convex portion has a side surface, as compared with the side surface of the semiconductor island portion,
A semiconductor device having a quantum structure, including a surface having a high oxidation rate. 2. The semiconductor device according to claim 1, wherein the insulator interposed between the semiconductor island and the protrusion is a tunnel insulating film, and the semiconductor island is a minute island to form a quantum structure. A semiconductor device having the quantum structure according to claim 1. 3. The semiconductor island portion, wherein the insulator interposed between the semiconductor island portion and the convex portion is a tunnel insulating film, and a source and a drain region are formed on both sides of a portion where the convex portion is formed. 2. The semiconductor device having a quantum structure according to claim 1, wherein a gate electrode is formed at least via the insulator. 4. A step of forming a pillar-shaped semiconductor on a substrate, and oxidizing a periphery of the pillar-shaped semiconductor to form a semiconductor island portion composed of a part of the pillar-shaped semiconductor and covered with an oxide insulator. A columnar semiconductor formed by the columnar semiconductor forming step has a semiconductor portion on the substrate side having a convex portion that becomes wider toward the substrate side, and a side surface of the convex portion. Is formed by a surface including a surface having a higher oxidation rate than the side surface of the columnar portion, wherein the semiconductor device has a quantum structure. 5. The semiconductor device according to claim 5, wherein in the oxidation treatment step, the convex portion and the semiconductor island portion are separated by an oxide film insulator generated from a surface of the convex portion having a high oxidation rate. 5. A method for manufacturing a semiconductor device having the quantum structure according to 4. 6. The step of forming the columnar semiconductor includes: a step of depositing a metal forming a molten alloy droplet with silicon on a substrate; a heating step of forming a molten alloy droplet of silicon and the metal; 5. The method of manufacturing a semiconductor device having a quantum structure according to claim 4, further comprising: a step of thermally decomposing a gas to grow the columnar semiconductor portion on a portion where the molten alloy droplet silicon is formed. 7. The method of manufacturing a semiconductor device having a quantum structure according to claim 6, wherein the silicon source gas is at least one of monosilane, disilane, and trisilane. 8. The substrate comprises an insulating layer or a substrate having a semiconductor layer on an insulating substrate, and after forming the columnar semiconductor having the convex portion on the substrate side on the semiconductor layer of the substrate. A mask material for lift-off is fly-deposited with a direction from one direction obliquely above the columnar semiconductor, and from a partial side surface of the columnar semiconductor to a portion which becomes a shadow of the columnar semiconductor along one direction on the substrate. Forming a lift-off mask layer in which the first lift-off mask material lacking region is formed; and forming an etching mask for the semiconductor layer of the substrate on the substrate so as to cover at least the lacking region. The first
Forming the etching mask layer, lifting off the lift-off mask layer, and selectively leaving the first etching mask layer in the deficient region; The lift-off mask material is fly-deposited with a direction from a direction symmetrical to the flight direction of the mask material for use, and a partial side surface of the columnar semiconductor is opposite to the side on which the first etching mask layer is formed. Forming a second lift-off mask layer in which a region where the lift-off mask material is not formed is formed in a portion of the substrate that is shaded by the columnar semiconductor; and at least one of the lift-off mask layers Forming a second etching mask layer on the substrate covering the deficient region and serving as a mask for etching the semiconductor layer of the substrate; Lifting off the second lift-off mask layer to selectively leave the second etching mask layer in the vacant region; and etching the semiconductor layer using the first and second etching mask layers as a mask. And then oxidizing the periphery of the columnar semiconductor on which the protrusions are formed on the substrate side by performing the above oxidation treatment and covering the columnar semiconductor with an oxide film insulator. A method for manufacturing a semiconductor device having a quantum structure according to claim 4, wherein the semiconductor device is formed. 9. The semiconductor device according to claim 1, wherein the substrate is a semiconductor substrate or a substrate having a semiconductor layer, wherein a portion of the columnar semiconductor formed on the substrate is oxidized and covered with an oxide film insulator. After forming the semiconductor island portion, the conductive layer is fly-deposited with directionality from two opposite directions obliquely above the columnar semiconductor and separated from each other on both sides of the columnar semiconductor by the conductive layer. Forming a pair of electrodes by layers, forming an insulating layer entirely over the electrodes, and forming a gate electrode above the semiconductor island on the insulating layer. A method for manufacturing a semiconductor device having the quantum structure according to claim 4.