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JP2000058599A - Manufacture of tab tape - Google Patents

Manufacture of tab tape

Info

Publication number
JP2000058599A
JP2000058599A JP21931298A JP21931298A JP2000058599A JP 2000058599 A JP2000058599 A JP 2000058599A JP 21931298 A JP21931298 A JP 21931298A JP 21931298 A JP21931298 A JP 21931298A JP 2000058599 A JP2000058599 A JP 2000058599A
Authority
JP
Japan
Prior art keywords
lead
wiring
tab tape
pattern
resist layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21931298A
Other languages
Japanese (ja)
Inventor
Masaki Baba
順己 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP21931298A priority Critical patent/JP2000058599A/en
Publication of JP2000058599A publication Critical patent/JP2000058599A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To correspond to the high density and compactness in size and width of a lead and improve the yield of products by forming a lead pattern in a manner to connect leads mutually in a lead tip part, and cutting the connecting part of the lead tip part to separate every lead individually before connecting them to a semiconductor device. SOLUTION: An adhesives 2 is applied to an insulation film having a device hole, and a copper foil 3 is adhered thereto and a resist layer is provided on its surface. Then a mask is brought closely into contact with the resist layer, and it is exposed and developed. Further, the exposed copper foil part is etched to form a wiring pattern, and the remaining resist layer is removed. The lead tip parts 4 of the wiring pattern are entirely connected mutually, and when connecting them to semiconductor elements, the connection parts of the lead tip part 4 are cut into individual leads. Therefore, no wiring for plating conduction is provided to the periphery part at every lead, so that the density of broken wire can be reduced and a wiring of smaller laying length can be designed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、リードの変形が少
なく、リード位置精度の良いTABテープの製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for producing a TAB tape having a small lead deformation and a high lead position accuracy.

【0002】[0002]

【従来の技術】半導体素子の実装部品の一つにTABテ
ープがある。従来のTABテープはデバイスホールを有
する厚さ50〜125μmのポリイミドフィルムに厚み
15〜35μmのCu箔を接着した銅ポリイミドフィル
ムを用い、Cu箔をフォトエッチングして配線パターン
を形成して得ている。
2. Description of the Related Art A TAB tape is one of the components mounted on a semiconductor device. A conventional TAB tape is obtained by using a copper polyimide film in which a Cu foil having a thickness of 15 to 35 μm is bonded to a polyimide film having a device hole and having a thickness of 50 to 125 μm, and forming a wiring pattern by photo-etching the Cu foil. .

【0003】この配線パターンの各リード部先端部は前
記デバイスホールに片持ち状に張り出しており、使用に
際してはこのリードの先端部が半導体素子の電極部と一
括または1リード単位で接続される。
The leading end of each lead portion of this wiring pattern protrudes in a cantilever manner into the device hole. In use, the leading end of each lead is connected to the electrode portion of the semiconductor element at a time or in units of one lead.

【0004】ところで、近年の半導体素子の高密度化の
要求は、リード幅を20μm、リードピッチを40μm
にするというレベルまでの狭小化を求めており、実際に
そのようなTABテープが作製されている。しかし、こ
のようなTABテープではリードの機械的強度の低下が
著しくなり、製造工程でのダメージおよびハンドリング
等での変形が多く製品歩留まりの低下を招いている。
[0004] In recent years, there has been a demand for a higher density of a semiconductor element, with a lead width of 20 µm and a lead pitch of 40 µm.
Therefore, such a TAB tape has been actually manufactured. However, in such a TAB tape, the mechanical strength of the lead is remarkably reduced, and damage in the manufacturing process and deformation due to handling and the like are large, resulting in a reduction in product yield.

【0005】また、配線パターンの高密度化、狭小化に
伴いリードを含む周辺パターンでの「断線」「ショート」
「エッチング残り」「配線の欠け」「ピンホール」とい
った所謂「エッチング不良」の発生率も高くなり、やは
り製品歩留まりの低下を招いている。
[0005] In addition, as the wiring pattern becomes higher in density and narrower, "disconnection" and "short" in a peripheral pattern including a lead.
The occurrence rate of so-called "etching failure" such as "residual etching", "missing wiring", and "pinhole" also increases, which also causes a reduction in product yield.

【0006】加えて、多ピン化、狭ピッチ化に伴いア1
0〜15μmレベルという従来のリードピッチ精度で作
製した高密度実装用TABテープを用いると、リードと
半導体素子の電極とにずれを生じ、接続がでない。この
ため必要とされるピッチ精度は5μm以下となってきて
いる。この点も製品歩留まりの低下の原因となってい
る。
In addition, with the increase in the number of pins and the narrow pitch,
When a TAB tape for high-density mounting manufactured with a conventional lead pitch accuracy of the level of 0 to 15 μm is used, there is a shift between the leads and the electrodes of the semiconductor element, and there is no connection. For this reason, the required pitch accuracy is 5 μm or less. This point also causes a decrease in product yield.

【0007】[0007]

【発明が解決しようとする課題】本発明は上記状況に鑑
みてなされたものであり、リードの高密度化、狭小化に
対応でき、かつ製品歩留まりの高いTABテープの製造
方法の提供を課題とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method of manufacturing a TAB tape which can cope with high density and narrow leads and has a high product yield. I do.

【0008】[0008]

【課題を解決するための手段】上記の目的の達成のた
め、本発明は、導電層が設けられた絶縁フィルムを用い
てフォトリソグラフ法によりTABテープを製造するに
際して、リードパターンを、リード先端部分がリード相
互に連結されたパターンとし、半導体素子と接続する前
にリード先端部分の連結部を切断して各リードを独立さ
せるものである。
In order to achieve the above object, the present invention provides a method for manufacturing a TAB tape by photolithography using an insulating film provided with a conductive layer. Is a pattern in which the leads are connected to each other, and the connecting portion at the leading end of the lead is cut off before connecting to the semiconductor element to make each lead independent.

【0009】[0009]

【発明の実施の形態】本発明の製造方法では、導電層が
設けられた絶縁フィルムを用いてフォトリソグラフ法に
よりTABテープを製造するに際して、配線部のリード
パターンを、リード先端部分がリード相互に連結された
パターンとし、半導体素子と接続するに際してこのリー
ド先端部分の連結部を切断して各リードを独立させる。
こうするのは、TABテープ製造最終工程に至るまで個
々のリードを連結しておくことによりリード部全体とし
て強度を確保し、各工程でリードが変形するのを防止し
ようとするものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In a manufacturing method according to the present invention, when a TAB tape is manufactured by a photolithographic method using an insulating film provided with a conductive layer, a lead pattern of a wiring portion is formed so that a leading end portion of a lead is connected to each other. When connecting to a semiconductor element, the connecting portion at the leading end of the lead is cut to make each lead independent.
This is to secure the strength of the entire lead portion by connecting the individual leads until the final step of manufacturing the TAB tape, and to prevent the leads from being deformed in each step.

【0010】本発明では用いるマスクを本発明が要求す
る形状のマスクとすること、最終工程でリード先端部を
切断して各リードを独立させる以外は従来の工程がその
まま使用できる。具体的には、例えば、デバイスホール
が開けられた絶縁性フィルムに銅箔を貼り付け、その表
面にレジスト層を設け、本発明の要件を満たすマスクを
レジスト層に密接し、露光し、現像し、露出した銅箔部
をエッチングし、配線パターンを形成し、残存するレジ
スト層を除去して配線部を得る。
In the present invention, a conventional process can be used as it is, except that the mask used is a mask having the shape required by the present invention, and the leads are cut off at the final step to make each lead independent. Specifically, for example, a copper foil is attached to an insulating film having a device hole, a resist layer is provided on the surface thereof, a mask satisfying the requirements of the present invention is brought into close contact with the resist layer, exposed, and developed. Then, the exposed copper foil portion is etched to form a wiring pattern, and the remaining resist layer is removed to obtain a wiring portion.

【0011】その後、絶縁性フィルムエッチング用レジ
ストを全面に塗布し、所望のマスクを用いて露光し、現
像し、露出した絶縁性フィルム部をエッチングしてビア
ホール形成し、ビアホール部と配線部の所望部とにメッ
キを施し、ソルダーレジスト処理を行い、リード先端部
を金型やレーザ光を用いて切断する。
Thereafter, an insulating film etching resist is applied to the entire surface, exposed using a desired mask, developed, and the exposed insulating film portion is etched to form a via hole. The parts are plated, solder-resisted, and the ends of the leads are cut using a mold or laser light.

【0012】このようなTABテープを用いて半導体装
置を得るには、従来通り、半導体素子の電極とリード先
端とを結合し、樹脂封止する。このような半導体装置と
プリント配線板との接続はビアホールに設けた半田ボー
ル等を介して行う。
In order to obtain a semiconductor device using such a TAB tape, the electrodes of the semiconductor element and the ends of the leads are connected and sealed with a resin, as in the prior art. Such a connection between the semiconductor device and the printed wiring board is made via a solder ball or the like provided in a via hole.

【0013】本発明に用いる配線パターン例を図1、2
に示した。図1はリード先端部を全て連結したものの例
であり、図2はリード先端部を各辺ごとで連結したもの
の例である。いずれの例でも、リードの先端部分がつな
がっていることにより、リード毎に周辺部へメッキ導通
用の配線を配置する必要が無くなるため、配線の密度を
少なくすることができ、配線引き回し長さを短縮して設
計することができる。
FIGS. 1 and 2 show examples of wiring patterns used in the present invention.
It was shown to. FIG. 1 shows an example in which all the lead ends are connected, and FIG. 2 shows an example in which the lead ends are connected for each side. In any case, since the leading ends of the leads are connected, it is not necessary to arrange the wiring for plating conduction in the periphery for each lead, so that the wiring density can be reduced and the wiring length can be reduced. Design can be shortened.

【0014】(検討例)以下検討例を用いて本発明を説
明する。
(Study Example) The present invention will be described below using a study example.

【0015】用いたポリイミドフィルム1は厚さ125
μmの宇部興産製ユーピレックスS(商品名)であり、
接着剤2は厚さ12μmの巴川製紙所製Xタイプ、銅箔
3は厚さ18μmの日本電解製のU−SLPを使用し
た。ポリイミドフィルムに接着剤を貼り付けたものにデ
バイスホールを設け、次いでこれと銅箔とをラミネート
して銅ポリイミド基板を作製した。この銅ポリイミド基
板の銅箔面に感光性レジストを塗布し、リード数800
ピン、リード間ピッチ40μm、リード幅20μmにて
設計したマスクパターンを感光性レジスト層の表面に密
接し、露光し、現像した。次いで、露出した銅箔部をエ
ッチングして除去し、残存するレジスト層を除去して配
線部を作製した。このとき、デバイスホールへ片持ち状
に張り出している部分のリード長さを約0.5mmとな
るようにした。なお、フォトマスクを作成する際に、図
2に示したように、リードの先端部分4は各辺毎にリー
ド先端が接続されるようにし、各辺毎にメッキ導通用の
配線5を配置した。
The polyimide film 1 used has a thickness of 125
μm Ube Industries UPIREX S (trade name)
The adhesive 2 used was an X type having a thickness of 12 μm manufactured by Tomagawa Paper Mill, and the copper foil 3 used was a U-SLP manufactured by Nihon Denki having a thickness of 18 μm. A device hole was provided in a polyimide film to which an adhesive was attached, and then this was laminated with a copper foil to produce a copper polyimide substrate. A photosensitive resist is applied to the copper foil surface of this copper polyimide substrate, and the number of leads is 800
A mask pattern designed with a pin-to-lead pitch of 40 μm and a lead width of 20 μm was brought into close contact with the surface of the photosensitive resist layer, exposed and developed. Next, the exposed copper foil portion was removed by etching, and the remaining resist layer was removed to form a wiring portion. At this time, the lead length of the portion that cantilevered into the device hole was set to about 0.5 mm. When the photomask was prepared, as shown in FIG. 2, the tip 4 of the lead was connected to the tip of the lead for each side, and the wiring 5 for plating conduction was arranged for each side. .

【0016】次に基板全面にポリイミドエッチング用の
レジストを塗布し、ビアホール用マスクを密接し、露光
し、現像して露出したポリイミド部をエッチング除去
し、ビアホール底部の銅箔面と、配線の必要部とをメッ
キし、ソルダーレジスト処理を施し、その後リード先端
部の最内側より200〜300μmの部分を金型を用い
て切断して本発明の方法に従ったTABテープaを得
た。
Next, a resist for polyimide etching is applied to the entire surface of the substrate, a mask for via holes is closely contacted, exposed, developed, and etched to remove the exposed polyimide portions. The part was plated and subjected to a solder resist treatment. Thereafter, a part of 200 to 300 μm from the innermost part of the lead tip was cut using a mold to obtain a TAB tape a according to the method of the present invention.

【0017】次に、比較としてリード先端がそれぞれ分
離している従来タイプのリード数800ピン、リード間
ピッチ40μm、リード幅20μmにて設計したマスク
パターンを用いた以外は上記と同様にして従来法に従っ
たTABテープbを得た。
Next, as a comparison, a conventional method was used in the same manner as described above, except that a mask pattern designed with a lead number of 800 pins, a lead pitch of 40 μm, and a lead width of 20 μm was used. A TAB tape b according to the above was obtained.

【0018】TABテープaとTABテープbとの製品
歩留まりを比較したところ、リード変形の不良率はTA
BテープaはTABテープbの1/3以下であり、エッ
チング不良に関しては1/4以下という結果であった。
また、各リード間の位置精度に関しては、TABテープ
bがn=800で、平均で1μm、標準偏差で3μm、
TABテープaが、n=800で、平均で0.2μm、
標準偏差は0.7μmとなっており、本発明の方法に従
えば好結果を得ることができることが解った。
When the product yields of the TAB tape a and TAB tape b were compared, the defect rate of lead deformation was TA
The result of the B tape a was 1/3 or less of the TAB tape b, and the result of the poor etching was 1/4 or less.
Regarding the positional accuracy between the leads, n = 800 for TAB tape b, 1 μm on average, 3 μm for standard deviation,
TAB tape a has an average of 0.2 μm when n = 800,
The standard deviation was 0.7 μm, and it was found that good results could be obtained according to the method of the present invention.

【0019】本発明において、先端形状の接続パターン
は無限にあるが、基本的にリード先端部の接続させるた
めのパターン幅を50〜200μm程度とし、最終的に
リードを形成させるための切り落とし部分までの距離は
リード先端部の最内側より200〜300μmとすると
操作上好ましい。
In the present invention, the end-shaped connection pattern is infinite, but the pattern width for connecting the lead end portion is basically about 50 to 200 μm, and finally the cut-off portion for forming the lead is formed. Is preferably 200 to 300 μm from the innermost side of the tip of the lead.

【0020】[0020]

【発明の効果】本発明によれば、リード先端を連結した
パターンを用いて配線部を作製し、最後、あるいは半導
体チップを搭載する直前に当該連結部を切断するため
に、リード変形不良やエッチング不良などの不良率を低
減させることができ、その結果歩留まりを大幅に向上さ
せることができる。
According to the present invention, a wiring portion is formed using a pattern in which lead ends are connected, and the connection portion is cut at the end or immediately before mounting a semiconductor chip. The rate of defects such as defects can be reduced, and as a result, the yield can be greatly improved.

【0021】また、リード間ピッチの精度確保ができ、
組み立てでの歩留まり向上ももたらせられる。そして、
本発明は、リードピン数、リード間ピッチ、リード幅に
かかわらず、上記効果を発揮できるため、極めて有効で
ある。
Further, the accuracy of the pitch between leads can be ensured,
The yield in assembly can be improved. And
The present invention is extremely effective because it can exert the above effects regardless of the number of lead pins, the pitch between leads, and the lead width.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に用いる配線パターン例であり、リード
先端部を全て連結したものの例である。
FIG. 1 is an example of a wiring pattern used in the present invention, which is an example in which all lead ends are connected.

【図2】本発明に用いる配線パターン例であり、リード
先端部を各辺ごとで連結したものの例である。
FIG. 2 is an example of a wiring pattern used in the present invention, in which lead end portions are connected for each side.

【符号の説明】[Explanation of symbols]

1−−−ポリイミドフィルム 2−−−接着剤 3−−−銅箔 4−−−リード先端部分 5−−−メッキ導通用の配線 1 ---- Polyimide film 2--Adhesive 3--Copper foil 4--Lead tip 5--Plating wiring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】導電層が設けられた絶縁フィルムを用いて
フォトリソグラフ法によりTABテープを製造するに際
して、リードパターンを、リード先端部分がリード相互
に連結されたパターンとし、最終工程あるいは半導体素
子を搭載する前にリード先端部分の連結部を切断して各
リードを独立させることを特徴とするTABテープの製
造方法。
When a TAB tape is manufactured by a photolithographic method using an insulating film provided with a conductive layer, a lead pattern is a pattern in which a lead end portion is connected to a lead, and a final step or a semiconductor element is formed. A method for manufacturing a TAB tape, comprising cutting a connecting portion of a lead tip portion before mounting to make each lead independent.
JP21931298A 1998-08-03 1998-08-03 Manufacture of tab tape Pending JP2000058599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21931298A JP2000058599A (en) 1998-08-03 1998-08-03 Manufacture of tab tape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21931298A JP2000058599A (en) 1998-08-03 1998-08-03 Manufacture of tab tape

Publications (1)

Publication Number Publication Date
JP2000058599A true JP2000058599A (en) 2000-02-25

Family

ID=16733522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21931298A Pending JP2000058599A (en) 1998-08-03 1998-08-03 Manufacture of tab tape

Country Status (1)

Country Link
JP (1) JP2000058599A (en)

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