JP2000050059A - Image formation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer pixel data by a fixed pixel clock after executing the thinning or overlapping of the pixel data to be transferred and to accelerate the transfer of the pixel data further. SOLUTION: This image formation device is provided with a direct memory access(DMA) control part 22, a DMA bus, a page memory 21, an image output part for performing the variable power processing of reducing or enlarging image data and a recording part. The image output part is provided with a first pixel data buffer 24 for outputting the image data as the word unit of 16 pixels or 64 pixels, a second data buffer 26 capable of selectively outputting the pixel data of the word unit for respective individual pixels, a pixel variable power control part 25 for generating pixel address signals for performing the selection or overlapping processing of the pixel data outputted from the second data buffer 26 corresponding to a variable power rate in a main scanning direction and a pixel data selection part 27 for performing the selection or overlapping processing of the respective pixels outputted from the second data buffer 26 by the pixel address signals and outputting them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a copying machine or a facsimile which performs reduction or enlargement processing on received image data to output an image.

[0002]

2. Description of the Related Art Conventionally, there have been known image forming apparatuses such as copying machines and facsimile machines which perform reduction or enlargement processing on image data received from a host machine or the like to output an image. For example, Japanese Patent Application Laid-Open No. 6-278316 discloses an image forming apparatus in which a reduction in the main scanning direction is performed by thinning out a pixel clock for transferring pixel data. Hereinafter, a conventional method of reducing the pixel clock by thinning out the pixel clock will be described with reference to the drawings. FIG. 13 is a diagram illustrating a state on an image recording medium (paper) in a case where the B4 paper horizontal size is reduced to the A4 paper horizontal size by clock thinning and output. In FIG. 13, a pixel clock PCLK is supplied periodically, and a line synchronization signal LSYNC generated for each line is provided.
Is set in accordance with the transfer time of the pixel data of 297 mm width of the A4 paper. This line synchronization signal LSINC
Is related to the printing speed. Since high speed is required for the printing speed, the line synchronization signal LSINC
Should not be unnecessarily long. A at most
The normal line synchronization signal LSINC in an image forming apparatus capable of printing three sheets is 297 mm, which is the width of the short side (vertical) of A3 paper, that is, the width of the long side (horizontal) of A4 paper.
Is the basis of the cycle of the line synchronization signal. For example, if the line synchronizing signal has a cycle of 420 mm width of the A3 sheet, a longer printing time is required in proportion to the longer cycle, so that the image forming apparatus does not meet the demand for high printing speed. Therefore, in an image forming apparatus capable of printing A3 paper at maximum, the width of the short side of 297 mm of A3 paper is the basis of the cycle of the line synchronization signal, and the line synchronization signal LSYNC is set to the cycle of 420 mm width of the A3 paper. Is not a good idea. In FIG. 13, the period at which the line synchronization signal LSYNC is generated is A4
This is a time period in which pixel data on the side of the sheet can be transferred. In the uppermost diagram, the diagram on the side of the A4 sheet falls within one cycle. In the second drawing from the top of the B4 sheet, the hatched portion protrudes from the line synchronization signal LSYNC, and the pixel data in this hatched portion is not transferred because it does not enter one cycle of the line synchronization signal LSYNC. A at the bottom of B4 paper
In the figure reduced to four sheets horizontally, the line synchronization signal LSYNC is used.
, But in this case, A4
The hatched portion beside the sheet has no pixel data. When printing this reduced A4 paper landscape, if the portion without pixel data is initialized to a white image, the hatched portion is output as white, otherwise, the portion is transferred to the transfer portion of the previous print image. The remaining traces are printed as unknown images.

[0003]

As described above, in the method of reducing the width of the B4 paper to the width of the A4 paper by thinning out the clock, it is necessary to transfer the pixel data for one line by the width of the width of the B4 paper. Nevertheless, the line synchronization signal LS
Since the INC cycle is in the middle of the transfer, the pixel data in the shaded portion in FIG. 1 is not transferred. For this reason, a white output or an unknown image may be printed on a part of the image reduced to the A4 size. The present invention has been made in order to solve the conventional problems as described above, and performs pixel data transfer with a constant pixel clock after performing thinning or duplication of pixel data to be transferred. An object of the present invention is to provide an image forming apparatus capable of speeding up the transfer of pixel data.

[0004]

In order to achieve the above-mentioned object, an image forming apparatus according to the present invention of claim 1 exchanges data between a storage device and a processing device without passing through a central processing unit (CPU). A direct memory access (DMA) controller for directly transmitting and receiving, a DMA bus as a data transmission path controlled by the DMA controller, and image data transmitted via the DMA bus. A page memory, an image output unit that receives image data expanded in the page memory via the DMA bus and performs a scaling process to reduce or enlarge the image data, and a scaling process performed by the image output unit. An image forming apparatus having a recording unit that records image data on an image recording medium, wherein the image output unit transmits the image data transferred from the page memory every 16 pixels. A first pixel data buffer that outputs the word data of 64 pixels, a second data buffer that can output the image data of the word unit transferred from the first pixel data buffer for each individual pixel, and a scaling factor in the main scanning direction. A pixel scaling control unit for generating a pixel address signal for selecting or duplicating pixel data output from the second data buffer in response to each of the pixels output from the second data buffer; A pixel data selection unit that performs selection or overlap processing by a signal and outputs the selected data. According to a second aspect of the present invention, in the image forming apparatus of the first aspect, the DMA control unit includes:
A plurality of the word-based image data are transferred from the page memory in response to one request, and are stored in the first pixel data buffer. According to a third aspect of the present invention, in the image forming apparatus of the first aspect, the DMA control unit transfers one line of image data from the page memory in response to one request, and the first pixel data buffer is A line buffer control unit for controlling one line of pixel data is provided to store the one line of image data. The fourth aspect of the present invention provides the first to third aspects.
In the image forming apparatus according to any one of the above, the image output unit includes: an image control signal generation unit that generates a control signal for recording image data on the image recording medium in the recording unit; A line selection control unit for generating a line selection signal for performing line selection or overlap processing for each pixel data transferred according to the magnification and outputting the signal to the DMA control unit.

[0005]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image forming apparatus according to the present invention will be described based on an illustrated embodiment. FIG. 1 is a block diagram showing a schematic overall configuration of a digital copying machine which is an embodiment of the image forming apparatus of the present invention. As shown in FIG. 1, the image forming apparatus according to the present embodiment includes a central processing unit (CPU) 1 connected to a central processing unit bus (CPU bus) 6.
A read-only memory (ROM) 2, a work memory 3 including a RAM that is a readable / writable memory, a modem 4 that modulates and demodulates image data and the like for communication using a communication network, A network control unit 5 for communicating image data and the like via a communication network, and a DM capable of directly transmitting and receiving data between the memory and each device without the intervention of the CPU 1
A control unit 7, a code memory 9 for storing compressed image data and the like, a page memory 10 for expanding image data, an image compressing unit 11 for compressing image data, and an image expanding unit for expanding image data Unit 12, an image output unit 13 for converting the image data transferred through the DMA bus 8 into output image data, a recording unit 14 as an image data output device such as a printer,
An image input unit 15 for converting image data that can be transferred to a bus;
A reading unit 16 that reads an original image such as a scanner and converts the read image into image data.

The CPU bus 6 includes a CPU 1, a ROM 2,
A work memory 3 and a modem 4 are connected, and a DMA control unit 7 is connected.
Page memory 10, image compression unit 11, image decompression unit 12,
The image output unit 13 and the image input unit 15 are connected and D
The MA control unit 7 is connected, and the DMA control unit 7 is connected to bridge the CPU bus 6 and the DMA bus 8. The network control unit 5 is connected to the modem 4 and the communication line network, and
Is connected to the image compression unit 13, and the reading unit 16 is connected to the image input unit 15. DMA controller 7 and DMA bus 8
The reason for using the DMA transfer is as follows. That is,
For example, when reducing from B4 paper width to A4 paper width,
It is necessary to determine whether or not to thin out all the pixels on the side of the B4 sheet. Therefore, the line synchronization signal L
In one cycle of SYNC, that is, within the time corresponding to the number of pixels on the side of the A4 sheet, the number of pixels on the side of the B4 sheet must be aligned. To this end, pixel data must be transferred from the page memory 10 to the pixel data buffer at a high speed, which requires a DMA transfer.

FIG. 2 is a block diagram showing an image output unit according to the first embodiment of the present invention. In the first embodiment, the image data in the main scanning direction developed in the page memory of FIG. 1 is reduced or enlarged and output to the recording unit. The page memory 21 and the DMA control unit 22 in FIG. 2 are as described for the page memory 10 and the DMA control unit 7 in FIG. The remaining configuration of the image output unit includes a line selection control unit 23 that performs line selection for controlling the reduction and enlargement magnification in the sub-scanning direction in printing.
And a first pixel data buffer 24 for storing image data transferred by the DMA bus, and a pixel scaling for thinning out or overlapping pixel data for controlling a scaling factor for reduction and enlargement in the main scanning direction in printing. A control unit 25; a second pixel data buffer 26 for selectively outputting the stored image data for each individual pixel data;
A pixel data selection unit 27 that selects pixel data output from the second pixel data buffer 26 in accordance with the instruction, an image control signal generation unit 28 that outputs a control signal for controlling image data to be printed by the recording unit, A latch 29 for temporarily storing image data and outputting the image data in synchronization with a synchronization signal.

FIG. 3 is a block diagram showing the configuration of the pixel scaling control section in the configuration of FIG. The pixel scaling controller in FIG. 3 includes a counter 41 that counts a pixel clock.
And a register 42 for storing a scaling factor for reduction or enlargement, an adder 43 for adding predetermined conditions, a latch 44 for delaying the output result by one pixel clock, and comparing the output of the counter 41 with the output of the latch 44. A comparator 46 for outputting a signal of a predetermined condition, a latch 46 for outputting an operation permission signal of the pixel scaling control unit in accordance with a pixel clock, and an address generator 47 for generating an address of pixel data. You. Next, using the configuration of FIGS. 2 and 3, for example, B
A method of scaling the main scanning at the time of reduction, such as when the pixel data of a document of four paper width is reduced in the main scanning direction so as to fall within the A4 paper width, will be described. The pixel data expanded in the page memory 21 from the receiving unit is written to the first pixel data buffer 24 at the timing of the rise of the response signal DACK to the DMA request using the DMA transfer. Next, in order to perform scaling processing of pixel data,
The data is written to the second pixel data buffer 26 in synchronization with the pixel clock signal PCLK by the transfer signal LD from the pixel scaling control unit 25. At this time, if the pixel data is at the head of the line, the transfer signal LD is generated by the line start signal LINST in the address generator 47, and the pixel data is transferred from the first pixel data buffer 24 to the second pixel data buffer 26 in advance. Is performed. In the pixel scaling control section 25, a register 42 in which a scaling factor is set is set.
The pixel data address value HDA is also generated by the value of.
With the pixel data address value HDA, the pixel data selection unit 27 selects pixel data output from the second pixel data buffer 26 one pixel at a time in synchronization with the pixel clock signal PCLK. The latch 29 performs a gate process on the pixel data selected by the line valid period signal LGATE, and outputs the gate data to the recording unit in synchronization with the pixel clock signal PCLK. In this manner, the pixel data that has been thinned out in advance is transferred by a fixed pixel clock and the reduction in the main scanning direction is performed. Therefore, the problem that the pixel data is not transferred by the conventional clock thinning does not occur.

On the other hand, a method of changing the main scanning magnification at the time of enlargement such as when enlarging pixel data of a document of B5 paper landscape size to A4 paper landscape size is as follows. Pixel data is stored in the second
Up to the point where the data is written into the data buffer 26, the operation is the same as in the reduction. However, at the time of enlargement, a value of 1 or more is set in the register 42 in which the magnification is set, so that the pixel magnification control unit 25 generates a pixel data address value HDA having a cycle different from that at the time of reduction. . In the pixel data selection unit 27, the pixel data output from the second pixel data buffer 26 is synchronized with the pixel clock signal PCLK to overlap the pixels at the cycle of the pixel data address value HDA. The processing in the latch 29 is the same as that at the time of reduction.
In this way, the previously duplicated pixel data is transferred by a fixed pixel clock, and the enlargement in the main scanning direction is performed.

Here, the abbreviations used in this embodiment will be described in the order of ABC. Note that [10: 0], [15: 0], [20:
[0], [22: 0], and the like mean the values from 0 to the number in combination with the following abbreviations, and the numerical value represented by the combination with the abbreviation is in hexadecimal notation. ADD: Addition result (according to condition 3 described later). ADDV: Addition result (according to condition 7 described later). ADL: Value obtained by delaying ADD by one pixel clock. ADLV: Value obtained by delaying ADDV by one pixel clock (LSYNC). CAS: control signal for DRAM, column address strobe signal. CN: reference pixel count value in one line. The count-up value is 100 (hexadecimal). CNV: Reference pixel count value in one page. The count-up value is 100 (hexadecimal). D: A signal on the pixel data bus of one word (16 pixels or 64 pixels) output from the page memory. DACK: response signal to DMA request. DCY: a selection signal for any one of the four buffers. DMD: A signal on the pixel data bus from the first pixel data buffer to the second pixel data buffer. DMR: DMA request signal. Write instruction signal from image output unit. DMWR: DMA write signal. Write instruction signal on DMA bus. ESD: serial pixel data output to the recording unit. FGATE: One page write valid period. HCMPM: A signal for masking the HRDC signal to 0 at the head of the line. HD: a signal on the pixel data bus from the second data buffer to the pixel data selection unit.

HDA: Pixel data address value. The pixel data selection unit selects a pixel according to the address value. For example, HDA [3: 0] = 0 ... HD [0] = 1 ... HD [1]: = F ... HD [15] HEXT: A signal for switching the addition condition of HDA. HR: Register value of main scanning magnification. The scaling ratio is R, and 364 mm of B4 paper width is A4
When reducing the paper size to 297 mm, R = 297/364 = 0.816 0.816 × 256 = 208.9 ≒ 209 = d1 (16
Hex), the next value is set in HR. Integer part HR [10: 8] = 000 Decimal part HR [7: 0] = 11010001 The scaling factor is R, and 297 mm of A4 paper horizontal size is B4
When the size is expanded to 364 mm, which is the horizontal size of the paper, since R = 364/297 = 1.226 0.226 × 256 = 57.9 ≒ 58 = 3A (hexadecimal), the following value is set in HR. Integer part HR [10: 8] = 001 Decimal part HR [7: 0] = 001111010 HRC: Signal for switching the addition condition of HDA. HRC = HRDC & HCMPM: HR with HCMPM signal
The DC signal is masked by HRC at the head of the line.
To make the signal 0. HSD: Selected image data. HRDC: The ADD addition condition is switched together with the HEXT signal. KAKUDAI: Reduction / enlargement switching signal (for main scanning) LD: Data transfer signal from the first buffer to the second buffer LGATE: Line valid period signal, when "0" indicates an effective image range in one line. LINST: Line start signal synchronized with LSYNC LSYNC: Line synchronization signal (line sync) OE: DRAM control signal. Output enable signal. PCLK: Pixel clock signal. This signal is generated from the recording unit and is used to capture pixels, and is independent of the CPU clock. PMSYNC: a line synchronization signal from the recording unit RAS: a control signal for DRAM. Row address strobe signal. RSTHR: The operation permission signal of the variable power control unit is valid only during one line. RSTVR: An operation permission signal of the line selection control unit is valid only during one page. SL: selected line value (current line value, next line value,...) SUBUKAKU: reduction / enlargement signal (for sub-scanning) VCMPM: signal for masking the VRDC signal to 0 at the top of the page. VEXT: Line switching signal VR: Sub-scanning magnification change register value VRC: Line switching signal VRDC: Addition condition of ADDV is switched together with VEXT signal. WCLK: Determines the image data transfer speed.

Further, the conditions of the pixel scaling control unit in this embodiment are determined as follows. Condition 1: Switching of reduction / enlargement in the pixel scaling control unit When HR [10: 8] ≧ 1, KAKUDAI = 1 (H level), and when HR [10: 8] = 0, KAKUDAI = 0 (L level), reduction condition 2: comparison condition of a comparator in the pixel scaling control unit: KADCAI = 0, CN <ADL, HRDC = 0, HEXT = 1, When CN ≧ ADL, HRDC = 1, HEXT = 1 When KAKUDAI = 1 and CN <ADL, HRDC = 0, HEXT = 0 When CN ≧ ADL, HRDC = 0, HEXT = 1 Condition 3: Addition condition of the adder in the pixel scaling control unit KAKUDAI = 0 and HRDC When = 0, ADD = ADL + HR When HRDC = 1, ADD = ADL + (HR × 2) When KAKUDAI = 1 and HEXT = 0, when ADD = ADL HEXT = 1, AD = ADL + HR Condition 4: Generation condition of address generator in pixel scaling control section HRC = HRDC & HCMPM HRC = 0, HEXT = 0: (duplicate), HDA = HDA: Next address is current address HRC = 0, HEXT = 1: (no thinning or duplication), HDA = HDA + 1: Next address generates next address of current address HRC = 1, HEXT = 1: HDA = HDA + 2: The next address generates the next address following the current address. Condition 5: Switching of reduction / enlargement in the line selection control unit When VR [10: 8] ≧ 1, SUBKAKU = 1 (H level), 1: 1 and enlargement VR [10: 8] = 0, SUBKAKU = 0 (L level), reduction Condition 6: Line selection control unit Comparison conditions of the comparator in SUBKAKU = 0 and CNV <ADLV, VRDC = 0, VEXT = 1, when CNV ≧ ADLV, VRDC = 1, VEXT = 1, when SUBKAKKU = 1 and CNV <ADLV, VRDC = 0, VEXT = 0 When CNV ≧ ADLV, VRDC = 0, VEXT = 1 Condition 7: Addition condition of the adder in the line selection control unit When SUBKAKU = 0 and VRDC = 0, ADDV = ADLV + VR When VRDC = 1, ADDV = ADLV + (VR × 2) SUBKAKU = 1 and VEXT = 0, ADDV = ADLV VEXT = 1, ADDV = ADLV + VR Condition 8: Line selection condition in the line selection control section VRC = VRDC & VCMPM LSYNC = VRC = 0, VEXT = 0 : (Duplicate), SL = SL: next line selects same line as current line When VRC = 0, VEXT = 1: (no thinning or duplication), SL = SL + 1: next line is current line VRC = 1, VEXT = 1: (thinning out), SL = SL + 2: the next line selects the next line following the current line. In each embodiment of the present invention, The processing of each part is performed according to the conditions.

FIG. 4 is a timing chart when the image size in the main scanning direction is reduced in the configuration shown in FIGS. In FIG. 4, 0D is stored in the scaling register 42 of FIG.
A timing chart is shown in the case where 1 (hexadecimal) is set and the size is reduced from the B4 paper horizontal size to the A4 paper horizontal size. HRC = 1 when HDA = 5, H
A thinning condition of EXT = 1 has occurred. Therefore, in the next address, HDA = 6 (hexadecimal) is skipped and HDA = 7 (hexadecimal). Similarly, HDA = B (16
Hex) and HDA = C (hex), the next word HDA = 1 (hex) is skipped and HDA = 2 (16)
Hex). Thus, the serial pixel data ES
From D, D1 [6], D1 [11], D2 [1], D2
[6],... (D1, D2, D3,... Are each word, and [number] indicates the number of pixel data in the word) are thinned out and pixel data is output to the recording unit. You. D
The change on the MD is performed at the timing of the rising edge of the DMWR.
This is performed at the rising edge of PCLK. The DMA request is generated when the pixel address is in the middle of one word (the seventh pixel), and the LD becomes 1 when the pixel address becomes F (hexadecimal). Also, the ESD is masked by LGATE to be 1 when LGATE is not valid.

The timing chart of FIG.
5 is a timing chart when the image size in the main scanning direction is enlarged in the configuration of FIG. FIG. 5 shows a case where 13A (hexadecimal) is set in the scaling ratio register 42 of FIG. HRC = 0, HEXT = 0 when HDA = 1
Duplicate condition has occurred. Therefore, the next address becomes HDA = 1 (hexadecimal) again. At that time, the above-mentioned overlapping condition has been eliminated, and the next address becomes HDA = 2 (hexadecimal). Similarly, HDA =
5 (hex), HDA = 9 (hex), HDA = E (1
Hex) overlaps. Thus, from the serial pixel data ESD, D1 [1], D1 [5], D1 [9],
D1 [14],... Are overlapped and the pixel data is output to the recording unit. In FIG. 5, HDA, HSD,
A blank portion such as an ESD means that the previous pixel overlaps.

FIG. 6 is a block diagram showing an image output unit according to a second embodiment of the present invention in which four words of pixel data can be transferred to the first pixel data buffer by one DMA request. In this case, the first pixel data buffer 30 has 4 words (4 pieces) of 16 pixels.
, And can accumulate pixel data of 64 pixels. Similarly, the second pixel data buffer 31
Accumulation of 64 pixels and output for each pixel are possible.

The DMA controller 22 causes four words of pixel data to be transferred by one DMA request DMR.
The selection signal DCY for any one of the four buffers of the first pixel data buffer 30 is output. FIG.
7 is a timing chart in the configuration of FIG. D
From the MA control unit 22, DMR, DACK, selection signal D
A DMA write signal DMWR is output together with CY. D
First pixel data buffer 3 at the rise of MWR
Write to 0. The DMR rises when the last word data in one DACK is selected. DC
With two bits of Y, one of the four buffers is selected and D
At the rise of the MWR, pixel data for one word such as D1 to D4 is taken into the first pixel data buffer 30. By enabling the transfer of multi-word pixel data at a time as in the second embodiment, the interval between DMA requests can be extended, and the number of arbitrations of the DMA bus can be reduced.
Since the addition of the DMA bus can be reduced, the transfer of pixel data can be speeded up.

FIG. 8 is a block diagram showing an image output unit according to a third embodiment of the present invention, in which one line of pixel data can be transferred to the first pixel data buffer by one DMA request. In this case, the first pixel data buffer 33 includes a buffer (line buffer) for one line and a line buffer control unit 34.
One line of pixel data can be stored. The DMA control unit 22 causes one line of image data to be transferred by one DMA request DMR, and outputs a DACK and a DMWR signal to the line buffer control unit 34. The line buffer control unit 34 controls the line buffer of the first pixel data buffer 33. FIG. 9 is a timing chart in the configuration of FIG. From the DMA control unit 22, D
DMWR is output together with MR and DACK. Also, DR
The page memory 21 is controlled by the AM control signals RAS, CAS, and OE. First at the rise of DMWR
Writing to the pixel data buffer 33 is performed. The relationship between the control signals RAS, CAS, OE and address is based on the AC characteristics of the DRAM. The DMWR signal has a timing at which the output from the DRAM is captured at the rising edge of the signal. Since the first pixel data buffer is a line buffer, DACK is used as a line buffer enable signal and DMWR is used as a line buffer clock. One line of image data is set in the page memory 21 for each row address. In a high-speed page mode in which only a column address is changed from the page memory 21 by one DMA request, one line of pixel data is transferred to a first pixel data buffer (line buffer) 3.
Transfer to 3. By enabling the transfer of one line of pixel data at a time as in the third embodiment, the DM
Reduce the number of A requests to one per line, and DMA
The number of bus arbitrations can be reduced to one per line,
Since the addition of the DMA bus can be reduced, the transfer of pixel data can be speeded up.

FIG. 10 shows, as a fourth embodiment of the present invention, a line selection control unit in the case where a circuit having a configuration similar to the pixel scaling control unit of FIG. 3 is used for the line selection control unit of FIG. FIG. In FIG. 10, the counter 51
The input to the register is LSYNC and RSTVR, and the value set in the register 52 is the magnification in the sub-scanning direction.
The output from the comparator 55 does not pass through the address generator as shown in FIG. 3, and VEXT for enlargement is output as it is, and VRDC for reduction is output from the mask unit 5 by VCMPM.
At 7, the first fall is output as a masked VRC. The other configuration of the line selection control unit is the same as the configuration of the pixel scaling control unit in FIG. 3 except that the signal from the register 52 to the adder 53 is changed due to the difference between the original signal and the setting in the register 52. Becomes VR and SUBKAKU, the signal from the adder 53 to the latch 54 becomes ADDV, and the signal from the latch 54 to the comparator 55 and the adder 53 becomes ADLV.
And the signal from the counter 51 to the comparator 55 is CNV
And the signal from the latch 56 to the mask unit 57 is VCM
Become PM. The DMA control unit receiving the selection line signal from the line selection control unit calculates the start address of each line in the image data on the page memory.
Then, as the start address of the next line, either the same address as the current line in the case of enlargement, the address of the next line of the current line in the normal case, or the address of the next line after the current line in the case of contraction Or choose.

FIG. 11 is a timing chart when the image size is reduced in the sub-scanning direction in the configuration of FIG. As described in the description of FIG. 10, the pixel clock PCLK in the case of the main scanning direction in FIG. 4 is a line synchronization signal LSYNC, and similarly, the operation permission signal RSTHIR of the variable power control unit is controlled by the line selection control. Becomes the operation permission signal RSTVR. Other signals in the main scanning direction in FIG. 4 are also as described in the description of FIG. Further, the pixel data address value HDA becomes the selected line value SL. VRC = 1, VEX when SL = 5
A thinning-out condition of T = 1 has occurred. Therefore, in the next line, SL = 6 is skipped and SL = 7. Similarly, SL = 11 is skipped and SL = 12, SL = 17 is skipped and SL = 18 and SL = 22 are skipped and SL =
23. In this way, the line in the sub-scanning direction is thinned out, and the pixel data is output to the recording unit, whereby the paper size is reduced. The timing chart of FIG. 12 shows a case where the image size is enlarged in the sub-scanning direction in the configuration of FIG. VRC when SL = 1
= 0 and VEXT = 0 have occurred. Therefore, the next line becomes SL = 1 again, and at that time, since the above-mentioned overlapping condition has been eliminated, the next line becomes SL = 2 (hexadecimal). Similarly VDA
= 5, VDA = 9, and VDA = 14 overlap. In this way, the line in the sub-scanning direction is overlapped, and the pixel data is output to the recording unit, thereby enlarging the paper size. By configuring the line selection unit as in the fourth embodiment, it is possible to realize a scaling process at an arbitrary magnification in the sub-scanning direction with a simple circuit configuration.

[0020]

As described above, according to the first aspect of the present invention, pixel data can be thinned out or overlapped under a constant pixel clock within the period of the line synchronization signal in the main scanning magnification change. Therefore, a neglected image unlike the case where the pixel clock is thinned out does not occur, and reduction and enlargement can be realized by a common simple circuit configuration. According to the second aspect of the present invention, in the main scanning magnification change, one DMA transfer is performed.
The request makes it possible to transfer a plurality of words of pixel data to the pixel data buffer.
The transfer of image data can be speeded up by reducing the load on the bus. According to the third aspect of the present invention, in the main scanning magnification change, the line buffer is used as the pixel data buffer, and one line of pixel data can be transferred to the pixel data buffer by one DMA request. Therefore, the load on the DMA bus can be further reduced to speed up the transfer of image data. According to the fourth aspect of the present invention, a configuration substantially similar to that of the pixel scaling control unit is used for the line selection control unit. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic overall configuration of a digital copying machine which is an embodiment of an image forming apparatus of the present invention.

FIG. 2 is a block diagram illustrating an image output unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a pixel scaling control unit in FIG. 2;

FIG. 4 is a timing chart when the image size in the main scanning direction is reduced in the configurations of FIGS.

FIG. 5 is a timing chart when the image size in the main scanning direction is enlarged in the configurations of FIGS.

FIG. 6 is a block diagram showing an image output unit according to a second embodiment of the present invention in which four words of pixel data can be transferred to a first pixel data buffer by one DMA request;

FIG. 7 is a timing chart in the configuration of FIG. 6;

FIG. 8 is a block diagram illustrating an image output unit according to a third embodiment of the present invention in which one line of pixel data can be transferred to a first pixel data buffer by one DMA request.

FIG. 9 is a timing chart in the configuration of FIG. 8;

10 is a block diagram showing a line selection control unit when a circuit having a configuration similar to that of the pixel scaling control unit in FIG. 3 is used as the line selection control unit in FIG. 2 as a fourth embodiment of the present invention; It is.

11 is a timing chart in the case of reducing the image size in the sub-scanning direction in the configuration of FIG.

FIG. 12 is a timing chart when the image size is enlarged in the sub-scanning direction in the configuration of FIG.

FIG. 13 is a diagram illustrating a state on an image recording medium (paper) when a B4 paper horizontal size is reduced to a A4 paper horizontal size by clock thinning and output.

[Explanation of symbols]

1 CPU, 2 ROM, 3 work memory, 4 modem, 5 network control unit, 6 CP
U bus, 7, 22 DMA controller, 8 DMA
Bus, 9 code memory, 10, 21 page memory, 11 compressed image section, 12 image expansion section,
13 ... image output unit, 14 ... recording unit, 15 ...
Image input unit, 16 reading unit, 23 line selection control unit, 24, 30, 33 first pixel data buffer, 25 pixel scaling control unit, 26, 31, 35
... Second pixel data buffer, 27, 32, 36, ...
A pixel data selection unit, 28 ... an image control signal generation unit,
29, 44, 46, 54, 56 ... latch, 34 ...
.Line buffer control units, 41, 51... Counters
42, 52 ... register, 43, 53 ... adder,
45, 55: comparator, 47: address generator,
57 ... mask part

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 1/21 G06F 15/66 355D

Claims (4)

[Claims] 1. A direct memory access (DMA) control unit for directly transmitting and receiving data between a storage device and a processing device without passing through a central processing unit (CPU), and controlled by the DMA control unit. A DMA bus, which is a transmission path of data to be transferred, a page memory for expanding image data transmitted via the DMA bus, and receiving the image data expanded in the page memory via the DMA bus to receive the image. An image forming apparatus comprising: an image output unit that performs a scaling process for reducing or enlarging data; and a recording unit that records the image data that has been subjected to the scaling process in the image output unit on an image recording medium. A first pixel data buffer for outputting the image data transferred from the page memory as a word unit of 16 pixels or 64 pixels; and a first pixel data buffer. A second data buffer capable of outputting the image data in word units transferred from the data buffer for each individual pixel, and selecting or overlapping the pixel data output from the second data buffer according to the magnification in the main scanning direction. And a pixel data selection unit for selecting or outputting each pixel output from the second data buffer by using the pixel address signal or performing an overlap process. Image forming apparatus. 2. The method according to claim 1, wherein the DMA control unit transfers the plurality of word-unit image data from the page memory in response to one request, and stores the image data in the first pixel data buffer. The image forming apparatus as described in the above. 3. The DMA controller transfers one line of image data from the page memory in response to one request.
2. The first pixel data buffer includes a line buffer control unit that controls the one line of pixel data, and stores the one line of image data. 3.
An image forming apparatus according to claim 1. 4. The image output unit includes: an image control signal generation unit configured to generate a control signal for recording image data on the image recording medium in the recording unit; 4. A line selection control unit for generating a line selection signal for performing line selection or overlap processing for each pixel data and outputting the line selection signal to the DMA control unit. Item 10. The image forming apparatus according to item 1.