JP2000049340A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and a fabrication method thereof, having a sidewall structure for which damages in the shape of the gate electrode and short circuit between the gate electrode and a metal electrode in a contact hole can be prevented at etching of a self-aligned contact hole without sacrificing reliability of a transistor. SOLUTION: This semiconductor device comprises an electrode wiring composed of lower conductive film of tungsten polyside 11 and a first upper insulating film of silicon nitride 13 formed on a silicon substrate 1, a second insulating film of silicon nitride 15 formed contiguously to the sidewall of the electrode wiring, a third insulating film of silicon oxide 14 formed between the silicon nitride 15 and the silicon substrate 1, a fourth insulating film formed as an interlayer insulating film while covering at least the electrode wiring, the sidewall thereof and the second insulating film, and a contact hole 17 made in the fourth insulating film while partially lapping over the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Metal-Oxide-Semiconductor
r) A semiconductor device having a structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, for example, along with the high integration and miniaturization of patterns of MOS type semiconductor devices, it has become difficult to align a mask of a contact for interconnecting a wiring such as a gate electrode or an upper wiring and a substrate. In order to cope with this, the wiring such as the gate electrode is covered with an insulating film such as silicon nitride,
Using this as an etching stopper film, a self-aligned contact (hereinafter referred to as S
A technique called AC) is being considered.

Hereinafter, a conventional semiconductor device and a method of manufacturing the same will be described with reference to the drawings. FIG. 5 is a cross-sectional view showing an example of a conventional semiconductor device, which is manufactured by using the SAC technique. The semiconductor device shown in FIG. 5 has a gate oxide film 110 on the surface of P-type silicon substrate 1.
And a conductive electrode wiring made of tungsten polycide 111 in which the lower layer is made of a polysilicon film and an upper layer made of tungsten polycide, an insulating film made of silicon oxide 112 and silicon nitride 113 on the upper part thereof, and an electrode wiring side wall part. It is composed of a side wall insulating film (hereinafter referred to as a side wall) of silicon oxide 114 and silicon nitride 115 formed in a self-aligned manner. An interlayer insulating film 116 is formed on the gate electrode having this structure to form a contact hole 117.
Are formed, and a metal electrode 118 is formed in the contact hole 117 by the SAC technique.

A semiconductor device having such a structure is manufactured as follows. FIG. 6 is an explanatory view of a first step in a conventional method of manufacturing a semiconductor device, and FIG. 7 is an explanatory view of the second step, showing a manufacturing step of the semiconductor device manufactured by using the SAC technique.

First, as shown in FIG. 6A, a gate oxide film 110 is deposited on the surface of a P-type silicon substrate 101. Next, as shown in FIG. 6B, after a tungsten polycide 111 serving as a gate electrode is formed, silicon oxide 112 and silicon nitride 113 are deposited as a protective insulating film serving as an SAC etching stopper in a later step. After the application of the resist, the resist 120 is patterned using a mask of the gate electrode. Next, as shown in FIG. 6C, the silicon nitride 113, the silicon oxide 11
2. The tungsten polycide 111 is sequentially etched to remove the patterned resist 120, thereby forming a gate electrode.

Next, as shown in FIG. 6D, silicon oxide 114 and silicon nitride 115 are deposited as sidewalls on the side walls of the gate electrode, and then the insulating film is entirely etched back to form a self-aligned film. Is formed. This sidewall is shown in FIG.
As shown in (e), the gate electrode protective insulating film is not only used as a mask when implanting impurities for alleviating the electric field between the source and the drain, but also against the etching when the contact hole 117 is opened in the vicinity of the gate electrode. Also serves as a role.

After that, as shown in FIG. 7A, an interlayer insulating film 116 containing silicon oxide as a main component is deposited to cover the gate electrode, and a resist pattern 121 for the contact hole 117 is formed. Then, as shown in FIG. 7B, the interlayer insulating film 116 is selectively etched using the resist pattern 121 as a mask, a contact hole 117 is opened, and finally, a metal electrode 122 mainly containing aluminum is formed. .

[0008] As described above, in the conventional process, the composite film of silicon nitride 115 and silicon oxide 114 is used for the side wall so as not to adversely affect the reliability and high-speed operation of the transistor. For example, when only silicon nitride is used for the sidewall of the sidewall, the silicon nitride film has a high dielectric constant, and when the silicon nitride film and the silicon substrate come into direct contact, an interface state is generated at the interface between the silicon substrate surface and the silicon nitride. Also, since a large number of trap centers for capturing electrons or holes are present in the silicon nitride film, hot carriers generated during the operation of the MOS transistor are trapped in the interface states or trap centers in the silicon nitride film. Then, the threshold voltage (Vt) of the transistor may fluctuate, or the hot electron resistance of the transistor may be degraded, thereby adversely affecting the reliability and high-speed operation of the transistor.
This problem can be solved by forming the side wall of the composite film as described above, because the silicon nitride film and the silicon substrate do not come into direct contact with each other.

[0009]

However, such a semiconductor device and its manufacturing method have the following problems.

(1) When sidewalls are formed in a self-aligned manner by etching back the entire surface of the silicon oxide 114 and the silicon nitride 115, different film types of the silicon oxide 114 and the silicon nitride 115 are simultaneously etched. And it is difficult to control the sidewall shape.

That is, oxygen is released from the silicon oxide 114 during this etching, so that the etching rate of the silicon nitride on the gate electrode shoulder 115 '(see FIG. 6E) increases, and the silicon nitride film This is because the shaving becomes large. When this is compared with the shape when only silicon nitride is deposited as a sidewall insulating film to the same thickness and etched, the gate electrode shoulder 11
The amount of the remaining silicon nitride film 5 ′ is reduced, and this reduction reduces the overetching margin when the contact hole 117 is opened after the gate electrode partially overlaps with the gate electrode. Of the silicon nitride film.

(2) When the contact hole 117 is opened in the interlayer insulating film 116, the contact hole 117
As shown in FIG. 7B, when the silicon nitride film partially overlaps with the sidewall and is exposed by etching,
A phenomenon in which the silicon nitride 115 and the silicon oxide 114 are etched abnormally fast is observed. This is because the etching rate of the silicon oxide film 114 is high in the etching of the contact hole 117, so that the silicon oxide is selectively etched during the etching to form a slit, and further, the gate electrode shoulder 115 ′ is formed in the sidewall forming step. Silicon nitride 11 in addition to missing
It is considered that 5 itself was also etched. In this way, the side wall of the tungsten polycide 111 of the gate electrode is exposed, and short-circuit with the metal electrode 122 is caused (see the broken line portion in FIG. 7B). When the contact hole 117 has a high aspect ratio of about 0.2 μm or less in diameter and a depth of about 0.8 μm to 1 μm, etching of the side wall becomes particularly remarkable.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and damages the shape of a gate electrode during etching of a self-aligned contact hole, does not impair the reliability of a transistor, and removes a gate electrode and a metal electrode in the contact hole. It is an object of the present invention to provide a semiconductor device having a sidewall structure capable of preventing a short circuit with the semiconductor device and a method of manufacturing the same.

[0014]

According to the present invention, there is provided a semiconductor device comprising:
An electrode wiring formed on a semiconductor substrate, the lower part of which is formed of a conductive film such as polycide, and the upper part is formed of a first insulating film such as silicon nitride, and silicon nitride formed in contact with a side wall of the electrode wiring , A third insulating film such as silicon oxide inserted between the second insulating film and the semiconductor substrate, at least an electrode wiring, a side wall thereof, and a second insulating film. A fourth insulating film formed so as to cover the film to form an interlayer insulating film, and a contact hole provided in the fourth insulating film so as to partially overlap the electrode wiring.

According to the present invention, the insulating film of the side wall of the gate electrode wiring is one kind of the second insulating film, and since there is no different kind of film, abnormally fast etching of the film does not occur, and the metal electrode and the metal electrode are not etched. Short circuit of the gate electrode can be prevented. In addition, since the third film such as silicon oxide is inserted between the second insulating film and the semiconductor substrate, there is no interface state or trap, and high reliability can be secured.

According to a method of manufacturing a semiconductor device of the present invention, an electrode wiring layer is formed on a semiconductor substrate, the lower portion being formed of a conductive film such as polycide and the upper portion being formed of a first insulating film such as a silicon nitride film. A second insulating film such as a silicon oxide film is formed on the semiconductor substrate including on the electrode wiring, and a portion formed on a side wall of the electrode wiring of the second insulating film is, for example, a silicon nitride film. A step of changing the quality, a step of forming a third insulating film such as a silicon nitride film on the side wall of the electrode wiring, and a step of forming a fourth insulating film such as a silicon oxide film on the electrode wiring region and other semiconductor substrate regions. The method includes a step of forming a film, selectively etching the film, and providing a contact hole so as to partially overlap the electrode wiring.

According to the present invention, for example, the second insulating film such as a silicon oxide film is transformed into a silicon nitride film similar to the third insulating film on the side wall of the electrode wiring. Is one type of silicon nitride film, and no slit is formed in the contact etching. Further, since the substrate surface portion of the second insulating film can be left without being nitrided, the second insulating film and the semiconductor substrate do not come into direct contact with each other, and high reliability can be secured.

[0018]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention, and shows a gate electrode portion of a MOS transistor.

The semiconductor device shown in FIG. 1 has a conductive electrode wiring serving as a gate electrode composed of a gate oxide film 10 and a tungsten polycide 11 on the surface of a P-type silicon substrate 1, and a silicon oxide 12 and a nitride An insulating film made of silicon, a thin silicon oxide film and a silicon nitride film formed on a side wall of the gate electrode in a self-aligned manner, and an interlayer insulating film formed on the gate electrode; 16 has a contact hole 17
Are provided, and a metal electrode 18 mainly composed of aluminum is provided. In this configuration, the portion of the sidewall that contacts the metal electrode 18 is only silicon nitride, and there is no silicon oxide film as in the above-described conventional device.
At the bottom of the sidewall, silicon oxide 14
Is characterized in that it is thinly left between the silicon substrate 1 and the silicon nitride 15.

FIG. 2 is an explanatory view of a first step in an embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIG. 3 is an explanatory view of a second step in the method of manufacturing the semiconductor device shown in FIG. Is shown.

First, as shown in FIG. 2A, a gate oxide film 10 having a thickness of, for example, 5 nm is deposited on a P-type doped silicon substrate 1. Next, as shown in FIG. 2B, a tungsten polycide 11 serving as a gate electrode is formed by, for example, WSi / DPS = 100/10 by a low-temperature CVD method.
Deposited with a thickness of 0 nm (DPS: phosphorus-doped polysilicon). Next, silicon oxide 12 and silicon nitride 13 are deposited as an electrode protection insulating film by, for example, 20 nm and 200 nm, respectively, using a CVD method. Silicon oxide 12
It is deposited by a mixed gas of tetraethoxysilane (hereinafter referred to as TEOS) and oxygen or ozone. Thereafter, a resist 20 is applied, and the resist 20 is patterned using a mask of the metal electrode 18.

Next, as shown in FIG. 2C, dry etching of the silicon nitride 13, the silicon oxide 12, and the tungsten polycide 11 is sequentially performed to remove the patterned resist 20.

Next, as shown in FIG. 2D, a silicon oxide 14 is deposited from TEOS and oxygen / ozone gas to a thickness of, for example, 20 nm on a flat surface by a CVD method.
Here, the silicon oxide 14 has a gate electrode side wall portion (vertical surface) larger than the film thickness of the flat portion (portion without a gate pattern).
It is important to deposit under such conditions that the film thickness becomes thin. Note that the state shown in FIG. 2D shows a state after the silicon oxide 14 is nitrided and a silicon nitride 15 is deposited, which will be described later. It has become. Such deposition conditions can be achieved by appropriately setting the pressure and temperature in the reaction chamber in the low pressure CVD method. According to specific experiments by the inventors, when the coverage ratio of silicon oxide was compared between the flat portion and the side wall of the gate electrode, the coverage ratio of the latter was approximately 60% to 70% as compared with the former (the film thickness was reduced). 12-14 nm).

Next, the silicon oxide 14 is subjected to a uniform nitriding treatment. This treatment is performed in the next step by the reaction of a CVD apparatus for depositing the silicon nitride 15 for the side wall using a gas containing NH _3. Perform indoors. That is, nitridation is performed in an NH ₃ purge step performed after depositing the silicon oxide 14 and before depositing the silicon nitride 15. The NH ₃ purge is a step of introducing NH ₃ gas as a raw material during the growth of silicon nitride.

For the nitriding treatment, it is not always necessary to use a silicon nitride CVD apparatus as described above, and an independent apparatus for processing or another apparatus capable of introducing NH ₃ can be used. However, a method using a silicon nitride CVD apparatus is desirable in terms of continuity with the next step and processing time. Note that a nitrogen gas other than NH ₃ may be used.

In examining the conditions for nitriding the silicon oxide 14, NH ₃ purge conditions during the formation of the silicon nitride 15 were examined. Figure 4 is a diagram showing the nitriding properties of silicon oxide in an embodiment of the method for manufacturing a semiconductor device of the present invention, the flow rate of NH ₃ and 600sccm constant, NH ₃
The result of plotting the nitriding amount of silicon oxide with respect to the purge time is shown. The nitride amount and NH ₃ purge time of the silicon oxide located approximately linear relationship, for example, NH ₃
When the purge time was 5 min, the nitridation amount of silicon oxide was about 7 nm, and when the NH ₃ purge time was 10 min, the nitridation amount of silicon oxide was about 14 nm. Therefore, the NH ₃ purge time was set to 10 min in the case where silicon oxide was deposited with a thickness of 20 nm, that is, in order to completely nitride the silicon oxide film with a thickness of 14 nm on the pattern side wall. At this time, unnitrided silicon oxide is left in the flat portion, approximately 6 nm thicker than the gate oxide film thickness (5 nm).
In this way, as shown in FIG. 2D, the silicon oxide remains only on the flat portion. Then, silicon nitride 15 is deposited to a thickness of about 140 nm by a chemical vapor deposition method using NH ₃ and silane, so that the silicon substrate 1 and the silicon nitride 15 are deposited.
To realize a configuration that does not directly contact

Next, as shown in FIG. 2E, the entire surface of the composite film of silicon nitride 15 and silicon oxide 14 is etched back by reactive ion etching to form sidewalls. At this time, the remaining amount of silicon nitride on the shoulder of the gate electrode was about 130 nm. In the conventional manufacturing method, the remaining film amount is about 70 nm, and the remaining film amount is about twice as large as this. This is presumably because the silicon oxide film was not in contact with the side wall of the gate electrode, so that the etching of the silicon nitride 15 was not accelerated.

Next, as shown in FIG. 3A, an interlayer insulating film 16 made of non-doped silica glass (NSG) is deposited on the gate electrode by bias sputtering, and the resist pattern 2 is formed using a contact hole pattern mask.
Form one.

Further, as shown in FIG.
6 is etched under an etching condition in which the etching rate ratio to silicon nitride 15 is increased, and when the resist pattern 21 is removed, a contact hole 17 overlapping the gate electrode in a self-aligned manner is completed. A metal electrode 18 such as a metal alloy, a refractory metal or a silicide thereof, or a semiconductor film is formed.

In this step, the silicon nitride 15 on the side wall shoulder remains sufficiently in the step shown in FIG. 2E, and the silicon oxide 14 is not present on the side wall of the gate electrode. Even if the etching is performed, the silicon nitride 15 is not quickly removed, and no short circuit occurs between the gate electrode and the metal electrode 18 in the contact hole 17.

As described above, the semiconductor device according to the present embodiment has a structure in which there is no silicon oxide layer which causes an increase in the amount of silicon nitride shaved off at the shoulder of the electrode when the entire surface of the sidewall is etched back. In addition, the silicon nitride on the electrode shoulder is not scraped, and at the same time, the contact hole etching eliminates the rapid etching of the side wall due to the silicon oxide etch that was present when the silicon oxide layer was present on the electrode shoulder. No etching occurs, and no short circuit occurs between the gate electrode and the metal electrode. In addition, since the unnitrided silicon oxide thicker than the gate oxide film remains at the bottom of the sidewall, contact between the silicon nitride and the silicon substrate is prevented, and a highly reliable transistor having no interface order or trap can be obtained. In addition, the semiconductor device can operate at high speed.

Next, according to the method of manufacturing a semiconductor device in the present embodiment, the second insulating film such as a silicon oxide film is transformed into a silicon nitride film similar to the third insulating film on the side wall of the gate electrode. Therefore, it is substantially the same as forming a single film on the side wall of the gate electrode, and no slit is formed in the contact hole etching. Further, since the substrate surface portion of the third insulating film can be left without being nitrided, contact between silicon nitride and the silicon substrate is prevented, and high reliability can be secured.
In the step of transforming the second insulating film, nitriding is employed, and the second insulating film is formed so that the surface of the semiconductor substrate is thicker than the side wall of the gate electrode, and the nitriding is performed uniformly. The thickness of the gate electrode side wall,
While the entire insulating film is nitrided, the non-nitrided portion can be specifically left on the surface of the semiconductor substrate due to its large thickness. Further, by performing the nitridation using a device for forming a third insulating film such as the nitride film and using a nitriding gas for forming the third insulating film,
It is possible to combine the nitridation and the formation of the third insulating film, which is advantageous in that it is efficient and economical.

[0034]

As described above, according to the semiconductor device of the present invention, the silicon nitride on the electrode shoulder is not shaved and the short circuit between the electrode wiring and the metal electrode in the contact hole is not caused. According to the method of manufacturing a semiconductor device of the present invention, a second insulating film such as a silicon oxide film is formed on the third side of the gate electrode side wall.
In this case, a single film is formed substantially on the side wall of the gate electrode, so that a slit is not formed in contact etching, and a silicon nitride film similar to that of the second insulating film is formed. Since the substrate surface portion can be left without being nitrided, the contact between the third insulating film and the semiconductor substrate is prevented, and an advantageous effect that high reliability can be secured can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a first process explanatory view in the embodiment of the method of manufacturing a semiconductor device according to the present invention;

FIG. 3 is a diagram illustrating a second process in one embodiment of the method of manufacturing a semiconductor device according to the present invention;

FIG. 4 is a diagram showing a nitriding characteristic of silicon oxide in one embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a sectional view showing an example of a conventional semiconductor device.

FIG. 6 is an explanatory view of a first step in a conventional method for manufacturing a semiconductor device.

FIG. 7 is an explanatory view of a second step in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 10 Gate oxide film 11 Tungsten polycide 12, 14 Silicon oxide 13, 15 Silicon nitride 16 Interlayer insulating film 17 Contact hole 18 Metal electrode 20 Resist 21 Resist pattern

Continued on the front page F term (reference) 4M104 AA01 BB01 BB02 BB40 CC05 DD04 DD43 DD55 DD99 EE06 EE09 EE12 EE17 FF14 GG09 5F033 AA02 AA29 BA02 BA12 BA24 BA33 BA37 CA04 CA09 DA07 DA35 EA04 EA25 5F040 DA01 EC01 EC04 EH08 EJ03 EJ09 FA03 FA05 FA07 FA16 FA17 FA18 FA19 FC00

Claims (7)

[Claims] An electrode wiring formed on a semiconductor substrate, a lower part of which is formed of a conductive film, an upper part of which is formed of a first insulating film, a second insulating film formed in contact with a side wall of the electrode wiring, A third insulating film formed between the second insulating film and the semiconductor substrate, a fourth insulating film formed so as to cover at least the electrode wiring and the second insulating film, A contact hole provided in the fourth insulating film so as to partially overlap with the electrode wiring, wherein the first and second insulating films are substantially made of a first material; Wherein the insulating film is substantially made of a second material different from the first material. 2. The semiconductor device according to claim 1, wherein the first and second insulating films are silicon nitride-based films, and the third and fourth insulating films are silicon oxide-based films. . 3. The semiconductor device according to claim 2, wherein the electrode wiring is a gate electrode wiring. 4. A step of forming an electrode wiring having a conductive film on the lower part and a first insulating film on the upper part, and forming a second insulating film on the electrode wiring and the semiconductor substrate on the semiconductor substrate. Performing a step of altering at least a portion of the second insulating film formed on the side wall of the electrode wiring; subsequently forming a third insulating film on at least the side wall of the electrode wiring; Forming a fourth insulating film in a region and another semiconductor substrate region, and selectively etching the fourth insulating film to provide a contact hole so as to partially overlap the electrode wiring. Wherein the step of changing the quality of the second insulating film is a changing step of changing the etching to a material having substantially the same properties as the third insulating film. . 5. The method according to claim 1, wherein the first and third insulating films are silicon nitride-based films, the second and fourth insulating films are silicon oxide-based films, and the altering process is a nitriding process. The method of manufacturing a semiconductor device according to claim 4. 6. The method according to claim 1, wherein the second insulating film is formed so that the surface portion of the semiconductor substrate is thicker than the side wall portion of the electrode wiring, and the nitriding in the transformation step is performed to a uniform thickness. Item 6. The method for manufacturing a semiconductor device according to Item 5. 7. The method according to claim 5, wherein the nitriding step is performed using an apparatus for forming a third insulating film, and using a nitriding gas for forming the third insulating film. Item 7. A method for manufacturing a semiconductor device according to Item 6.