JP2000040385A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a high voltage generating circuit in which stability in a high potential outputted at the time of variation of an external power source potential is improved. SOLUTION: This device is provided with a constant voltage generating circuit 34 stabilizing further an output potential of a constant voltage generating circuit 32 stabilizing an external power source potential Ext.Vcc, the output potential Vccs is made a current supply source of a charge pump circuit 60, also the charge pump circuit 60 comprises inverters 68, 70 setting amplitude of a clock by the output potential Vccs. A boosted potential Vout is hard to be affected by variation of the external power source potential Ext.Vcc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a booster circuit.

[0002]

2. Description of the Related Art In a semiconductor device, a potential higher than an externally applied power supply potential may be required for the operation of an internal circuit. For example, in a flash memory which is a typical nonvolatile semiconductor memory device, a high voltage is required for writing and erasing a memory cell.

FIG. 4 is a circuit diagram showing a configuration of a high voltage generating circuit 180 in a conventional semiconductor device.

Referring to FIG. 4, high voltage generation circuit 180
Is a power supply potential Ext. A constant voltage generation circuit 130 receiving Vcc to reduce the voltage to generate internal power supply potential Vcci, and a charge pump circuit 160 receiving clock signals CLK and / CLK to boost internal power supply potential Vcci and output it as boosted potential Vout. Including.

The constant voltage generating circuit 130 has an N-channel MOS transistor 138 having a source connected to the ground potential Vss and a gate connected to the node N10, and a source connected to the external power supply potential Ext. P-channel MOS transistor 136 whose drain and gate are connected to the drain of N-channel MOS transistor 138 and whose source is connected to ground potential Vss and whose gate has reference potential Vr
N-channel MOS transistor 142 supplied with ef
And the source is the external power supply potential Ext. Vcc, the gate is connected to the drain of N-channel MOS transistor 138, and the drain is N-channel MOS transistor 1
P-channel MOS transistor 140 connected to the drain of external power supply potential Ext. N-channel MOS transistor 142 coupled to Vcc and having a gate
And a P-channel MOS transistor 144 having a drain connected to node N10. The potential of node N10 is equal to external power supply potential Ext. Vcc is stepped down to internal power supply potential Vcci stabilized at a constant potential.

The charge pump circuit 160 includes a diode 162 having an anode and a cathode connected to nodes N13 and N14, respectively, and a diode 164 having an anode and a cathode connected to nodes N14 and N15, respectively.
And the anode and the cathode are connected to nodes N15 and N15, respectively.
16 connected to the diode 166. Node N
13 is supplied with the internal power supply potential Vcci, and the node N1
6 outputs a boosted potential Vout which is an output potential of the high voltage generating circuit 180.

Charge pump circuit 160 receives clock signal CLK and has an inverter 168 whose amplitude is determined by internal power supply potential Vcci, and a capacitor having one electrode connected to the output of inverter 168 and the other electrode connected to node N14. 172, an inverter 170 which receives and inverts a clock signal / CLK which is a complementary clock signal of the clock signal CLK and whose amplitude is determined by the internal power supply potential Vcci, one electrode connected to the output of the inverter 170 and the other electrode Further connected to a node N15.

By using such a high voltage generating circuit 180, the dependency of the operation (ripple) for recovering the drop of the boosted potential Vout or the like when the internal circuit operates or the like on the external power supply is reduced.

FIG. 5 is a diagram for explaining the ripple. Referring to FIG. 5, when the external power supply is turned on at time t = 0 and the external power supply potential rises, boosted potential Vout, which is the output of the booster circuit, also rises accordingly.

In a portion surrounded by a dotted line 190 after a lapse of a predetermined time, the boosted potential Vout fluctuates due to a voltage drop due to the operation of the supplied internal circuit and a recovery operation thereof. This variation is the ripple.

Such a ripple also depends on the power supply voltage before boosting applied to the boosting circuit. By reducing this dependency, for example, in a flash memory, a high voltage applied to a memory cell at the time of writing and erasing is used. Stabilize. By stabilizing this voltage, the dependence of the shift amount of the threshold value Vth, which is the information stored in the memory cell, and the writing time on the external power supply is reduced.

[0012]

For example, in a flash memory, it has become difficult to further miniaturize a memory cell, and in order to further increase the capacity, one memory cell has multiple values (for example, 2 bits, (3 bits, etc.) is being realized. In a flash memory, a voltage is applied to a transistor which is a memory cell to store information, and the threshold value is changed. To store multi-valued information in one memory cell, a threshold value corresponding to the amount of information is set. It is necessary to do. That is, in order to hold 2-bit information in one memory cell, the state of the threshold is set to four values corresponding to (00, 01, 10, 11).

In order to write the threshold value precisely, it is necessary to further stabilize the high potential applied to the memory cell at the time of writing and erasing.

The conventional high-voltage generating circuit shown in FIG. 4 has a problem that if a large fluctuation occurs in the external power supply potential, a non-negligible fluctuation occurs in the boosted output voltage. Such a situation is likely to occur when noise is put on the ground potential or the external power supply potential.

An object of the present invention is to provide a semiconductor device provided with a high voltage generating circuit in which the stability of a high potential output when the external power supply potential fluctuates is improved.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a first constant potential generating means for generating a first potential by receiving a power supply potential and controlling the first potential to a first reference potential; A second constant potential generating means for receiving the first potential and controlling and outputting the second potential to be the second reference potential, and a booster driven by the clock signal and receiving the second potential And a booster for generating a boosted potential.

According to a second aspect of the present invention, in addition to the configuration of the semiconductor device according to the first aspect, the boosting means is configured to direct the boosted potential from an internal node supplied with the second potential to an output node outputting a boosted potential. Receiving a clock signal, a first and second diode connected in series provided to allow a current to flow, a capacitor having one electrode connected to a connection node of the first and second diodes, And an amplitude adjusting means for applying an internal clock signal having an amplitude corresponding to the potential of the second capacitor to the other electrode of the capacitor.

According to a third aspect of the present invention, in addition to the configuration of the semiconductor device of the first aspect, the first constant potential generating means receives the power supply potential and is supplied with the first potential. A first transistor for supplying a current to the internal node of the first transistor, and comparing the first reference potential with the first constant potential. When the first potential is lower than the first reference potential, the first transistor is further increased. And first comparing means for activating and further inactivating the first transistor when the first potential is higher than the first reference potential, wherein the second constant potential generating means receives the power supply potential. A second transistor that supplies a current to a second internal node supplied with the second potential, a second reference potential lower than the first reference potential, and a second potential are compared to determine that the second potential is higher. When the potential is lower than the second reference potential, the first transistor is further activated. And, when the second potential is higher than the second reference potential and a second comparator means for further deactivating the second transistor.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 is a schematic block diagram showing a configuration of the semiconductor device of the first embodiment. FIG. 1 shows a flash memory as an example of a semiconductor device, and for simplicity of description, a memory cell array in one block has two memory cells.
The configuration is simplified to × 2.

The write / erase control circuit 1 controls the timing of the write operation and the erase operation and the voltage at each operation. The data input / output buffer 2 outputs data output from the sense amplifier 3 to a data terminal DQr, or
The write data input from data terminal DQr is output to write circuit 4.

The sense amplifier 3 amplifies the data of the memory cell in the memory cell array 11 inputted through the Y gate transistors Q1 and Q2, and amplifies the data input / output buffer 2
Output to

Write circuit 4 applies data input from data input / output buffer 2 to column latches 17 and 18. The column decoder 5 receives the output from the address buffer 13 and selects the Y gate transistors Q1, Q2.

The write / erase voltage generation circuit 19 supplies a voltage of 5 to 9 V to the column latches 17 and 18, and
5 to 9 V is supplied to the bit line according to data "0".

The write / erase voltage generating circuit 19 supplies -1 to the word line and the row decoder 12 during the write operation, and to the P well and the source of the selected memory cell during the erase operation.
Supply 1V voltage.

Select gate decoder 9 receives the output from address buffer 13 and selects select gates Q7-Q10 in memory cell array 11. Source line driver 10 includes N-channel MOS transistors Q3-Q
6 inclusive. The source line driver 10 applies a ground level voltage to the source line of the memory cell during a read operation, and applies a negative voltage during an erase operation.

The memory cell array 11 includes a memory cell Q1
1 to Q18 and select gates Q7 to Q10. In the memory cell array 11, data is written to or erased from the memory cells selected by the row decoder 12 and the column decoder 5. Row decoder 12 receives an output from address buffer 13 and selects a predetermined word line. The address buffer 13 has an address terminal A
An address signal for selecting a predetermined memory cell in the memory cell array 11 is received from dr, a column address signal is sent to the column decoder 5 and a row address signal is sent to the row decoder 1.
Output to 2.

The well potential switching circuit 15 applies a high negative voltage to the P well when erasing a memory cell, and grounds the P well in other operation modes.

The transfer gate 16 controls connection between the column latches 17 and 18 and the bit lines. The column latches 17 and 18 latch a write operation.

The write / erase voltage generation circuit 19 has an O.O. P.
At the time of recovery, 6V is supplied to the row decoder. At this time, the row decoder supplies 6 V to the word line.

As can be seen from the above description, the semiconductor device shown in FIG. 1 includes a high voltage generating circuit for generating a plurality of voltages inside write / erase voltage generating circuit 19.

FIG. 2 is a circuit diagram showing a configuration of high voltage generation circuit 80 included in write / erase voltage generation circuit 19 in FIG.

Referring to FIG. 2, high voltage generating circuit 80 includes:
Externally applied power supply potential Ext. A constant voltage generating circuit 32 receiving Vcc and lowering to generate internal power supply potential Vcc1, a constant voltage generating circuit 34 receiving and lowering power supply potential Vcc1 to generate internal power supply potential Vccs, and clock signals CLK and / CLK. And a charge pump circuit 60 that boosts internal power supply potential Vccs and outputs it as boosted potential Vout.

Constant voltage generating circuit 32 includes an N-channel MOS transistor 38 having a source connected to ground potential Vss and a gate connected to node N1, and a source connected to external power supply potential Ext. Vcc and the drain and gate are N
P-channel MOS transistor 36 connected to the drain of channel MOS transistor 38, N-channel MOS transistor 42 having a source coupled to ground potential Vss and a gate supplied with reference potential Vref1, and a source connected to external power supply potential Ext. Vcc, a gate connected to the drain of N-channel MOS transistor 38 and a drain connected to the drain of N-channel MOS transistor 42, and a source connected to external power supply potential Ext. P-channel MOS coupled to Vcc, having a gate connected to the drain of N-channel MOS transistor 42 and a drain connected to node N1
And a transistor 44. The potential of node N1 is equal to external power supply potential Ext. Vcc is stepped down to internal power supply potential Vcc1 stabilized at a constant potential.

Constant voltage generation circuit 34 has an N-channel MOS transistor 48 having a source connected to ground potential Vss and a gate connected to node N2, and a N-channel MOS transistor having a source connected to internal power supply potential Vcc1 and a drain and gate. 48, a P-channel MOS transistor 46 connected to the drain, and a source connected to the ground potential V
an N-channel MOS transistor 52 coupled to ss and having a gate supplied with reference potential Vref2; an N-channel MOS transistor having a source coupled to internal power supply potential Vcc1 and a gate
P-channel MOS transistor 50 connected to the drain of transistor 48 and the drain connected to the drain of N-channel MOS transistor 52; the source is coupled to internal power supply potential Vcc1, the gate is connected to the drain of N-channel MOS transistor 52, and the drain is connected P-channel MOS transistor 54 connected to node N2. The potential of node N2 is reduced from internal power supply potential Vcc1 and further stabilized at a constant potential.
cs.

The charge pump circuit 60 includes a diode 62 having an anode and a cathode connected to nodes N3 and N4, respectively, and an anode and a cathode each connected to a node N3.
4 and N5, and a diode 66 whose anode and cathode are connected to nodes N5 and N6, respectively. Node N3 has an internal power supply potential Vc
cs is applied, and a high voltage generation circuit 80
Is output as the boosted potential Vout.

Charge pump circuit 60 has an inverter 68 receiving clock signal CLK and having an amplitude determined by internal power supply potential Vccs, and a capacitor having one electrode connected to the output of inverter 68 and the other electrode connected to node N4. And an inverter 70 receiving and inverting clock signal / CLK which is a complementary clock signal of clock signal CLK and having an amplitude determined by internal power supply potential Vccs.
And a capacitor 74 having one electrode connected to the output of inverter 70 and the other electrode connected to node N5.

By using such a high voltage generating circuit 80, the boosted potential V when the internal circuit is operated, etc.
The dependence of the operation (ripple) for recovering the drop of out on the external power supply is reduced.

FIG. 2 shows an example in which three diodes 62, 64 and 66 are connected in series as the charge pump circuit 60 and capacitors are connected to the connection nodes N4 and N5, respectively, for the sake of simplicity. The number of diodes and capacitors is appropriately increased or decreased according to the required boosted potential.

FIG. 3 shows the reference potential Vref1 in FIG.
FIG. 2 is a circuit diagram showing a configuration of a reference potential generation circuit 90 that generates a signal.

Referring to FIG. 3, reference voltage generating circuit 90
A P-channel MOS transistor 92 having a source coupled to the power supply potential and a ground potential applied to the gate; and an N-channel MOS transistor 9 having a gate and a drain connected to the drain of the P-channel MOS transistor 92.
4 and an N-channel MOS transistor 96 whose source is connected to the ground potential and whose gate and drain are connected.

A required number of N-channel MOS transistors are diode-connected in series between the source of N-channel MOS transistor 94 and the drain of N-channel MOS transistor 96 according to the required value of reference potential Vref1. Is connected.

Then, the N-channel MOS transistor 9
4 has a reference potential Vref1 determined by threshold values of N-channel MOS transistors 94 to 96. This potential is equal to the external power supply potential Ext. The voltage becomes almost constant even if Vcc fluctuates.

The reference voltage generating circuit 90 generates a constant voltage according to the threshold value of an N-channel MOS transistor diode-connected in series, and uses it to generate a constant voltage Vref1.
Is not particularly limited as long as the circuit generates a reference potential independent of the power supply voltage. The reference potential Vref2 in FIG. 2 is generated in a similar manner.

Next, the operation of high voltage generating circuit 80 will be briefly described with reference to FIGS. 2 and 3. Constant voltage generating circuit 32 receives a reference potential Vref1 applied from reference voltage generating circuit 90 and receives a P-channel MOS. The resistance value of the transistor 44 is adjusted so that the potential Vcc1 of the node N1 becomes equal to the reference potential Vref1.

The constant voltage generation circuit 34 is a reference voltage generation circuit 9
0, the internal power supply potential Vccs of node N1 is adjusted to the reference potential Vr by adjusting the resistance value of P channel MOS transistor 54 in response to reference potential Vref2 applied from a circuit similar to that of node N1.
ef2.

As described above, the internal power supply potential Vccs, which is stabilized over two stages and is less susceptible to fluctuations in the external power supply potential, is applied to the node N3 to charge the charge pump circuit 60.
Generates a boosted potential Vout. At this time, the amplitudes of clocks CLK and / CLK, which are important in determining the boosted potential, are also determined by inverters 68 and 70 according to internal power supply potential Vccs. Therefore, the stability of the boosted potential Vout against the fluctuation of the external power supply potential is also improved.

As described above, Embodiment 1 of the present invention
In semiconductor devices, the amplitude of the ripple generated in the boosted potential when noise is added to the ground potential or the external power supply potential can be further reduced, so that a more accurate potential than the conventional output potential is supplied. It is possible to

Therefore, for example, it is effective in narrowing the distribution width of the threshold value (Vth) at the time of erasing and writing necessary for realizing a multi-valued memory using a nonvolatile element in a flash memory or the like. .

However, the semiconductor device of the present invention is not limited to a flash memory, and an effect can be expected if the semiconductor device requires a highly accurate boosted potential.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0052]

The semiconductor device according to the first, second and third aspects is expected because the amplitude of the ripple generated in the boosted potential when noise is superimposed on the ground potential or the external power supply potential can be suppressed. It is possible to supply a higher-precision potential than the output potential, which is effective, for example, in accurately setting the threshold value of a memory cell at the time of writing / erasing of a flash memory.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a semiconductor device according to a first embodiment;

FIG. 2 is a circuit diagram showing a configuration of a high voltage generation circuit included in write / erase voltage generation circuit in FIG.

FIG. 3 shows reference potentials Vref1 and Vref in FIG.
FIG. 4 is a circuit diagram showing a configuration of a reference potential generation circuit 90 that generates a reference potential 2;

FIG. 4 shows a high-voltage generation circuit 1 in a conventional semiconductor device.
FIG. 2 is a circuit diagram showing a configuration of an embodiment.

FIG. 5 is a diagram for explaining a ripple.

[Explanation of symbols]

1 write / erase control circuit, 4 write circuit, 9 select gate decoder, 12 row decoder, 15 well potential switching circuit, 19 write / erase voltage generation circuit, 80 high voltage generation circuit, 32, 34 constant voltage generation circuit , 60 charge pump circuits, 68, 70 inverters.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Satoru Tamada 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Nobuo Ando 2-3-2 Marunouchi 3-chome, Chiyoda-ku, Tokyo Rishi Electric Co., Ltd. F term (reference) 5B025 AA01 AC02 AD10 AE00 5F038 BB04 BG03 BG04 BG05 BG08 BG09 CD15 DF05 DF14 EZ20 5H730 AA04 AS00 BB02 BB57 BB86

Claims (3)

[Claims] A first constant potential generating means for controlling a first potential to a first reference potential and outputting the first potential in response to a power supply potential, and a second potential in response to the first potential. A semiconductor, comprising: a second constant potential generating means for controlling and outputting a second reference potential; and a boosting means driven by a clock signal, receiving the second potential and boosting to generate a boosted potential. apparatus. 2. The first and second serially connected boosting means provided to flow a current from an internal node to which the second potential is applied to an output node that outputs the boosted potential. A diode, a capacitor having one electrode connected to a connection node between the first and second diodes, and an internal clock signal having an amplitude corresponding to the second potential, receiving the clock signal. The semiconductor device according to claim 1, further comprising: an amplitude adjusting means for giving the other electrode. 3. The first constant potential generation means receives a power supply potential and receives a first potential.
A first transistor for supplying a current to an internal node of the first transistor, and comparing a first reference potential with the first potential and comparing the first reference potential with the first potential.
When the potential is lower than the first reference potential, the first transistor is further activated. When the first potential is higher than the first reference potential, the first transistor is further deactivated. A second comparing unit that receives the power supply potential and is supplied with the second potential.
A second transistor for supplying a current to the internal node of the second transistor, a second reference potential lower than the first reference potential, and a second transistor.
When the second potential is lower than the second reference potential, the first transistor is further activated, and when the second potential is higher than the second reference potential, A second transistor for further deactivating the second transistor;
2. The semiconductor device according to claim 1, further comprising: comparing means.