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IT8683608A0 - Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento. - Google Patents

Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento.

Info

Publication number
IT8683608A0
IT8683608A0 IT8683608A IT8360886A IT8683608A0 IT 8683608 A0 IT8683608 A0 IT 8683608A0 IT 8683608 A IT8683608 A IT 8683608A IT 8360886 A IT8360886 A IT 8360886A IT 8683608 A0 IT8683608 A0 IT 8683608A0
Authority
IT
Italy
Prior art keywords
procedure
sized
self
manufacture
small
Prior art date
Application number
IT8683608A
Other languages
English (en)
Other versions
IT1204243B (it
Inventor
Claudio Contiero
Antonio Andreini
Paola Galbiati
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT83608/86A priority Critical patent/IT1204243B/it
Publication of IT8683608A0 publication Critical patent/IT8683608A0/it
Priority to DE8787830063T priority patent/DE3778961D1/de
Priority to EP87830063A priority patent/EP0244366B1/en
Priority to US07/019,785 priority patent/US4774198A/en
Priority to JP62051180A priority patent/JPS62222677A/ja
Application granted granted Critical
Publication of IT1204243B publication Critical patent/IT1204243B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
IT83608/86A 1986-03-06 1986-03-06 Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento IT1204243B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT83608/86A IT1204243B (it) 1986-03-06 1986-03-06 Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento
DE8787830063T DE3778961D1 (de) 1986-03-06 1987-02-23 Selbstausrichtendes verfahren zur herstellung kleiner dmos-zellen und durch dieses verfahren erhaltene mos-bauelemente.
EP87830063A EP0244366B1 (en) 1986-03-06 1987-02-23 Self-aligned process for fabricating small size dmos cells and mos devices obtained by means of said process
US07/019,785 US4774198A (en) 1986-03-06 1987-02-26 Self-aligned process for fabricating small DMOS cells
JP62051180A JPS62222677A (ja) 1986-03-06 1987-03-05 小サイズのｄｍｏｓセルの自動位置合わせによる製造方法及び該方法により得られるｍｏｓデバイス

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT83608/86A IT1204243B (it) 1986-03-06 1986-03-06 Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento

Publications (2)

Publication Number Publication Date
IT8683608A0 true IT8683608A0 (it) 1986-03-06
IT1204243B IT1204243B (it) 1989-03-01

Family

ID=11323069

Family Applications (1)

Application Number Title Priority Date Filing Date
IT83608/86A IT1204243B (it) 1986-03-06 1986-03-06 Procedimento autoallineato per la fabbricazione di celle dmos di piccole dimensioni e dispositivi mos ottenuti mediante detto procedimento

Country Status (5)

Country Link
US (1) US4774198A (it)
EP (1) EP0244366B1 (it)
JP (1) JPS62222677A (it)
DE (1) DE3778961D1 (it)
IT (1) IT1204243B (it)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01225164A (ja) * 1988-03-03 1989-09-08 Fuji Electric Co Ltd 絶縁ゲートｍｏｓｆｅｔの製造方法
GB2206443A (en) * 1987-06-08 1989-01-05 Philips Electronic Associated A method of manufacturing a semiconductor device
US5179034A (en) * 1987-08-24 1993-01-12 Hitachi, Ltd. Method for fabricating insulated gate semiconductor device
JPH0766968B2 (ja) * 1987-08-24 1995-07-19 株式会社日立製作所 半導体装置及びその製造方法
US5285094A (en) * 1987-08-24 1994-02-08 Hitachi, Ltd. Vertical insulated gate semiconductor device with less influence from the parasitic bipolar effect
JP2521783B2 (ja) * 1987-09-28 1996-08-07 三菱電機株式会社 半導体装置およびその製造方法
JPH0734474B2 (ja) * 1988-03-03 1995-04-12 富士電機株式会社 伝導度変調型ｍｏｓｆｅｔの製造方法
US5118638A (en) * 1988-03-18 1992-06-02 Fuji Electric Co., Ltd. Method for manufacturing MOS type semiconductor devices
JPH01238172A (ja) * 1988-03-18 1989-09-22 Fuji Electric Co Ltd Ｍｏｓ型半導体素子の製造方法
US4853345A (en) * 1988-08-22 1989-08-01 Delco Electronics Corporation Process for manufacture of a vertical DMOS transistor
US5342797A (en) * 1988-10-03 1994-08-30 National Semiconductor Corporation Method for forming a vertical power MOSFET having doped oxide side wall spacers
US4998151A (en) * 1989-04-13 1991-03-05 General Electric Company Power field effect devices having small cell size and low contact resistance
US4970173A (en) * 1989-07-03 1990-11-13 Motorola, Inc. Method of making high voltage vertical field effect transistor with improved safe operating area
IT1231300B (it) * 1989-07-24 1991-11-28 Sgs Thomson Microelectronics Processo di definizione e realizzazione di una regione attivadi dimensioni molto ridotte in uno strato di materiale semiconduttore
EP0416805B1 (en) * 1989-08-30 1996-11-20 Siliconix, Inc. Transistor with voltage clamp
US4931408A (en) * 1989-10-13 1990-06-05 Siliconix Incorporated Method of fabricating a short-channel low voltage DMOS transistor
IT1236994B (it) * 1989-12-29 1993-05-12 Sgs Thomson Microelectronics Processo per la fabbricazione di dispositivi semiconduttori mos di potenza e dispositivi con esso ottenuti
US5202276A (en) * 1990-08-20 1993-04-13 Texas Instruments Incorporated Method of forming a low on-resistance DMOS vertical transistor structure
EP0481153B1 (en) * 1990-10-16 1997-02-12 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Process for the accomplishment of power MOS transistors with vertical current flow
JPH04152536A (ja) * 1990-10-16 1992-05-26 Fuji Electric Co Ltd Ｍｉｓ型半導体装置の製造方法
US5155052A (en) * 1991-06-14 1992-10-13 Davies Robert B Vertical field effect transistor with improved control of low resistivity region geometry
US5182222A (en) * 1991-06-26 1993-01-26 Texas Instruments Incorporated Process for manufacturing a DMOS transistor
US5268586A (en) * 1992-02-25 1993-12-07 North American Philips Corporation Vertical power MOS device with increased ruggedness and method of fabrication
US5321281A (en) * 1992-03-18 1994-06-14 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method of fabricating same
US5355008A (en) * 1993-11-19 1994-10-11 Micrel, Inc. Diamond shaped gate mesh for cellular MOS transistor array
EP0658940A1 (de) * 1993-11-23 1995-06-21 Siemens Aktiengesellschaft Durch Feldeffekt steuerbares Halbleiterbauelement
US5405794A (en) * 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
US5474946A (en) * 1995-02-17 1995-12-12 International Rectifier Corporation Reduced mask process for manufacture of MOS gated devices
DE69512021T2 (de) * 1995-03-31 2000-05-04 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania DMOS-Anordnung-Struktur und Verfahren zur Herstellung
US5567634A (en) * 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
US5684319A (en) * 1995-08-24 1997-11-04 National Semiconductor Corporation Self-aligned source and body contact structure for high performance DMOS transistors and method of fabricating same
JPH1154746A (ja) * 1997-07-31 1999-02-26 Toyota Motor Corp 絶縁ゲート型半導体装置およびその製造方法
US6051504A (en) * 1997-08-15 2000-04-18 International Business Machines Corporation Anisotropic and selective nitride etch process for high aspect ratio features in high density plasma
US6461529B1 (en) 1999-04-26 2002-10-08 International Business Machines Corporation Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme
EP1058303A1 (en) * 1999-05-31 2000-12-06 STMicroelectronics S.r.l. Fabrication of VDMOS structure with reduced parasitic effects
ITVA20010045A1 (it) * 2001-12-14 2003-06-16 St Microelectronics Srl Flusso di processo per la realizzazione di un vdmos a canale scalato e basso gradiente di body per prestazioni ad elevata densita' di corren
US20030151092A1 (en) * 2002-02-11 2003-08-14 Feng-Tso Chien Power mosfet device with reduced snap-back and being capable of increasing avalanche-breakdown current endurance, and method of manafacturing the same
DE10355587B4 (de) * 2003-11-28 2007-05-24 Infineon Technologies Ag Verfahren zur Herstellung eines vertikalen Leistungs-Halbleitertransistors
US7279743B2 (en) 2003-12-02 2007-10-09 Vishay-Siliconix Closed cell trench metal-oxide-semiconductor field effect transistor
US8183629B2 (en) * 2004-05-13 2012-05-22 Vishay-Siliconix Stacked trench metal-oxide-semiconductor field effect transistor device
US8471390B2 (en) * 2006-05-12 2013-06-25 Vishay-Siliconix Power MOSFET contact metallization
US8368126B2 (en) * 2007-04-19 2013-02-05 Vishay-Siliconix Trench metal oxide semiconductor with recessed trench material and remote contacts
US9306056B2 (en) 2009-10-30 2016-04-05 Vishay-Siliconix Semiconductor device with trench-like feed-throughs
CN107331617B (zh) * 2016-04-29 2019-12-31 北大方正集团有限公司 平面型vdmos器件的制作方法
CN115939178A (zh) * 2023-03-10 2023-04-07 广东芯聚能半导体有限公司 半导体结构及其制备方法

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Publication number Priority date Publication date Assignee Title
DE3103444A1 (de) * 1981-02-02 1982-10-21 Siemens AG, 1000 Berlin und 8000 München Vertikal-mis-feldeffekttransistor mit kleinem durchlasswiderstand
DE3240162C2 (de) * 1982-01-04 1996-08-01 Gen Electric Verfahren zum Herstellen eines doppelt-diffundierten Leistungs-MOSFET mit Source-Basis-Kurzschluß
US4443931A (en) * 1982-06-28 1984-04-24 General Electric Company Method of fabricating a semiconductor device with a base region having a deep portion
US4466176A (en) * 1982-08-09 1984-08-21 General Electric Company Process for manufacturing insulated-gate semiconductor devices with integral shorts
JPS60196975A (ja) * 1984-08-24 1985-10-05 Nissan Motor Co Ltd 縦型ｍｏｓｆｅｔ
JPS6010677A (ja) * 1983-06-30 1985-01-19 Nissan Motor Co Ltd 縦型ｍｏｓトランジスタ
US4618872A (en) * 1983-12-05 1986-10-21 General Electric Company Integrated power switching semiconductor devices including IGT and MOSFET structures
JPS61156882A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 二重拡散形絶縁ゲ−ト電界効果トランジスタ及びその製造方法
US4661838A (en) * 1985-10-24 1987-04-28 General Electric Company High voltage semiconductor devices electrically isolated from an integrated circuit substrate
US4717940A (en) * 1986-03-11 1988-01-05 Kabushiki Kaisha Toshiba MIS controlled gate turn-off thyristor

Also Published As

Publication number Publication date
EP0244366A3 (en) 1988-01-07
DE3778961D1 (de) 1992-06-17
EP0244366B1 (en) 1992-05-13
US4774198A (en) 1988-09-27
EP0244366A2 (en) 1987-11-04
JPS62222677A (ja) 1987-09-30
IT1204243B (it) 1989-03-01

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970329