IT1306183B1 - PROCEDURE FOR THE FORMATION OF THICKNESS INSULATING LAYERS PREPARED IN WAFER OF SEMICONDUCTORS FOR THE PRODUCTION OF - Google Patents
PROCEDURE FOR THE FORMATION OF THICKNESS INSULATING LAYERS PREPARED IN WAFER OF SEMICONDUCTORS FOR THE PRODUCTION OFInfo
- Publication number
- IT1306183B1 IT1306183B1 IT1999RM000498A ITRM990498A IT1306183B1 IT 1306183 B1 IT1306183 B1 IT 1306183B1 IT 1999RM000498 A IT1999RM000498 A IT 1999RM000498A IT RM990498 A ITRM990498 A IT RM990498A IT 1306183 B1 IT1306183 B1 IT 1306183B1
- Authority
- IT
- Italy
- Prior art keywords
- semiconductors
- wafer
- procedure
- formation
- production
- Prior art date
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT1999RM000498A IT1306183B1 (en) | 1999-08-02 | 1999-08-02 | PROCEDURE FOR THE FORMATION OF THICKNESS INSULATING LAYERS PREPARED IN WAFER OF SEMICONDUCTORS FOR THE PRODUCTION OF |
| AU67239/00A AU6723900A (en) | 1999-08-02 | 2000-08-02 | Process for the forming of isolation layers of a predetermined thickness in semiconductor wafers for the manufacturing of integrated circuits |
| PCT/IT2000/000331 WO2001009943A1 (en) | 1999-08-02 | 2000-08-02 | Process for the forming of isolation layers of a predetermined thickness in semiconductor wafers for the manufacturing of integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT1999RM000498A IT1306183B1 (en) | 1999-08-02 | 1999-08-02 | PROCEDURE FOR THE FORMATION OF THICKNESS INSULATING LAYERS PREPARED IN WAFER OF SEMICONDUCTORS FOR THE PRODUCTION OF |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITRM990498A0 ITRM990498A0 (en) | 1999-08-02 |
| ITRM990498A1 ITRM990498A1 (en) | 2001-02-02 |
| IT1306183B1 true IT1306183B1 (en) | 2001-05-30 |
Family
ID=11406922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT1999RM000498A IT1306183B1 (en) | 1999-08-02 | 1999-08-02 | PROCEDURE FOR THE FORMATION OF THICKNESS INSULATING LAYERS PREPARED IN WAFER OF SEMICONDUCTORS FOR THE PRODUCTION OF |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU6723900A (en) |
| IT (1) | IT1306183B1 (en) |
| WO (1) | WO2001009943A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6273909B1 (en) | 1998-10-05 | 2001-08-14 | Teramed Inc. | Endovascular graft system |
| FR3012256A1 (en) * | 2013-10-17 | 2015-04-24 | St Microelectronics Tours Sas | VERTICAL POWER COMPONENT HIGH VOLTAGE |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4380865A (en) * | 1981-11-13 | 1983-04-26 | Bell Telephone Laboratories, Incorporated | Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation |
| FR2564241B1 (en) * | 1984-05-09 | 1987-03-27 | Bois Daniel | METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS |
| EP0225519A3 (en) * | 1985-12-06 | 1989-12-06 | Texas Instruments Incorporated | High definition anodized sublayer boundary |
| US4910165A (en) * | 1988-11-04 | 1990-03-20 | Ncr Corporation | Method for forming epitaxial silicon on insulator structures using oxidized porous silicon |
| KR950008261B1 (en) * | 1991-12-03 | 1995-07-26 | 삼성전자주식회사 | Making method of semiconductor device |
-
1999
- 1999-08-02 IT IT1999RM000498A patent/IT1306183B1/en active
-
2000
- 2000-08-02 AU AU67239/00A patent/AU6723900A/en not_active Abandoned
- 2000-08-02 WO PCT/IT2000/000331 patent/WO2001009943A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| AU6723900A (en) | 2001-02-19 |
| ITRM990498A1 (en) | 2001-02-02 |
| ITRM990498A0 (en) | 1999-08-02 |
| WO2001009943A1 (en) | 2001-02-08 |
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