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IN2014CN04680A - - Google Patents

Info

Publication number
IN2014CN04680A
IN2014CN04680A IN4680CHN2014A IN2014CN04680A IN 2014CN04680 A IN2014CN04680 A IN 2014CN04680A IN 4680CHN2014 A IN4680CHN2014 A IN 4680CHN2014A IN 2014CN04680 A IN2014CN04680 A IN 2014CN04680A
Authority
IN
India
Prior art keywords
die
heat spreader
microelectronic
parallel
encapsulation material
Prior art date
Application number
Inventor
Weng Hong Teh
Deepak Kulkarni
Chia Pin Chiu
Tannaz Harirchian
John S Guzek
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of IN2014CN04680A publication Critical patent/IN2014CN04680A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • HELECTRICITY
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    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
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    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211Disposition
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747Copper [Cu] as principal constituent

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

An example includes a die package including a microelectronic die having a lower die surface an upper die surface parallel to the lower die surface and a die side the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface an upper heat spreader surface parallel to the lower heat spreader surface and at least one heat spreader side the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
IN4680CHN2014 2012-09-28 2013-06-04 IN2014CN04680A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/631,205 US8912670B2 (en) 2012-09-28 2012-09-28 Bumpless build-up layer package including an integrated heat spreader
PCT/US2013/044001 WO2014051714A1 (en) 2012-09-28 2013-06-04 Bumpless build-up layer package including an integrated heat spreader

Publications (1)

Publication Number Publication Date
IN2014CN04680A true IN2014CN04680A (en) 2015-09-18

Family

ID=50384394

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4680CHN2014 IN2014CN04680A (en) 2012-09-28 2013-06-04

Country Status (5)

Country Link
US (3) US8912670B2 (en)
CN (1) CN104025289B (en)
DE (1) DE112013000494B4 (en)
IN (1) IN2014CN04680A (en)
WO (1) WO2014051714A1 (en)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013089754A1 (en) * 2011-12-15 2013-06-20 Intel Corporation Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (bbul) packages
US8912670B2 (en) 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
JP2016039213A (en) * 2014-08-06 2016-03-22 ローム株式会社 Substrate built-in package, semiconductor device, and module
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
CN106449434B (en) * 2015-06-26 2021-08-10 Pep创新私人有限公司 Semiconductor packaging method, semiconductor package and stacked semiconductor package
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10515929B2 (en) * 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory
US10431563B1 (en) 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
TWI675441B (en) * 2018-05-14 2019-10-21 欣興電子股份有限公司 Package carrier structure and manufacturing method thereof
US11527483B2 (en) * 2018-06-29 2022-12-13 Intel Corporation Package including fully integrated voltage regulator circuitry within a substrate
WO2020010265A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US10692737B2 (en) * 2018-10-08 2020-06-23 General Electric Company Multilayer interconnect structure with buried conductive via connections and method of manufacturing thereof
US10504826B1 (en) 2018-10-08 2019-12-10 General Electric Company Device almost last embedded device structure and method of manufacturing thereof
US11004786B2 (en) * 2019-03-15 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US11652020B2 (en) * 2019-05-29 2023-05-16 Intel Corporation Thermal solutions for multi-package assemblies and methods for fabricating the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11972999B2 (en) * 2021-12-07 2024-04-30 Globalfoundries U.S. Inc. Unlanded thermal dissipation pillar adjacent active contact

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287247A (en) * 1990-09-21 1994-02-15 Lsi Logic Corporation Computer system module assembly
US5111278A (en) * 1991-03-27 1992-05-05 Eichelberger Charles W Three-dimensional multichip module systems
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6150716A (en) * 1995-01-25 2000-11-21 International Business Machines Corporation Metal substrate having an IC chip and carrier mounting
JP2636777B2 (en) * 1995-02-14 1997-07-30 日本電気株式会社 Semiconductor module for microprocessor
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US5567657A (en) * 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US6011694A (en) * 1996-08-01 2000-01-04 Fuji Machinery Mfg. & Electronics Co., Ltd. Ball grid array semiconductor package with solder ball openings in an insulative base
KR100543836B1 (en) * 1997-08-19 2006-01-23 가부시키가이샤 히타치세이사쿠쇼 Multichip module structure and method for manufacturing the same
US5903052A (en) * 1998-05-12 1999-05-11 Industrial Technology Research Institute Structure for semiconductor package for improving the efficiency of spreading heat
US6060777A (en) * 1998-07-21 2000-05-09 Intel Corporation Underside heat slug for ball grid array packages
US6084297A (en) * 1998-09-03 2000-07-04 Micron Technology, Inc. Cavity ball grid array apparatus
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6586836B1 (en) 2000-03-01 2003-07-01 Intel Corporation Process for forming microelectronic packages and intermediate structures formed therewith
EP1268698B1 (en) * 2000-04-04 2004-05-26 Henkel Kommanditgesellschaft auf Aktien Assembly adhesive on the basis of an aqueous polymer dispersion
CN100426492C (en) 2000-08-16 2008-10-15 英特尔公司 Direct build-up layer on encapsulated die package
US20020070443A1 (en) 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
US6506632B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of forming IC package having downward-facing chip cavity
TW582100B (en) * 2002-05-30 2004-04-01 Fujitsu Ltd Semiconductor device having a heat spreader exposed from a seal resin
US6987032B1 (en) 2002-07-19 2006-01-17 Asat Ltd. Ball grid array package and process for manufacturing same
JP4012496B2 (en) * 2003-09-19 2007-11-21 カシオ計算機株式会社 Semiconductor device
JP4361826B2 (en) 2004-04-20 2009-11-11 新光電気工業株式会社 Semiconductor device
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
US7129572B2 (en) * 2004-08-18 2006-10-31 Chung-Cheng Wang Submember mounted on a chip of electrical device for electrical connection
US6969640B1 (en) * 2004-09-02 2005-11-29 Stats Chippac Ltd. Air pocket resistant semiconductor package system
US7786567B2 (en) * 2004-11-10 2010-08-31 Chung-Cheng Wang Substrate for electrical device and methods for making the same
KR100702968B1 (en) * 2005-11-24 2007-04-03 삼성전자주식회사 Semiconductor package having floated heat sink, stack package using the same and manufacturing method thereof
US8067267B2 (en) 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
TWI311789B (en) 2006-06-13 2009-07-01 Siliconware Precision Industries Co Ltd Heat sink package structure and method for fabricating the same
US7723164B2 (en) 2006-09-01 2010-05-25 Intel Corporation Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same
US7659143B2 (en) 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US8643172B2 (en) 2007-06-08 2014-02-04 Freescale Semiconductor, Inc. Heat spreader for center gate molding
TW200901409A (en) 2007-06-22 2009-01-01 Nan Ya Printed Circuit Board Corp Packaging substrate with embedded chip and buried heatsink
US8299626B2 (en) 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
US7851905B2 (en) 2007-09-26 2010-12-14 Intel Corporation Microelectronic package and method of cooling an interconnect feature in same
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8064224B2 (en) 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US20090294949A1 (en) 2008-05-30 2009-12-03 Infineon Technologies Ag Molded semiconductor device
US8093704B2 (en) 2008-06-03 2012-01-10 Intel Corporation Package on package using a bump-less build up layer (BBUL) package
KR20100033012A (en) 2008-09-19 2010-03-29 주식회사 하이닉스반도체 Semiconductor package and stacked semiconductor package having the same
US7851894B1 (en) 2008-12-23 2010-12-14 Amkor Technology, Inc. System and method for shielding of package on package (PoP) assemblies
US8018072B1 (en) * 2008-12-23 2011-09-13 Amkor Technology, Inc. Semiconductor package having a heat spreader with an exposed exterion surface and a top mold gate
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8912670B2 (en) 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation

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CN104025289B (en) 2017-06-20
US20150104907A1 (en) 2015-04-16
DE112013000494T5 (en) 2014-10-02
US20160027757A1 (en) 2016-01-28
US9520376B2 (en) 2016-12-13
CN104025289A (en) 2014-09-03
WO2014051714A1 (en) 2014-04-03
US20140091445A1 (en) 2014-04-03
US9153552B2 (en) 2015-10-06
US8912670B2 (en) 2014-12-16
DE112013000494B4 (en) 2018-07-19

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