GB9620362D0 - A semi-conductor integrated circuit - Google Patents
A semi-conductor integrated circuitInfo
- Publication number
- GB9620362D0 GB9620362D0 GBGB9620362.5A GB9620362A GB9620362D0 GB 9620362 D0 GB9620362 D0 GB 9620362D0 GB 9620362 A GB9620362 A GB 9620362A GB 9620362 D0 GB9620362 D0 GB 9620362D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- semi
- integrated circuit
- conductor integrated
- conductor
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB9520026.7A GB9520026D0 (en) | 1995-09-30 | 1995-09-30 | Semi-conductor integrated circuit |
GBGB9520027.5A GB9520027D0 (en) | 1995-09-30 | 1995-09-30 | A semi-conductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
GB9620362D0 true GB9620362D0 (en) | 1996-11-13 |
GB2305759A GB2305759A (en) | 1997-04-16 |
Family
ID=26307850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9620362A Withdrawn GB2305759A (en) | 1995-09-30 | 1996-09-27 | Semi-conductor integrated circuit |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0853840A1 (en) |
JP (1) | JP2000513511A (en) |
CN (1) | CN1203706A (en) |
AU (1) | AU7309196A (en) |
CA (1) | CA2235927A1 (en) |
GB (1) | GB2305759A (en) |
WO (1) | WO1997013324A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6275064B1 (en) * | 1997-12-22 | 2001-08-14 | Vantis Corporation | Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits |
US6215326B1 (en) * | 1998-11-18 | 2001-04-10 | Altera Corporation | Programmable logic device architecture with super-regions having logic regions and a memory region |
JP3616518B2 (en) * | 1999-02-10 | 2005-02-02 | 日本電気株式会社 | Programmable device |
US6342792B1 (en) * | 1999-03-04 | 2002-01-29 | Altera Corporation | Logic module circuitry for programmable logic devices |
EP1465345A3 (en) * | 1999-03-04 | 2006-04-12 | Altera Corporation | Interconnection resources for programmable logic integrated circuit devices |
ATE300121T1 (en) * | 1999-05-07 | 2005-08-15 | Infineon Technologies Ag | DEVICE AND METHOD FOR DYNAMIC DEFINITION OF SUBFIELDS WITHIN A PROGRAMMABLE GATE FIELD |
US9667256B2 (en) * | 2013-03-01 | 2017-05-30 | Axion Research Inc. | Data processing device and control method therefor |
US8853815B1 (en) * | 2013-03-14 | 2014-10-07 | Qualcomm Incorporated | Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains |
DE102019006292A1 (en) * | 2019-09-05 | 2021-03-11 | PatForce GmbH | Arrangement of switch boxes |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5144166A (en) * | 1990-11-02 | 1992-09-01 | Concurrent Logic, Inc. | Programmable logic cell and array |
US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
US5357153A (en) * | 1993-01-28 | 1994-10-18 | Xilinx, Inc. | Macrocell with product-term cascade and improved flip flop utilization |
JPH0737272Y2 (en) * | 1993-06-16 | 1995-08-23 | 第一電装部品株式会社 | Attachment mounting structure |
GB9312674D0 (en) * | 1993-06-18 | 1993-08-04 | Pilkington Micro Electronics | Configurabel logic array |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
DE69534659T2 (en) * | 1994-04-14 | 2006-09-07 | BTR, Inc., Reno | Architecture and connection model for programmable logic circuits |
US5689195A (en) * | 1995-05-17 | 1997-11-18 | Altera Corporation | Programmable logic array integrated circuit devices |
US5592106A (en) * | 1995-05-17 | 1997-01-07 | Altera Corporation | Programmable logic array integrated circuits with interconnection conductors of overlapping extent |
-
1996
- 1996-09-27 GB GB9620362A patent/GB2305759A/en not_active Withdrawn
- 1996-10-01 WO PCT/GB1996/002461 patent/WO1997013324A1/en not_active Application Discontinuation
- 1996-10-01 AU AU73091/96A patent/AU7309196A/en not_active Abandoned
- 1996-10-01 JP JP09514085A patent/JP2000513511A/en active Pending
- 1996-10-01 EP EP96934983A patent/EP0853840A1/en not_active Ceased
- 1996-10-01 CA CA 2235927 patent/CA2235927A1/en not_active Abandoned
- 1996-10-01 CN CN 96198716 patent/CN1203706A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
WO1997013324A1 (en) | 1997-04-10 |
CN1203706A (en) | 1998-12-30 |
CA2235927A1 (en) | 1997-04-10 |
AU7309196A (en) | 1997-04-28 |
JP2000513511A (en) | 2000-10-10 |
EP0853840A1 (en) | 1998-07-22 |
GB2305759A (en) | 1997-04-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |