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GB861515A - Improvements in or relating to timing circuits - Google Patents

Improvements in or relating to timing circuits

Info

Publication number
GB861515A
GB861515A GB39824/58A GB3982458A GB861515A GB 861515 A GB861515 A GB 861515A GB 39824/58 A GB39824/58 A GB 39824/58A GB 3982458 A GB3982458 A GB 3982458A GB 861515 A GB861515 A GB 861515A
Authority
GB
United Kingdom
Prior art keywords
store
output
signal
translator
talker
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB39824/58A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of GB861515A publication Critical patent/GB861515A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/17Time-division multiplex systems in which the transmission channel allotted to a first user may be taken away and re-allotted to a second user if the first user becomes inactive, e.g. TASI
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/24Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

861,515. Telephone transmission systems. WESTERN ELECTRIC CO. Inc. Dec. 10, 1958 [Dec. 24, 1957], No. 39824/58. Class 40 (4). A circuit for timing an operation comprises a generator for cyclically generating a succession of code groups, a store into which is entered that code group occurring at the beginning of the operation, means for translating the code groups into groups corresponding to later positions in the cycle, and a comparator which upon receiving identical code groups from the store and the translator emits a signal to terminate the operation. As described, the successive code groups are binary representations of numbers 1 . . . 8 and the translator is a logic circuit whose binary output represents a member 2 more than its input. The invention is applied to the timing of a talker connecting signal in a TAS1 system such as that described in Specification 845,174. As shown identities, in the form of 7-digit binary numbers, of newly active talkers, are queried in a register 322 preparatory to insertion into a free time slot in a circulating store 309, which has a slot for every channel. A free channel is indicated by the digits 00 in the channel status portion of the store and when these are received by the translator 310, an output on lead 311 opens the switch 315 to admit the identity of a talker to the store and also to replace the 00 by 01. Simultaneously a three-digit binary number is admitted to the right-hand side of the store from a binary counter stepped once per millisecond by the oscillator 325 in an 8-millisecond cycle. This binary number is fed to the ADD 2 logic circuit 327 whose output feeds one side of the comparator 328. After 6 milliseconds the output of the logic circuit will be identical with that originally stored in the circulating memory. The latter circulates at 8 revolutions per millisecond so that the contents of all its time slots are compared with the each output from the logic circuit, and when identity is obtained the comparator emits a signal on lead 329. Meanwhile, with 01 in the channel status portion, translator 310 when fed from this time slot opens switch 333 to feed the talker identity to a " connect " signal source 323, which emits pulses on 324 modulated by combinations of seven tones in accordance with the talker's identity. These are fed over the assigned channel to the receiver as described in Specification 845,174. At the end of 6 milliseconds the output on lead 329 causes the substitution of 11 for 01 in the channel status portion of the memory to terminate the " connect " signal. The remainder of the operation is as described in Specification 845,174. Specification 781,622 also is referred to.
GB39824/58A 1957-12-24 1958-12-10 Improvements in or relating to timing circuits Expired GB861515A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US704927A US2957945A (en) 1957-12-24 1957-12-24 Timing circuit

Publications (1)

Publication Number Publication Date
GB861515A true GB861515A (en) 1961-02-22

Family

ID=24831408

Family Applications (1)

Application Number Title Priority Date Filing Date
GB39824/58A Expired GB861515A (en) 1957-12-24 1958-12-10 Improvements in or relating to timing circuits

Country Status (8)

Country Link
US (1) US2957945A (en)
JP (1) JPS372563B1 (en)
BE (1) BE574121A (en)
DE (1) DE1183958B (en)
ES (1) ES246497A1 (en)
FR (1) FR1215377A (en)
GB (1) GB861515A (en)
NL (1) NL234515A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2604270A1 (en) * 1986-09-22 1988-03-25 Jutand Francis BINARY ADDITIONER HAVING FIXED OPERAND, AND PARALLEL-SERIAL BINARY MULTIPLIER COMPRISING SUCH ADDITIONER

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3092808A (en) * 1959-05-18 1963-06-04 Acf Ind Inc Continuously variable digital delay line
US3241067A (en) * 1961-04-21 1966-03-15 Bell Telephone Labor Inc Synchronization of decoder systems based on message wave statistics
DE1219983B (en) * 1963-04-24 1966-06-30 Licentia Gmbh Circuit arrangement for the adjustable delay of a signal using a forward binary counter
US3921133A (en) * 1970-12-07 1975-11-18 Honeywell Inf Systems Controllable timing device for signalling the end of an interval
US4220990A (en) * 1978-09-25 1980-09-02 Bell Telephone Laboratories, Incorporated Peripheral processor multifunction timer for data processing systems
JPS56106421A (en) * 1980-01-29 1981-08-24 Nippon Hoso Kyokai <Nhk> Constant ratio delay circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2518405A (en) * 1946-11-18 1950-08-08 Hendrik C A Van Duuren Signal storing and code converting radio telegraph system
GB692412A (en) * 1948-04-30 1953-06-03 Standard Telephones Cables Ltd Improvements in or relating to telecommunication exchange systems
US2541932A (en) * 1948-05-19 1951-02-13 Bell Telephone Labor Inc Multiplex speech interpolation system
US2577141A (en) * 1948-06-10 1951-12-04 Eckert Mauchly Comp Corp Data translating apparatus
US2779933A (en) * 1950-03-29 1957-01-29 Itt Complex pulse communication system
US2669706A (en) * 1950-05-09 1954-02-16 Bell Telephone Labor Inc Code selector
GB722179A (en) * 1950-05-17
US2692303A (en) * 1950-12-19 1954-10-19 Bell Telephone Labor Inc Speech interpolated communication system
US2674733A (en) * 1952-12-02 1954-04-06 Hughes Tool Co Electronic sorting system
US2744955A (en) * 1953-08-24 1956-05-08 Rca Corp Reversible electronic code translators
US2827623A (en) * 1955-01-21 1958-03-18 Ernest F Ainsworth Magnetic tape inscriber-outscriber

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2604270A1 (en) * 1986-09-22 1988-03-25 Jutand Francis BINARY ADDITIONER HAVING FIXED OPERAND, AND PARALLEL-SERIAL BINARY MULTIPLIER COMPRISING SUCH ADDITIONER
EP0262032A1 (en) * 1986-09-22 1988-03-30 Francis Jutand Binary adder having a fixed operand, and a parallel/serial multiplier comprising such an adder
US4853887A (en) * 1986-09-22 1989-08-01 Francis Jutand Binary adder having a fixed operand and parallel-serial binary multiplier incorporating such an adder

Also Published As

Publication number Publication date
ES246497A1 (en) 1959-06-01
US2957945A (en) 1960-10-25
BE574121A (en) 1959-04-16
DE1183958B (en) 1964-12-23
FR1215377A (en) 1960-04-19
JPS372563B1 (en) 1962-05-24
NL234515A (en)

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